1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu-common.h"
28#include "cpu.h"
29#include "hw/hw.h"
30#include "hw/sysbus.h"
31#include "hw/pci/pci.h"
32#include "hw/pci/msi.h"
33#include "hw/pci/msix.h"
34#include "hw/pci/pci_host.h"
35#include "hw/ppc/spapr.h"
36#include "hw/pci-host/spapr.h"
37#include "exec/address-spaces.h"
38#include "exec/ram_addr.h"
39#include <libfdt.h>
40#include "trace.h"
41#include "qemu/error-report.h"
42#include "qapi/qmp/qerror.h"
43#include "hw/ppc/fdt.h"
44#include "hw/pci/pci_bridge.h"
45#include "hw/pci/pci_bus.h"
46#include "hw/pci/pci_ids.h"
47#include "hw/ppc/spapr_drc.h"
48#include "sysemu/device_tree.h"
49#include "sysemu/kvm.h"
50#include "sysemu/hostmem.h"
51#include "sysemu/numa.h"
52
53
54#define RTAS_QUERY_FN 0
55#define RTAS_CHANGE_FN 1
56#define RTAS_RESET_FN 2
57#define RTAS_CHANGE_MSI_FN 3
58#define RTAS_CHANGE_MSIX_FN 4
59
60
61#define RTAS_TYPE_MSI 1
62#define RTAS_TYPE_MSIX 2
63
64sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid)
65{
66 sPAPRPHBState *sphb;
67
68 QLIST_FOREACH(sphb, &spapr->phbs, list) {
69 if (sphb->buid != buid) {
70 continue;
71 }
72 return sphb;
73 }
74
75 return NULL;
76}
77
78PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
79 uint32_t config_addr)
80{
81 sPAPRPHBState *sphb = spapr_pci_find_phb(spapr, buid);
82 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
83 int bus_num = (config_addr >> 16) & 0xFF;
84 int devfn = (config_addr >> 8) & 0xFF;
85
86 if (!phb) {
87 return NULL;
88 }
89
90 return pci_find_device(phb->bus, bus_num, devfn);
91}
92
93static uint32_t rtas_pci_cfgaddr(uint32_t arg)
94{
95
96 return ((arg >> 20) & 0xf00) | (arg & 0xff);
97}
98
99static void finish_read_pci_config(sPAPRMachineState *spapr, uint64_t buid,
100 uint32_t addr, uint32_t size,
101 target_ulong rets)
102{
103 PCIDevice *pci_dev;
104 uint32_t val;
105
106 if ((size != 1) && (size != 2) && (size != 4)) {
107
108 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
109 return;
110 }
111
112 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
113 addr = rtas_pci_cfgaddr(addr);
114
115 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
116
117
118 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
119 return;
120 }
121
122 val = pci_host_config_read_common(pci_dev, addr,
123 pci_config_size(pci_dev), size);
124
125 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
126 rtas_st(rets, 1, val);
127}
128
129static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
130 uint32_t token, uint32_t nargs,
131 target_ulong args,
132 uint32_t nret, target_ulong rets)
133{
134 uint64_t buid;
135 uint32_t size, addr;
136
137 if ((nargs != 4) || (nret != 2)) {
138 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
139 return;
140 }
141
142 buid = rtas_ldq(args, 1);
143 size = rtas_ld(args, 3);
144 addr = rtas_ld(args, 0);
145
146 finish_read_pci_config(spapr, buid, addr, size, rets);
147}
148
149static void rtas_read_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
150 uint32_t token, uint32_t nargs,
151 target_ulong args,
152 uint32_t nret, target_ulong rets)
153{
154 uint32_t size, addr;
155
156 if ((nargs != 2) || (nret != 2)) {
157 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
158 return;
159 }
160
161 size = rtas_ld(args, 1);
162 addr = rtas_ld(args, 0);
163
164 finish_read_pci_config(spapr, 0, addr, size, rets);
165}
166
167static void finish_write_pci_config(sPAPRMachineState *spapr, uint64_t buid,
168 uint32_t addr, uint32_t size,
169 uint32_t val, target_ulong rets)
170{
171 PCIDevice *pci_dev;
172
173 if ((size != 1) && (size != 2) && (size != 4)) {
174
175 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
176 return;
177 }
178
179 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
180 addr = rtas_pci_cfgaddr(addr);
181
182 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
183
184
185 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
186 return;
187 }
188
189 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
190 val, size);
191
192 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
193}
194
195static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
196 uint32_t token, uint32_t nargs,
197 target_ulong args,
198 uint32_t nret, target_ulong rets)
199{
200 uint64_t buid;
201 uint32_t val, size, addr;
202
203 if ((nargs != 5) || (nret != 1)) {
204 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
205 return;
206 }
207
208 buid = rtas_ldq(args, 1);
209 val = rtas_ld(args, 4);
210 size = rtas_ld(args, 3);
211 addr = rtas_ld(args, 0);
212
213 finish_write_pci_config(spapr, buid, addr, size, val, rets);
214}
215
216static void rtas_write_pci_config(PowerPCCPU *cpu, sPAPRMachineState *spapr,
217 uint32_t token, uint32_t nargs,
218 target_ulong args,
219 uint32_t nret, target_ulong rets)
220{
221 uint32_t val, size, addr;
222
223 if ((nargs != 3) || (nret != 1)) {
224 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
225 return;
226 }
227
228
229 val = rtas_ld(args, 2);
230 size = rtas_ld(args, 1);
231 addr = rtas_ld(args, 0);
232
233 finish_write_pci_config(spapr, 0, addr, size, val, rets);
234}
235
236
237
238
239
240
241
242
243
244static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
245 unsigned first_irq, unsigned req_num)
246{
247 unsigned i;
248 MSIMessage msg = { .address = addr, .data = first_irq };
249
250 if (!msix) {
251 msi_set_message(pdev, msg);
252 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
253 return;
254 }
255
256 for (i = 0; i < req_num; ++i) {
257 msix_set_message(pdev, i, msg);
258 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
259 if (addr) {
260 ++msg.data;
261 }
262 }
263}
264
265static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
266 uint32_t token, uint32_t nargs,
267 target_ulong args, uint32_t nret,
268 target_ulong rets)
269{
270 uint32_t config_addr = rtas_ld(args, 0);
271 uint64_t buid = rtas_ldq(args, 1);
272 unsigned int func = rtas_ld(args, 3);
273 unsigned int req_num = rtas_ld(args, 4);
274 unsigned int seq_num = rtas_ld(args, 5);
275 unsigned int ret_intr_type;
276 unsigned int irq, max_irqs = 0;
277 sPAPRPHBState *phb = NULL;
278 PCIDevice *pdev = NULL;
279 spapr_pci_msi *msi;
280 int *config_addr_key;
281 Error *err = NULL;
282
283 switch (func) {
284 case RTAS_CHANGE_MSI_FN:
285 case RTAS_CHANGE_FN:
286 ret_intr_type = RTAS_TYPE_MSI;
287 break;
288 case RTAS_CHANGE_MSIX_FN:
289 ret_intr_type = RTAS_TYPE_MSIX;
290 break;
291 default:
292 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
293 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
294 return;
295 }
296
297
298 phb = spapr_pci_find_phb(spapr, buid);
299 if (phb) {
300 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
301 }
302 if (!phb || !pdev) {
303 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
304 return;
305 }
306
307 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
308
309
310 if (!req_num) {
311 if (!msi) {
312 trace_spapr_pci_msi("Releasing wrong config", config_addr);
313 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
314 return;
315 }
316
317 spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
318 if (msi_present(pdev)) {
319 spapr_msi_setmsg(pdev, 0, false, 0, 0);
320 }
321 if (msix_present(pdev)) {
322 spapr_msi_setmsg(pdev, 0, true, 0, 0);
323 }
324 g_hash_table_remove(phb->msi, &config_addr);
325
326 trace_spapr_pci_msi("Released MSIs", config_addr);
327 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
328 rtas_st(rets, 1, 0);
329 return;
330 }
331
332
333
334
335 if (ret_intr_type == RTAS_TYPE_MSI) {
336 max_irqs = msi_nr_vectors_allocated(pdev);
337 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
338 max_irqs = pdev->msix_entries_nr;
339 }
340 if (!max_irqs) {
341 error_report("Requested interrupt type %d is not enabled for device %x",
342 ret_intr_type, config_addr);
343 rtas_st(rets, 0, -1);
344 return;
345 }
346
347 if (req_num > max_irqs) {
348 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
349 req_num = max_irqs;
350 irq = 0;
351 goto out;
352 }
353
354
355 irq = spapr_ics_alloc_block(spapr->ics, req_num, false,
356 ret_intr_type == RTAS_TYPE_MSI, &err);
357 if (err) {
358 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
359 config_addr);
360 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
361 return;
362 }
363
364
365 if (msi) {
366 spapr_ics_free(spapr->ics, msi->first_irq, msi->num);
367 g_hash_table_remove(phb->msi, &config_addr);
368 }
369
370
371 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
372 irq, req_num);
373
374
375 msi = g_new(spapr_pci_msi, 1);
376 msi->first_irq = irq;
377 msi->num = req_num;
378 config_addr_key = g_new(int, 1);
379 *config_addr_key = config_addr;
380 g_hash_table_insert(phb->msi, config_addr_key, msi);
381
382out:
383 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
384 rtas_st(rets, 1, req_num);
385 rtas_st(rets, 2, ++seq_num);
386 if (nret > 3) {
387 rtas_st(rets, 3, ret_intr_type);
388 }
389
390 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
391}
392
393static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
394 sPAPRMachineState *spapr,
395 uint32_t token,
396 uint32_t nargs,
397 target_ulong args,
398 uint32_t nret,
399 target_ulong rets)
400{
401 uint32_t config_addr = rtas_ld(args, 0);
402 uint64_t buid = rtas_ldq(args, 1);
403 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
404 sPAPRPHBState *phb = NULL;
405 PCIDevice *pdev = NULL;
406 spapr_pci_msi *msi;
407
408
409 phb = spapr_pci_find_phb(spapr, buid);
410 if (phb) {
411 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
412 }
413 if (!phb || !pdev) {
414 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
415 return;
416 }
417
418
419 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr);
420 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
421 trace_spapr_pci_msi("Failed to return vector", config_addr);
422 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
423 return;
424 }
425 intr_src_num = msi->first_irq + ioa_intr_num;
426 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
427 intr_src_num);
428
429 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
430 rtas_st(rets, 1, intr_src_num);
431 rtas_st(rets, 2, 1);
432}
433
434static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
435 sPAPRMachineState *spapr,
436 uint32_t token, uint32_t nargs,
437 target_ulong args, uint32_t nret,
438 target_ulong rets)
439{
440 sPAPRPHBState *sphb;
441 uint32_t addr, option;
442 uint64_t buid;
443 int ret;
444
445 if ((nargs != 4) || (nret != 1)) {
446 goto param_error_exit;
447 }
448
449 buid = rtas_ldq(args, 1);
450 addr = rtas_ld(args, 0);
451 option = rtas_ld(args, 3);
452
453 sphb = spapr_pci_find_phb(spapr, buid);
454 if (!sphb) {
455 goto param_error_exit;
456 }
457
458 if (!spapr_phb_eeh_available(sphb)) {
459 goto param_error_exit;
460 }
461
462 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
463 rtas_st(rets, 0, ret);
464 return;
465
466param_error_exit:
467 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
468}
469
470static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
471 sPAPRMachineState *spapr,
472 uint32_t token, uint32_t nargs,
473 target_ulong args, uint32_t nret,
474 target_ulong rets)
475{
476 sPAPRPHBState *sphb;
477 PCIDevice *pdev;
478 uint32_t addr, option;
479 uint64_t buid;
480
481 if ((nargs != 4) || (nret != 2)) {
482 goto param_error_exit;
483 }
484
485 buid = rtas_ldq(args, 1);
486 sphb = spapr_pci_find_phb(spapr, buid);
487 if (!sphb) {
488 goto param_error_exit;
489 }
490
491 if (!spapr_phb_eeh_available(sphb)) {
492 goto param_error_exit;
493 }
494
495
496
497
498
499 option = rtas_ld(args, 3);
500 switch (option) {
501 case RTAS_GET_PE_ADDR:
502 addr = rtas_ld(args, 0);
503 pdev = spapr_pci_find_dev(spapr, buid, addr);
504 if (!pdev) {
505 goto param_error_exit;
506 }
507
508 rtas_st(rets, 1, (pci_bus_num(pdev->bus) << 16) + 1);
509 break;
510 case RTAS_GET_PE_MODE:
511 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
512 break;
513 default:
514 goto param_error_exit;
515 }
516
517 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
518 return;
519
520param_error_exit:
521 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
522}
523
524static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
525 sPAPRMachineState *spapr,
526 uint32_t token, uint32_t nargs,
527 target_ulong args, uint32_t nret,
528 target_ulong rets)
529{
530 sPAPRPHBState *sphb;
531 uint64_t buid;
532 int state, ret;
533
534 if ((nargs != 3) || (nret != 4 && nret != 5)) {
535 goto param_error_exit;
536 }
537
538 buid = rtas_ldq(args, 1);
539 sphb = spapr_pci_find_phb(spapr, buid);
540 if (!sphb) {
541 goto param_error_exit;
542 }
543
544 if (!spapr_phb_eeh_available(sphb)) {
545 goto param_error_exit;
546 }
547
548 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
549 rtas_st(rets, 0, ret);
550 if (ret != RTAS_OUT_SUCCESS) {
551 return;
552 }
553
554 rtas_st(rets, 1, state);
555 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
556 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
557 if (nret >= 5) {
558 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
559 }
560 return;
561
562param_error_exit:
563 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
564}
565
566static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
567 sPAPRMachineState *spapr,
568 uint32_t token, uint32_t nargs,
569 target_ulong args, uint32_t nret,
570 target_ulong rets)
571{
572 sPAPRPHBState *sphb;
573 uint32_t option;
574 uint64_t buid;
575 int ret;
576
577 if ((nargs != 4) || (nret != 1)) {
578 goto param_error_exit;
579 }
580
581 buid = rtas_ldq(args, 1);
582 option = rtas_ld(args, 3);
583 sphb = spapr_pci_find_phb(spapr, buid);
584 if (!sphb) {
585 goto param_error_exit;
586 }
587
588 if (!spapr_phb_eeh_available(sphb)) {
589 goto param_error_exit;
590 }
591
592 ret = spapr_phb_vfio_eeh_reset(sphb, option);
593 rtas_st(rets, 0, ret);
594 return;
595
596param_error_exit:
597 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
598}
599
600static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
601 sPAPRMachineState *spapr,
602 uint32_t token, uint32_t nargs,
603 target_ulong args, uint32_t nret,
604 target_ulong rets)
605{
606 sPAPRPHBState *sphb;
607 uint64_t buid;
608 int ret;
609
610 if ((nargs != 3) || (nret != 1)) {
611 goto param_error_exit;
612 }
613
614 buid = rtas_ldq(args, 1);
615 sphb = spapr_pci_find_phb(spapr, buid);
616 if (!sphb) {
617 goto param_error_exit;
618 }
619
620 if (!spapr_phb_eeh_available(sphb)) {
621 goto param_error_exit;
622 }
623
624 ret = spapr_phb_vfio_eeh_configure(sphb);
625 rtas_st(rets, 0, ret);
626 return;
627
628param_error_exit:
629 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
630}
631
632
633static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
634 sPAPRMachineState *spapr,
635 uint32_t token, uint32_t nargs,
636 target_ulong args, uint32_t nret,
637 target_ulong rets)
638{
639 sPAPRPHBState *sphb;
640 int option;
641 uint64_t buid;
642
643 if ((nargs != 8) || (nret != 1)) {
644 goto param_error_exit;
645 }
646
647 buid = rtas_ldq(args, 1);
648 sphb = spapr_pci_find_phb(spapr, buid);
649 if (!sphb) {
650 goto param_error_exit;
651 }
652
653 if (!spapr_phb_eeh_available(sphb)) {
654 goto param_error_exit;
655 }
656
657 option = rtas_ld(args, 7);
658 switch (option) {
659 case RTAS_SLOT_TEMP_ERR_LOG:
660 case RTAS_SLOT_PERM_ERR_LOG:
661 break;
662 default:
663 goto param_error_exit;
664 }
665
666
667 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
668 return;
669
670param_error_exit:
671 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
672}
673
674static int pci_spapr_swizzle(int slot, int pin)
675{
676 return (slot + pin) % PCI_NUM_PINS;
677}
678
679static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num)
680{
681
682
683
684
685
686
687 return pci_spapr_swizzle(PCI_SLOT(pci_dev->devfn), irq_num);
688}
689
690static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
691{
692
693
694
695
696 sPAPRPHBState *phb = opaque;
697
698 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
699 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
700}
701
702static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
703{
704 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
705 PCIINTxRoute route;
706
707 route.mode = PCI_INTX_ENABLED;
708 route.irq = sphb->lsi_table[pin].irq;
709
710 return route;
711}
712
713
714
715
716
717
718static void spapr_msi_write(void *opaque, hwaddr addr,
719 uint64_t data, unsigned size)
720{
721 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
722 uint32_t irq = data;
723
724 trace_spapr_pci_msi_write(addr, data, irq);
725
726 qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), irq));
727}
728
729static const MemoryRegionOps spapr_msi_ops = {
730
731 .read = NULL,
732 .write = spapr_msi_write,
733 .endianness = DEVICE_LITTLE_ENDIAN
734};
735
736
737
738
739static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
740{
741 sPAPRPHBState *phb = opaque;
742
743 return &phb->iommu_as;
744}
745
746static char *spapr_phb_vfio_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
747{
748 char *path = NULL, *buf = NULL, *host = NULL;
749
750
751 host = object_property_get_str(OBJECT(pdev), "host", NULL);
752 if (!host) {
753 goto err_out;
754 }
755
756
757 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
758 g_free(host);
759 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
760 goto err_out;
761 }
762 g_free(path);
763
764
765 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf);
766 g_free(buf);
767 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
768 goto err_out;
769 }
770 return buf;
771
772err_out:
773 g_free(path);
774 return NULL;
775}
776
777static char *spapr_phb_get_loc_code(sPAPRPHBState *sphb, PCIDevice *pdev)
778{
779 char *buf;
780 const char *devtype = "qemu";
781 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
782
783 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
784 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
785 if (buf) {
786 return buf;
787 }
788 devtype = "vfio";
789 }
790
791
792
793
794 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
795 devtype, pdev->name, sphb->index, busnr,
796 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
797 return buf;
798}
799
800
801#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
802#define b_n(x) b_x((x), 31, 1)
803#define b_p(x) b_x((x), 30, 1)
804#define b_t(x) b_x((x), 29, 1)
805#define b_ss(x) b_x((x), 24, 2)
806#define b_bbbbbbbb(x) b_x((x), 16, 8)
807#define b_ddddd(x) b_x((x), 11, 5)
808#define b_fff(x) b_x((x), 8, 3)
809#define b_rrrrrrrr(x) b_x((x), 0, 8)
810
811
812#define RESOURCE_CELLS_SIZE 2
813#define RESOURCE_CELLS_ADDRESS 3
814
815typedef struct ResourceFields {
816 uint32_t phys_hi;
817 uint32_t phys_mid;
818 uint32_t phys_lo;
819 uint32_t size_hi;
820 uint32_t size_lo;
821} QEMU_PACKED ResourceFields;
822
823typedef struct ResourceProps {
824 ResourceFields reg[8];
825 ResourceFields assigned[7];
826 uint32_t reg_len;
827 uint32_t assigned_len;
828} ResourceProps;
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
884{
885 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
886 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
887 b_ddddd(PCI_SLOT(d->devfn)) |
888 b_fff(PCI_FUNC(d->devfn)));
889 ResourceFields *reg, *assigned;
890 int i, reg_idx = 0, assigned_idx = 0;
891
892
893 reg = &rp->reg[reg_idx++];
894 reg->phys_hi = cpu_to_be32(dev_id);
895 reg->phys_mid = 0;
896 reg->phys_lo = 0;
897 reg->size_hi = 0;
898 reg->size_lo = 0;
899
900 for (i = 0; i < PCI_NUM_REGIONS; i++) {
901 if (!d->io_regions[i].size) {
902 continue;
903 }
904
905 reg = &rp->reg[reg_idx++];
906
907 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
908 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
909 reg->phys_hi |= cpu_to_be32(b_ss(1));
910 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
911 reg->phys_hi |= cpu_to_be32(b_ss(3));
912 } else {
913 reg->phys_hi |= cpu_to_be32(b_ss(2));
914 }
915 reg->phys_mid = 0;
916 reg->phys_lo = 0;
917 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
918 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
919
920 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) {
921 continue;
922 }
923
924 assigned = &rp->assigned[assigned_idx++];
925 assigned->phys_hi = cpu_to_be32(reg->phys_hi | b_n(1));
926 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32);
927 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr);
928 assigned->size_hi = reg->size_hi;
929 assigned->size_lo = reg->size_lo;
930 }
931
932 rp->reg_len = reg_idx * sizeof(ResourceFields);
933 rp->assigned_len = assigned_idx * sizeof(ResourceFields);
934}
935
936typedef struct PCIClass PCIClass;
937typedef struct PCISubClass PCISubClass;
938typedef struct PCIIFace PCIIFace;
939
940struct PCIIFace {
941 int iface;
942 const char *name;
943};
944
945struct PCISubClass {
946 int subclass;
947 const char *name;
948 const PCIIFace *iface;
949};
950
951struct PCIClass {
952 const char *name;
953 const PCISubClass *subc;
954};
955
956static const PCISubClass undef_subclass[] = {
957 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
958 { 0xFF, NULL, NULL },
959};
960
961static const PCISubClass mass_subclass[] = {
962 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
963 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
964 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
965 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
966 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
967 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
968 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
969 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
970 { 0xFF, NULL, NULL },
971};
972
973static const PCISubClass net_subclass[] = {
974 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
975 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
976 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
977 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
978 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
979 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
980 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
981 { 0xFF, NULL, NULL },
982};
983
984static const PCISubClass displ_subclass[] = {
985 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
986 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
987 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
988 { 0xFF, NULL, NULL },
989};
990
991static const PCISubClass media_subclass[] = {
992 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
993 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
994 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
995 { 0xFF, NULL, NULL },
996};
997
998static const PCISubClass mem_subclass[] = {
999 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1000 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1001 { 0xFF, NULL, NULL },
1002};
1003
1004static const PCISubClass bridg_subclass[] = {
1005 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1006 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1007 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1008 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1009 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1010 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1011 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1012 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1013 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1014 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1015 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1016 { 0xFF, NULL, NULL },
1017};
1018
1019static const PCISubClass comm_subclass[] = {
1020 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1021 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1022 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1023 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1024 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1025 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1026 { 0xFF, NULL, NULL, },
1027};
1028
1029static const PCIIFace pic_iface[] = {
1030 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1031 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1032 { 0xFF, NULL },
1033};
1034
1035static const PCISubClass sys_subclass[] = {
1036 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1037 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1038 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1039 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1040 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1041 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1042 { 0xFF, NULL, NULL },
1043};
1044
1045static const PCISubClass inp_subclass[] = {
1046 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1047 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1048 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1049 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1050 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1051 { 0xFF, NULL, NULL },
1052};
1053
1054static const PCISubClass dock_subclass[] = {
1055 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1056 { 0xFF, NULL, NULL },
1057};
1058
1059static const PCISubClass cpu_subclass[] = {
1060 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1061 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1062 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1063 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1064 { 0xFF, NULL, NULL },
1065};
1066
1067static const PCIIFace usb_iface[] = {
1068 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1069 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1070 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1071 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1072 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1073 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1074 { 0xFF, NULL },
1075};
1076
1077static const PCISubClass ser_subclass[] = {
1078 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1079 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1080 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1081 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1082 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1083 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1084 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1085 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1086 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1087 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1088 { 0xFF, NULL, NULL },
1089};
1090
1091static const PCISubClass wrl_subclass[] = {
1092 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1093 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1094 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1095 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1096 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1097 { 0xFF, NULL, NULL },
1098};
1099
1100static const PCISubClass sat_subclass[] = {
1101 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1102 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1103 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1104 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1105 { 0xFF, NULL, NULL },
1106};
1107
1108static const PCISubClass crypt_subclass[] = {
1109 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1110 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1111 "entertainment-encryption", NULL },
1112 { 0xFF, NULL, NULL },
1113};
1114
1115static const PCISubClass spc_subclass[] = {
1116 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1117 { PCI_CLASS_SP_PERF, "counter", NULL },
1118 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1119 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1120 { 0xFF, NULL, NULL },
1121};
1122
1123static const PCIClass pci_classes[] = {
1124 { "legacy-device", undef_subclass },
1125 { "mass-storage", mass_subclass },
1126 { "network", net_subclass },
1127 { "display", displ_subclass, },
1128 { "multimedia-device", media_subclass },
1129 { "memory-controller", mem_subclass },
1130 { "unknown-bridge", bridg_subclass },
1131 { "communication-controller", comm_subclass},
1132 { "system-peripheral", sys_subclass },
1133 { "input-controller", inp_subclass },
1134 { "docking-station", dock_subclass },
1135 { "cpu", cpu_subclass },
1136 { "serial-bus", ser_subclass },
1137 { "wireless-controller", wrl_subclass },
1138 { "intelligent-io", NULL },
1139 { "satellite-device", sat_subclass },
1140 { "encryption", crypt_subclass },
1141 { "data-processing-controller", spc_subclass },
1142};
1143
1144static const char *pci_find_device_name(uint8_t class, uint8_t subclass,
1145 uint8_t iface)
1146{
1147 const PCIClass *pclass;
1148 const PCISubClass *psubclass;
1149 const PCIIFace *piface;
1150 const char *name;
1151
1152 if (class >= ARRAY_SIZE(pci_classes)) {
1153 return "pci";
1154 }
1155
1156 pclass = pci_classes + class;
1157 name = pclass->name;
1158
1159 if (pclass->subc == NULL) {
1160 return name;
1161 }
1162
1163 psubclass = pclass->subc;
1164 while ((psubclass->subclass & 0xff) != 0xff) {
1165 if ((psubclass->subclass & 0xff) == subclass) {
1166 name = psubclass->name;
1167 break;
1168 }
1169 psubclass++;
1170 }
1171
1172 piface = psubclass->iface;
1173 if (piface == NULL) {
1174 return name;
1175 }
1176 while ((piface->iface & 0xff) != 0xff) {
1177 if ((piface->iface & 0xff) == iface) {
1178 name = piface->name;
1179 break;
1180 }
1181 piface++;
1182 }
1183
1184 return name;
1185}
1186
1187static gchar *pci_get_node_name(PCIDevice *dev)
1188{
1189 int slot = PCI_SLOT(dev->devfn);
1190 int func = PCI_FUNC(dev->devfn);
1191 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1192 const char *name;
1193
1194 name = pci_find_device_name((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1195 ccode & 0xff);
1196
1197 if (func != 0) {
1198 return g_strdup_printf("%s@%x,%x", name, slot, func);
1199 } else {
1200 return g_strdup_printf("%s@%x", name, slot);
1201 }
1202}
1203
1204static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1205 PCIDevice *pdev);
1206
1207static void spapr_populate_pci_child_dt(PCIDevice *dev, void *fdt, int offset,
1208 sPAPRPHBState *sphb)
1209{
1210 ResourceProps rp;
1211 bool is_bridge = false;
1212 int pci_status;
1213 char *buf = NULL;
1214 uint32_t drc_index = spapr_phb_get_pci_drc_index(sphb, dev);
1215 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1216 uint32_t max_msi, max_msix;
1217
1218 if (pci_default_read_config(dev, PCI_HEADER_TYPE, 1) ==
1219 PCI_HEADER_TYPE_BRIDGE) {
1220 is_bridge = true;
1221 }
1222
1223
1224 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id",
1225 pci_default_read_config(dev, PCI_VENDOR_ID, 2)));
1226 _FDT(fdt_setprop_cell(fdt, offset, "device-id",
1227 pci_default_read_config(dev, PCI_DEVICE_ID, 2)));
1228 _FDT(fdt_setprop_cell(fdt, offset, "revision-id",
1229 pci_default_read_config(dev, PCI_REVISION_ID, 1)));
1230 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1231 if (pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)) {
1232 _FDT(fdt_setprop_cell(fdt, offset, "interrupts",
1233 pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1)));
1234 }
1235
1236 if (!is_bridge) {
1237 _FDT(fdt_setprop_cell(fdt, offset, "min-grant",
1238 pci_default_read_config(dev, PCI_MIN_GNT, 1)));
1239 _FDT(fdt_setprop_cell(fdt, offset, "max-latency",
1240 pci_default_read_config(dev, PCI_MAX_LAT, 1)));
1241 }
1242
1243 if (pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)) {
1244 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id",
1245 pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2)));
1246 }
1247
1248 if (pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)) {
1249 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1250 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2)));
1251 }
1252
1253 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size",
1254 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1)));
1255
1256
1257 pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1258 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1259 PCI_STATUS_DEVSEL_MASK & pci_status));
1260
1261 if (pci_status & PCI_STATUS_FAST_BACK) {
1262 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1263 }
1264 if (pci_status & PCI_STATUS_66MHZ) {
1265 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1266 }
1267 if (pci_status & PCI_STATUS_UDF) {
1268 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1269 }
1270
1271 _FDT(fdt_setprop_string(fdt, offset, "name",
1272 pci_find_device_name((ccode >> 16) & 0xff,
1273 (ccode >> 8) & 0xff,
1274 ccode & 0xff)));
1275
1276 buf = spapr_phb_get_loc_code(sphb, dev);
1277 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", buf));
1278 g_free(buf);
1279
1280 if (drc_index) {
1281 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index));
1282 }
1283
1284 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1285 RESOURCE_CELLS_ADDRESS));
1286 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1287 RESOURCE_CELLS_SIZE));
1288
1289 max_msi = msi_nr_vectors_allocated(dev);
1290 if (max_msi) {
1291 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1292 }
1293 max_msix = dev->msix_entries_nr;
1294 if (max_msix) {
1295 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1296 }
1297
1298 populate_resource_props(dev, &rp);
1299 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1300 _FDT(fdt_setprop(fdt, offset, "assigned-addresses",
1301 (uint8_t *)rp.assigned, rp.assigned_len));
1302
1303 if (sphb->pcie_ecs && pci_is_express(dev)) {
1304 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1305 }
1306}
1307
1308
1309static int spapr_create_pci_child_dt(sPAPRPHBState *phb, PCIDevice *dev,
1310 void *fdt, int node_offset)
1311{
1312 int offset;
1313 gchar *nodename;
1314
1315 nodename = pci_get_node_name(dev);
1316 _FDT(offset = fdt_add_subnode(fdt, node_offset, nodename));
1317 g_free(nodename);
1318
1319 spapr_populate_pci_child_dt(dev, fdt, offset, phb);
1320
1321 return offset;
1322}
1323
1324
1325void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1326{
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337 pci_device_reset(PCI_DEVICE(dev));
1338 object_unparent(OBJECT(dev));
1339}
1340
1341static sPAPRDRConnector *spapr_phb_get_pci_func_drc(sPAPRPHBState *phb,
1342 uint32_t busnr,
1343 int32_t devfn)
1344{
1345 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1346 (phb->index << 16) | (busnr << 8) | devfn);
1347}
1348
1349static sPAPRDRConnector *spapr_phb_get_pci_drc(sPAPRPHBState *phb,
1350 PCIDevice *pdev)
1351{
1352 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
1353 return spapr_phb_get_pci_func_drc(phb, busnr, pdev->devfn);
1354}
1355
1356static uint32_t spapr_phb_get_pci_drc_index(sPAPRPHBState *phb,
1357 PCIDevice *pdev)
1358{
1359 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1360
1361 if (!drc) {
1362 return 0;
1363 }
1364
1365 return spapr_drc_index(drc);
1366}
1367
1368static void spapr_pci_plug(HotplugHandler *plug_handler,
1369 DeviceState *plugged_dev, Error **errp)
1370{
1371 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1372 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1373 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1374 Error *local_err = NULL;
1375 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1376 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1377 void *fdt = NULL;
1378 int fdt_start_offset, fdt_size;
1379
1380
1381
1382
1383 if (!phb->dr_enabled) {
1384
1385
1386
1387 if (plugged_dev->hotplugged) {
1388 error_setg(&local_err, QERR_BUS_NO_HOTPLUG,
1389 object_get_typename(OBJECT(phb)));
1390 }
1391 goto out;
1392 }
1393
1394 g_assert(drc);
1395
1396
1397
1398
1399
1400 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1401 PCI_FUNC(pdev->devfn) != 0) {
1402 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s,"
1403 " additional functions can no longer be exposed to guest.",
1404 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1405 goto out;
1406 }
1407
1408 fdt = create_device_tree(&fdt_size);
1409 fdt_start_offset = spapr_create_pci_child_dt(phb, pdev, fdt, 0);
1410
1411 spapr_drc_attach(drc, DEVICE(pdev), fdt, fdt_start_offset, &local_err);
1412 if (local_err) {
1413 goto out;
1414 }
1415
1416
1417
1418
1419 if (!spapr_drc_hotplugged(plugged_dev)) {
1420 spapr_drc_reset(drc);
1421 } else if (PCI_FUNC(pdev->devfn) == 0) {
1422 int i;
1423
1424 for (i = 0; i < 8; i++) {
1425 sPAPRDRConnector *func_drc;
1426 sPAPRDRConnectorClass *func_drck;
1427 sPAPRDREntitySense state;
1428
1429 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1430 PCI_DEVFN(slotnr, i));
1431 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1432 state = func_drck->dr_entity_sense(func_drc);
1433
1434 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1435 spapr_hotplug_req_add_by_index(func_drc);
1436 }
1437 }
1438 }
1439
1440out:
1441 if (local_err) {
1442 error_propagate(errp, local_err);
1443 g_free(fdt);
1444 }
1445}
1446
1447static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1448 DeviceState *plugged_dev, Error **errp)
1449{
1450 sPAPRPHBState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1451 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1452 sPAPRDRConnector *drc = spapr_phb_get_pci_drc(phb, pdev);
1453
1454 if (!phb->dr_enabled) {
1455 error_setg(errp, QERR_BUS_NO_HOTPLUG,
1456 object_get_typename(OBJECT(phb)));
1457 return;
1458 }
1459
1460 g_assert(drc);
1461 g_assert(drc->dev == plugged_dev);
1462
1463 if (!spapr_drc_unplug_requested(drc)) {
1464 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1465 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1466 sPAPRDRConnector *func_drc;
1467 sPAPRDRConnectorClass *func_drck;
1468 sPAPRDREntitySense state;
1469 int i;
1470
1471
1472 if (PCI_FUNC(pdev->devfn) == 0) {
1473 for (i = 1; i < 8; i++) {
1474 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1475 PCI_DEVFN(slotnr, i));
1476 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1477 state = func_drck->dr_entity_sense(func_drc);
1478 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1479 && !spapr_drc_unplug_requested(func_drc)) {
1480 error_setg(errp,
1481 "PCI: slot %d, function %d still present. "
1482 "Must unplug all non-0 functions first.",
1483 slotnr, i);
1484 return;
1485 }
1486 }
1487 }
1488
1489 spapr_drc_detach(drc);
1490
1491
1492
1493
1494 if (PCI_FUNC(pdev->devfn) == 0) {
1495 for (i = 7; i >= 0; i--) {
1496 func_drc = spapr_phb_get_pci_func_drc(phb, pci_bus_num(bus),
1497 PCI_DEVFN(slotnr, i));
1498 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1499 state = func_drck->dr_entity_sense(func_drc);
1500 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1501 spapr_hotplug_req_remove_by_index(func_drc);
1502 }
1503 }
1504 }
1505 }
1506}
1507
1508static void spapr_phb_realize(DeviceState *dev, Error **errp)
1509{
1510
1511
1512
1513 sPAPRMachineState *spapr =
1514 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
1515 TYPE_SPAPR_MACHINE);
1516 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1517 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(s);
1518 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1519 char *namebuf;
1520 int i;
1521 PCIBus *bus;
1522 uint64_t msi_window_size = 4096;
1523 sPAPRTCETable *tcet;
1524 const unsigned windows_supported =
1525 sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
1526
1527 if (!spapr) {
1528 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1529 return;
1530 }
1531
1532 if (sphb->index != (uint32_t)-1) {
1533 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1534 Error *local_err = NULL;
1535
1536 smc->phb_placement(spapr, sphb->index,
1537 &sphb->buid, &sphb->io_win_addr,
1538 &sphb->mem_win_addr, &sphb->mem64_win_addr,
1539 windows_supported, sphb->dma_liobn, &local_err);
1540 if (local_err) {
1541 error_propagate(errp, local_err);
1542 return;
1543 }
1544 } else {
1545 error_setg(errp, "\"index\" for PAPR PHB is mandatory");
1546 return;
1547 }
1548
1549 if (sphb->mem64_win_size != 0) {
1550 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1551 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1552 " (max 2 GiB)", sphb->mem_win_size);
1553 return;
1554 }
1555
1556
1557 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1558 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1559
1560
1561
1562
1563
1564
1565
1566 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE;
1567 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE;
1568 sphb->mem64_win_pciaddr =
1569 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE;
1570 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE;
1571 }
1572
1573 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1574 error_setg(errp, "PCI host bridges must have unique BUIDs");
1575 return;
1576 }
1577
1578 if (sphb->numa_node != -1 &&
1579 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) {
1580 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1581 return;
1582 }
1583
1584 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1585
1586
1587 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
1588 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1589 g_free(namebuf);
1590
1591 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
1592 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1593 namebuf, &sphb->memspace,
1594 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1595 g_free(namebuf);
1596 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1597 &sphb->mem32window);
1598
1599 if (sphb->mem64_win_size != 0) {
1600 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1601 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1602 namebuf, &sphb->memspace,
1603 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1604 g_free(namebuf);
1605
1606 memory_region_add_subregion(get_system_memory(),
1607 sphb->mem64_win_addr,
1608 &sphb->mem64window);
1609 }
1610
1611
1612 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
1613 memory_region_init(&sphb->iospace, OBJECT(sphb),
1614 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1615 g_free(namebuf);
1616
1617 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
1618 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1619 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1620 g_free(namebuf);
1621 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1622 &sphb->iowindow);
1623
1624 bus = pci_register_bus(dev, NULL,
1625 pci_spapr_set_irq, pci_spapr_map_irq, sphb,
1626 &sphb->memspace, &sphb->iospace,
1627 PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
1628 phb->bus = bus;
1629 qbus_set_hotplug_handler(BUS(phb->bus), DEVICE(sphb), NULL);
1630
1631
1632
1633
1634
1635
1636
1637
1638 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
1639 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1640 namebuf, UINT64_MAX);
1641 g_free(namebuf);
1642 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1643 sphb->dtbusname);
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656#ifdef CONFIG_KVM
1657 if (kvm_enabled()) {
1658 msi_window_size = getpagesize();
1659 }
1660#endif
1661
1662 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1663 "msi", msi_window_size);
1664 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1665 &sphb->msiwindow);
1666
1667 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
1668
1669 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1670
1671 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1672
1673
1674 for (i = 0; i < PCI_NUM_PINS; i++) {
1675 uint32_t irq;
1676 Error *local_err = NULL;
1677
1678 irq = spapr_ics_alloc_block(spapr->ics, 1, true, false, &local_err);
1679 if (local_err) {
1680 error_propagate(errp, local_err);
1681 error_prepend(errp, "can't allocate LSIs: ");
1682 return;
1683 }
1684
1685 sphb->lsi_table[i].irq = irq;
1686 }
1687
1688
1689 if (sphb->dr_enabled) {
1690 for (i = 0; i < PCI_SLOT_MAX * 8; i++) {
1691 spapr_dr_connector_new(OBJECT(phb), TYPE_SPAPR_DRC_PCI,
1692 (sphb->index << 16) | i);
1693 }
1694 }
1695
1696
1697 if (((sphb->page_size_mask & qemu_getrampagesize()) == 0)
1698 && kvm_enabled()) {
1699 error_report("System page size 0x%lx is not enabled in page_size_mask "
1700 "(0x%"PRIx64"). Performance may be slow",
1701 qemu_getrampagesize(), sphb->page_size_mask);
1702 }
1703
1704 for (i = 0; i < windows_supported; ++i) {
1705 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1706 if (!tcet) {
1707 error_setg(errp, "Creating window#%d failed for %s",
1708 i, sphb->dtbusname);
1709 return;
1710 }
1711 memory_region_add_subregion(&sphb->iommu_root, 0,
1712 spapr_tce_get_iommu(tcet));
1713 }
1714
1715 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free);
1716}
1717
1718static int spapr_phb_children_reset(Object *child, void *opaque)
1719{
1720 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1721
1722 if (dev) {
1723 device_reset(dev);
1724 }
1725
1726 return 0;
1727}
1728
1729void spapr_phb_dma_reset(sPAPRPHBState *sphb)
1730{
1731 int i;
1732 sPAPRTCETable *tcet;
1733
1734 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
1735 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1736
1737 if (tcet && tcet->nb_table) {
1738 spapr_tce_table_disable(tcet);
1739 }
1740 }
1741
1742
1743 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
1744 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
1745 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
1746}
1747
1748static void spapr_phb_reset(DeviceState *qdev)
1749{
1750 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
1751
1752 spapr_phb_dma_reset(sphb);
1753
1754
1755 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
1756
1757 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
1758 spapr_phb_vfio_reset(qdev);
1759 }
1760}
1761
1762static Property spapr_phb_properties[] = {
1763 DEFINE_PROP_UINT32("index", sPAPRPHBState, index, -1),
1764 DEFINE_PROP_UINT64("mem_win_size", sPAPRPHBState, mem_win_size,
1765 SPAPR_PCI_MEM32_WIN_SIZE),
1766 DEFINE_PROP_UINT64("mem64_win_size", sPAPRPHBState, mem64_win_size,
1767 SPAPR_PCI_MEM64_WIN_SIZE),
1768 DEFINE_PROP_UINT64("io_win_size", sPAPRPHBState, io_win_size,
1769 SPAPR_PCI_IO_WIN_SIZE),
1770 DEFINE_PROP_BOOL("dynamic-reconfiguration", sPAPRPHBState, dr_enabled,
1771 true),
1772
1773 DEFINE_PROP_UINT64("dma_win_addr", sPAPRPHBState, dma_win_addr, 0),
1774 DEFINE_PROP_UINT64("dma_win_size", sPAPRPHBState, dma_win_size, 0x40000000),
1775 DEFINE_PROP_UINT64("dma64_win_addr", sPAPRPHBState, dma64_win_addr,
1776 0x800000000000000ULL),
1777 DEFINE_PROP_BOOL("ddw", sPAPRPHBState, ddw_enabled, true),
1778 DEFINE_PROP_UINT64("pgsz", sPAPRPHBState, page_size_mask,
1779 (1ULL << 12) | (1ULL << 16)),
1780 DEFINE_PROP_UINT32("numa_node", sPAPRPHBState, numa_node, -1),
1781 DEFINE_PROP_BOOL("pre-2.8-migration", sPAPRPHBState,
1782 pre_2_8_migration, false),
1783 DEFINE_PROP_BOOL("pcie-extended-configuration-space", sPAPRPHBState,
1784 pcie_ecs, true),
1785 DEFINE_PROP_END_OF_LIST(),
1786};
1787
1788static const VMStateDescription vmstate_spapr_pci_lsi = {
1789 .name = "spapr_pci/lsi",
1790 .version_id = 1,
1791 .minimum_version_id = 1,
1792 .fields = (VMStateField[]) {
1793 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL),
1794
1795 VMSTATE_END_OF_LIST()
1796 },
1797};
1798
1799static const VMStateDescription vmstate_spapr_pci_msi = {
1800 .name = "spapr_pci/msi",
1801 .version_id = 1,
1802 .minimum_version_id = 1,
1803 .fields = (VMStateField []) {
1804 VMSTATE_UINT32(key, spapr_pci_msi_mig),
1805 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig),
1806 VMSTATE_UINT32(value.num, spapr_pci_msi_mig),
1807 VMSTATE_END_OF_LIST()
1808 },
1809};
1810
1811static int spapr_pci_pre_save(void *opaque)
1812{
1813 sPAPRPHBState *sphb = opaque;
1814 GHashTableIter iter;
1815 gpointer key, value;
1816 int i;
1817
1818 if (sphb->pre_2_8_migration) {
1819 sphb->mig_liobn = sphb->dma_liobn[0];
1820 sphb->mig_mem_win_addr = sphb->mem_win_addr;
1821 sphb->mig_mem_win_size = sphb->mem_win_size;
1822 sphb->mig_io_win_addr = sphb->io_win_addr;
1823 sphb->mig_io_win_size = sphb->io_win_size;
1824
1825 if ((sphb->mem64_win_size != 0)
1826 && (sphb->mem64_win_addr
1827 == (sphb->mem_win_addr + sphb->mem_win_size))) {
1828 sphb->mig_mem_win_size += sphb->mem64_win_size;
1829 }
1830 }
1831
1832 g_free(sphb->msi_devs);
1833 sphb->msi_devs = NULL;
1834 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
1835 if (!sphb->msi_devs_num) {
1836 return 0;
1837 }
1838 sphb->msi_devs = g_malloc(sphb->msi_devs_num * sizeof(spapr_pci_msi_mig));
1839
1840 g_hash_table_iter_init(&iter, sphb->msi);
1841 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
1842 sphb->msi_devs[i].key = *(uint32_t *) key;
1843 sphb->msi_devs[i].value = *(spapr_pci_msi *) value;
1844 }
1845
1846 return 0;
1847}
1848
1849static int spapr_pci_post_load(void *opaque, int version_id)
1850{
1851 sPAPRPHBState *sphb = opaque;
1852 gpointer key, value;
1853 int i;
1854
1855 for (i = 0; i < sphb->msi_devs_num; ++i) {
1856 key = g_memdup(&sphb->msi_devs[i].key,
1857 sizeof(sphb->msi_devs[i].key));
1858 value = g_memdup(&sphb->msi_devs[i].value,
1859 sizeof(sphb->msi_devs[i].value));
1860 g_hash_table_insert(sphb->msi, key, value);
1861 }
1862 g_free(sphb->msi_devs);
1863 sphb->msi_devs = NULL;
1864 sphb->msi_devs_num = 0;
1865
1866 return 0;
1867}
1868
1869static bool pre_2_8_migration(void *opaque, int version_id)
1870{
1871 sPAPRPHBState *sphb = opaque;
1872
1873 return sphb->pre_2_8_migration;
1874}
1875
1876static const VMStateDescription vmstate_spapr_pci = {
1877 .name = "spapr_pci",
1878 .version_id = 2,
1879 .minimum_version_id = 2,
1880 .pre_save = spapr_pci_pre_save,
1881 .post_load = spapr_pci_post_load,
1882 .fields = (VMStateField[]) {
1883 VMSTATE_UINT64_EQUAL(buid, sPAPRPHBState, NULL),
1884 VMSTATE_UINT32_TEST(mig_liobn, sPAPRPHBState, pre_2_8_migration),
1885 VMSTATE_UINT64_TEST(mig_mem_win_addr, sPAPRPHBState, pre_2_8_migration),
1886 VMSTATE_UINT64_TEST(mig_mem_win_size, sPAPRPHBState, pre_2_8_migration),
1887 VMSTATE_UINT64_TEST(mig_io_win_addr, sPAPRPHBState, pre_2_8_migration),
1888 VMSTATE_UINT64_TEST(mig_io_win_size, sPAPRPHBState, pre_2_8_migration),
1889 VMSTATE_STRUCT_ARRAY(lsi_table, sPAPRPHBState, PCI_NUM_PINS, 0,
1890 vmstate_spapr_pci_lsi, struct spapr_pci_lsi),
1891 VMSTATE_INT32(msi_devs_num, sPAPRPHBState),
1892 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, sPAPRPHBState, msi_devs_num, 0,
1893 vmstate_spapr_pci_msi, spapr_pci_msi_mig),
1894 VMSTATE_END_OF_LIST()
1895 },
1896};
1897
1898static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
1899 PCIBus *rootbus)
1900{
1901 sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
1902
1903 return sphb->dtbusname;
1904}
1905
1906static void spapr_phb_class_init(ObjectClass *klass, void *data)
1907{
1908 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
1909 DeviceClass *dc = DEVICE_CLASS(klass);
1910 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
1911
1912 hc->root_bus_path = spapr_phb_root_bus_path;
1913 dc->realize = spapr_phb_realize;
1914 dc->props = spapr_phb_properties;
1915 dc->reset = spapr_phb_reset;
1916 dc->vmsd = &vmstate_spapr_pci;
1917
1918 dc->user_creatable = true;
1919 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1920 hp->plug = spapr_pci_plug;
1921 hp->unplug_request = spapr_pci_unplug_request;
1922}
1923
1924static const TypeInfo spapr_phb_info = {
1925 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
1926 .parent = TYPE_PCI_HOST_BRIDGE,
1927 .instance_size = sizeof(sPAPRPHBState),
1928 .class_init = spapr_phb_class_init,
1929 .interfaces = (InterfaceInfo[]) {
1930 { TYPE_HOTPLUG_HANDLER },
1931 { }
1932 }
1933};
1934
1935PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index)
1936{
1937 DeviceState *dev;
1938
1939 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
1940 qdev_prop_set_uint32(dev, "index", index);
1941 qdev_init_nofail(dev);
1942
1943 return PCI_HOST_BRIDGE(dev);
1944}
1945
1946typedef struct sPAPRFDT {
1947 void *fdt;
1948 int node_off;
1949 sPAPRPHBState *sphb;
1950} sPAPRFDT;
1951
1952static void spapr_populate_pci_devices_dt(PCIBus *bus, PCIDevice *pdev,
1953 void *opaque)
1954{
1955 PCIBus *sec_bus;
1956 sPAPRFDT *p = opaque;
1957 int offset;
1958 sPAPRFDT s_fdt;
1959
1960 offset = spapr_create_pci_child_dt(p->sphb, pdev, p->fdt, p->node_off);
1961 if (!offset) {
1962 error_report("Failed to create pci child device tree node");
1963 return;
1964 }
1965
1966 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
1967 PCI_HEADER_TYPE_BRIDGE)) {
1968 return;
1969 }
1970
1971 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
1972 if (!sec_bus) {
1973 return;
1974 }
1975
1976 s_fdt.fdt = p->fdt;
1977 s_fdt.node_off = offset;
1978 s_fdt.sphb = p->sphb;
1979 pci_for_each_device_reverse(sec_bus, pci_bus_num(sec_bus),
1980 spapr_populate_pci_devices_dt,
1981 &s_fdt);
1982}
1983
1984static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
1985 void *opaque)
1986{
1987 unsigned int *bus_no = opaque;
1988 unsigned int primary = *bus_no;
1989 unsigned int subordinate = 0xff;
1990 PCIBus *sec_bus = NULL;
1991
1992 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
1993 PCI_HEADER_TYPE_BRIDGE)) {
1994 return;
1995 }
1996
1997 (*bus_no)++;
1998 pci_default_write_config(pdev, PCI_PRIMARY_BUS, primary, 1);
1999 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2000 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2001
2002 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2003 if (!sec_bus) {
2004 return;
2005 }
2006
2007 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, subordinate, 1);
2008 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
2009 spapr_phb_pci_enumerate_bridge, bus_no);
2010 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2011}
2012
2013static void spapr_phb_pci_enumerate(sPAPRPHBState *phb)
2014{
2015 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2016 unsigned int bus_no = 0;
2017
2018 pci_for_each_device(bus, pci_bus_num(bus),
2019 spapr_phb_pci_enumerate_bridge,
2020 &bus_no);
2021
2022}
2023
2024int spapr_populate_pci_dt(sPAPRPHBState *phb,
2025 uint32_t xics_phandle,
2026 void *fdt)
2027{
2028 int bus_off, i, j, ret;
2029 gchar *nodename;
2030 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2031 struct {
2032 uint32_t hi;
2033 uint64_t child;
2034 uint64_t parent;
2035 uint64_t size;
2036 } QEMU_PACKED ranges[] = {
2037 {
2038 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2039 cpu_to_be64(phb->io_win_addr),
2040 cpu_to_be64(memory_region_size(&phb->iospace)),
2041 },
2042 {
2043 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2044 cpu_to_be64(phb->mem_win_addr),
2045 cpu_to_be64(phb->mem_win_size),
2046 },
2047 {
2048 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2049 cpu_to_be64(phb->mem64_win_addr),
2050 cpu_to_be64(phb->mem64_win_size),
2051 },
2052 };
2053 const unsigned sizeof_ranges =
2054 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2055 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2056 uint32_t interrupt_map_mask[] = {
2057 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2058 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2059 uint32_t ddw_applicable[] = {
2060 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2061 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2062 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2063 };
2064 uint32_t ddw_extensions[] = {
2065 cpu_to_be32(1),
2066 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW)
2067 };
2068 uint32_t associativity[] = {cpu_to_be32(0x4),
2069 cpu_to_be32(0x0),
2070 cpu_to_be32(0x0),
2071 cpu_to_be32(0x0),
2072 cpu_to_be32(phb->numa_node)};
2073 sPAPRTCETable *tcet;
2074 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2075 sPAPRFDT s_fdt;
2076
2077
2078 nodename = g_strdup_printf("pci@%" PRIx64, phb->buid);
2079 _FDT(bus_off = fdt_add_subnode(fdt, 0, nodename));
2080 g_free(nodename);
2081
2082
2083 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2084 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2085 _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3));
2086 _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2));
2087 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2088 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2089 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2090 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2091 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2092 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2093 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR));
2094
2095
2096 if (phb->ddw_enabled) {
2097 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2098 sizeof(ddw_applicable)));
2099 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2100 &ddw_extensions, sizeof(ddw_extensions)));
2101 }
2102
2103
2104 if (phb->numa_node != -1) {
2105 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity,
2106 sizeof(associativity)));
2107 }
2108
2109
2110
2111
2112 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2113 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2114 for (i = 0; i < PCI_SLOT_MAX; i++) {
2115 for (j = 0; j < PCI_NUM_PINS; j++) {
2116 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2117 int lsi_num = pci_spapr_swizzle(i, j);
2118
2119 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2120 irqmap[1] = 0;
2121 irqmap[2] = 0;
2122 irqmap[3] = cpu_to_be32(j+1);
2123 irqmap[4] = cpu_to_be32(xics_phandle);
2124 irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq);
2125 irqmap[6] = cpu_to_be32(0x8);
2126 }
2127 }
2128
2129 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2130 sizeof(interrupt_map)));
2131
2132 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2133 if (!tcet) {
2134 return -1;
2135 }
2136 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2137 tcet->liobn, tcet->bus_offset,
2138 tcet->nb_table << tcet->page_shift);
2139
2140
2141 spapr_phb_pci_enumerate(phb);
2142 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2143
2144
2145 s_fdt.fdt = fdt;
2146 s_fdt.node_off = bus_off;
2147 s_fdt.sphb = phb;
2148 pci_for_each_device_reverse(bus, pci_bus_num(bus),
2149 spapr_populate_pci_devices_dt,
2150 &s_fdt);
2151
2152 ret = spapr_drc_populate_dt(fdt, bus_off, OBJECT(phb),
2153 SPAPR_DR_CONNECTOR_TYPE_PCI);
2154 if (ret) {
2155 return ret;
2156 }
2157
2158 return 0;
2159}
2160
2161void spapr_pci_rtas_init(void)
2162{
2163 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2164 rtas_read_pci_config);
2165 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2166 rtas_write_pci_config);
2167 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2168 rtas_ibm_read_pci_config);
2169 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2170 rtas_ibm_write_pci_config);
2171 if (msi_nonbroken) {
2172 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2173 "ibm,query-interrupt-source-number",
2174 rtas_ibm_query_interrupt_source_number);
2175 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2176 rtas_ibm_change_msi);
2177 }
2178
2179 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2180 "ibm,set-eeh-option",
2181 rtas_ibm_set_eeh_option);
2182 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2183 "ibm,get-config-addr-info2",
2184 rtas_ibm_get_config_addr_info2);
2185 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2186 "ibm,read-slot-reset-state2",
2187 rtas_ibm_read_slot_reset_state2);
2188 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2189 "ibm,set-slot-reset",
2190 rtas_ibm_set_slot_reset);
2191 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2192 "ibm,configure-pe",
2193 rtas_ibm_configure_pe);
2194 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2195 "ibm,slot-error-detail",
2196 rtas_ibm_slot_error_detail);
2197}
2198
2199static void spapr_pci_register_types(void)
2200{
2201 type_register_static(&spapr_phb_info);
2202}
2203
2204type_init(spapr_pci_register_types)
2205
2206static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2207{
2208 bool be = *(bool *)opaque;
2209
2210 if (object_dynamic_cast(OBJECT(dev), "VGA")
2211 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) {
2212 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer",
2213 &error_abort);
2214 }
2215 return 0;
2216}
2217
2218void spapr_pci_switch_vga(bool big_endian)
2219{
2220 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
2221 sPAPRPHBState *sphb;
2222
2223
2224
2225
2226
2227
2228 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2229 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2230 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2231 &big_endian);
2232 }
2233}
2234