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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "qemu-common.h"
25#include "hw/qdev-properties.h"
26#include "linux-user/syscall_defs.h"
27#include "exec/exec-all.h"
28
29static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
30 fprintf_function cpu_fprintf, int flags)
31{
32 static const char * const reg_names[TILEGX_R_COUNT] = {
33 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
34 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
35 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
36 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
37 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
38 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
39 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
40 };
41
42 TileGXCPU *cpu = TILEGX_CPU(cs);
43 CPUTLGState *env = &cpu->env;
44 int i;
45
46 for (i = 0; i < TILEGX_R_COUNT; i++) {
47 cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
48 reg_names[i], env->regs[i],
49 (i % 4) == 3 ? "\n" : " ");
50 }
51 cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
52 env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
53}
54
55static ObjectClass *tilegx_cpu_class_by_name(const char *cpu_model)
56{
57 return object_class_by_name(TYPE_TILEGX_CPU);
58}
59
60static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
61{
62 TileGXCPU *cpu = TILEGX_CPU(cs);
63
64 cpu->env.pc = value;
65}
66
67static bool tilegx_cpu_has_work(CPUState *cs)
68{
69 return true;
70}
71
72static void tilegx_cpu_reset(CPUState *s)
73{
74 TileGXCPU *cpu = TILEGX_CPU(s);
75 TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
76 CPUTLGState *env = &cpu->env;
77
78 tcc->parent_reset(s);
79
80 memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
81}
82
83static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
84{
85 CPUState *cs = CPU(dev);
86 TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
87 Error *local_err = NULL;
88
89 cpu_exec_realizefn(cs, &local_err);
90 if (local_err != NULL) {
91 error_propagate(errp, local_err);
92 return;
93 }
94
95 cpu_reset(cs);
96 qemu_init_vcpu(cs);
97
98 tcc->parent_realize(dev, errp);
99}
100
101static void tilegx_cpu_initfn(Object *obj)
102{
103 CPUState *cs = CPU(obj);
104 TileGXCPU *cpu = TILEGX_CPU(obj);
105 CPUTLGState *env = &cpu->env;
106
107 cs->env_ptr = env;
108}
109
110static void tilegx_cpu_do_interrupt(CPUState *cs)
111{
112 cs->exception_index = -1;
113}
114
115static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
116 int mmu_idx)
117{
118 TileGXCPU *cpu = TILEGX_CPU(cs);
119
120
121 cs->exception_index = TILEGX_EXCP_SIGNAL;
122 cpu->env.excaddr = address;
123 cpu->env.signo = TARGET_SIGSEGV;
124 cpu->env.sigcode = 0;
125
126 return 1;
127}
128
129static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
130{
131 if (interrupt_request & CPU_INTERRUPT_HARD) {
132 tilegx_cpu_do_interrupt(cs);
133 return true;
134 }
135 return false;
136}
137
138static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
139{
140 DeviceClass *dc = DEVICE_CLASS(oc);
141 CPUClass *cc = CPU_CLASS(oc);
142 TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
143
144 tcc->parent_realize = dc->realize;
145 dc->realize = tilegx_cpu_realizefn;
146
147 tcc->parent_reset = cc->reset;
148 cc->reset = tilegx_cpu_reset;
149
150 cc->class_by_name = tilegx_cpu_class_by_name;
151 cc->has_work = tilegx_cpu_has_work;
152 cc->do_interrupt = tilegx_cpu_do_interrupt;
153 cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
154 cc->dump_state = tilegx_cpu_dump_state;
155 cc->set_pc = tilegx_cpu_set_pc;
156 cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
157 cc->gdb_num_core_regs = 0;
158 cc->tcg_initialize = tilegx_tcg_init;
159}
160
161static const TypeInfo tilegx_cpu_type_info = {
162 .name = TYPE_TILEGX_CPU,
163 .parent = TYPE_CPU,
164 .instance_size = sizeof(TileGXCPU),
165 .instance_init = tilegx_cpu_initfn,
166 .class_size = sizeof(TileGXCPUClass),
167 .class_init = tilegx_cpu_class_init,
168};
169
170static void tilegx_cpu_register_types(void)
171{
172 type_register_static(&tilegx_cpu_type_info);
173}
174
175type_init(tilegx_cpu_register_types)
176