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18#include "qemu/osdep.h"
19
20#include "cpu.h"
21#include "exec/exec-all.h"
22
23enum {
24 TLBRET_DIRTY = -4,
25 TLBRET_INVALID = -3,
26 TLBRET_NOMATCH = -2,
27 TLBRET_BADADDR = -1,
28 TLBRET_MATCH = 0
29};
30
31#if defined(CONFIG_SOFTMMU)
32static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
33 int *prot, target_ulong address,
34 int rw, int access_type)
35{
36 int ret = TLBRET_MATCH;
37
38 *physical = address & 0xFFFFFFFF;
39 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
40
41 return ret;
42}
43#endif
44
45
46static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
47 int rw, int tlb_error)
48{
49}
50
51int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
52 int rw, int mmu_idx)
53{
54 TriCoreCPU *cpu = TRICORE_CPU(cs);
55 CPUTriCoreState *env = &cpu->env;
56 hwaddr physical;
57 int prot;
58 int access_type;
59 int ret = 0;
60
61 rw &= 1;
62 access_type = ACCESS_INT;
63 ret = get_physical_address(env, &physical, &prot,
64 address, rw, access_type);
65 qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
66 " prot %d\n", __func__, address, ret, physical, prot);
67
68 if (ret == TLBRET_MATCH) {
69 tlb_set_page(cs, address & TARGET_PAGE_MASK,
70 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
71 mmu_idx, TARGET_PAGE_SIZE);
72 ret = 0;
73 } else if (ret < 0) {
74 raise_mmu_exception(env, address, rw, ret);
75 ret = 1;
76 }
77
78 return ret;
79}
80
81static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
82{
83 ObjectClass *oc = data;
84 CPUListState *s = user_data;
85 const char *typename;
86 char *name;
87
88 typename = object_class_get_name(oc);
89 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU));
90 (*s->cpu_fprintf)(s->file, " %s\n",
91 name);
92 g_free(name);
93}
94
95void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
96{
97 CPUListState s = {
98 .file = f,
99 .cpu_fprintf = cpu_fprintf,
100 };
101 GSList *list;
102
103 list = object_class_get_list(TYPE_TRICORE_CPU, false);
104 (*cpu_fprintf)(f, "Available CPUs:\n");
105 g_slist_foreach(list, tricore_cpu_list_entry, &s);
106 g_slist_free(list);
107}
108
109void fpu_set_state(CPUTriCoreState *env)
110{
111 set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
112 set_flush_inputs_to_zero(1, &env->fp_status);
113 set_flush_to_zero(1, &env->fp_status);
114 set_default_nan_mode(1, &env->fp_status);
115}
116
117uint32_t psw_read(CPUTriCoreState *env)
118{
119
120 env->PSW &= 0x6ffffff;
121
122 env->PSW |= ((env->PSW_USB_C != 0) << 31);
123 env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
124 env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2);
125 env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3);
126 env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4);
127
128 return env->PSW;
129}
130
131void psw_write(CPUTriCoreState *env, uint32_t val)
132{
133 env->PSW_USB_C = (val & MASK_USB_C);
134 env->PSW_USB_V = (val & MASK_USB_V) << 1;
135 env->PSW_USB_SV = (val & MASK_USB_SV) << 2;
136 env->PSW_USB_AV = (val & MASK_USB_AV) << 3;
137 env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4;
138 env->PSW = val;
139
140 fpu_set_state(env);
141}
142