LXR qemu/target/xtensa/cpu.c

   1/*
   2 * QEMU Xtensa CPU
   3 *
   4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   5 * Copyright (c) 2012 SUSE LINUX Products GmbH
   6 * All rights reserved.
   7 *
   8 * Redistribution and use in source and binary forms, with or without
   9 * modification, are permitted provided that the following conditions are met:
  10 *     * Redistributions of source code must retain the above copyright
  11 *       notice, this list of conditions and the following disclaimer.
  12 *     * Redistributions in binary form must reproduce the above copyright
  13 *       notice, this list of conditions and the following disclaimer in the
  14 *       documentation and/or other materials provided with the distribution.
  15 *     * Neither the name of the Open Source and Linux Lab nor the
  16 *       names of its contributors may be used to endorse or promote products
  17 *       derived from this software without specific prior written permission.
  18 *
  19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 */
  30
  31#include "qemu/osdep.h"
  32#include "qapi/error.h"
  33#include "cpu.h"
  34#include "qemu-common.h"
  35#include "migration/vmstate.h"
  36#include "exec/exec-all.h"
  37
  38
  39static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
  40{
  41    XtensaCPU *cpu = XTENSA_CPU(cs);
  42
  43    cpu->env.pc = value;
  44}
  45
  46static bool xtensa_cpu_has_work(CPUState *cs)
  47{
  48    XtensaCPU *cpu = XTENSA_CPU(cs);
  49
  50    return !cpu->env.runstall && cpu->env.pending_irq_level;
  51}
  52
  53/* CPUClass::reset() */
  54static void xtensa_cpu_reset(CPUState *s)
  55{
  56    XtensaCPU *cpu = XTENSA_CPU(s);
  57    XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
  58    CPUXtensaState *env = &cpu->env;
  59
  60    xcc->parent_reset(s);
  61
  62    env->exception_taken = 0;
  63    env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
  64    env->sregs[LITBASE] &= ~1;
  65    env->sregs[PS] = xtensa_option_enabled(env->config,
  66            XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
  67    env->sregs[VECBASE] = env->config->vecbase;
  68    env->sregs[IBREAKENABLE] = 0;
  69    env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
  70    env->sregs[CACHEATTR] = 0x22222222;
  71    env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
  72            XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
  73    env->sregs[CONFIGID0] = env->config->configid[0];
  74    env->sregs[CONFIGID1] = env->config->configid[1];
  75
  76    env->pending_irq_level = 0;
  77    reset_mmu(env);
  78    s->halted = env->runstall;
  79}
  80
  81static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
  82{
  83    ObjectClass *oc;
  84    char *typename;
  85
  86    typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
  87    oc = object_class_by_name(typename);
  88    g_free(typename);
  89    if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
  90        object_class_is_abstract(oc)) {
  91        return NULL;
  92    }
  93    return oc;
  94}
  95
  96static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
  97{
  98    CPUState *cs = CPU(dev);
  99    XtensaCPU *cpu = XTENSA_CPU(dev);
 100    XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
 101    Error *local_err = NULL;
 102
 103    xtensa_irq_init(&cpu->env);
 104
 105    cpu_exec_realizefn(cs, &local_err);
 106    if (local_err != NULL) {
 107        error_propagate(errp, local_err);
 108        return;
 109    }
 110
 111    cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
 112
 113    qemu_init_vcpu(cs);
 114
 115    xcc->parent_realize(dev, errp);
 116}
 117
 118static void xtensa_cpu_initfn(Object *obj)
 119{
 120    CPUState *cs = CPU(obj);
 121    XtensaCPU *cpu = XTENSA_CPU(obj);
 122    XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
 123    CPUXtensaState *env = &cpu->env;
 124
 125    cs->env_ptr = env;
 126    env->config = xcc->config;
 127
 128    env->address_space_er = g_malloc(sizeof(*env->address_space_er));
 129    env->system_er = g_malloc(sizeof(*env->system_er));
 130    memory_region_init_io(env->system_er, NULL, NULL, env, "er",
 131                          UINT64_C(0x100000000));
 132    address_space_init(env->address_space_er, env->system_er, "ER");
 133}
 134
 135static const VMStateDescription vmstate_xtensa_cpu = {
 136    .name = "cpu",
 137    .unmigratable = 1,
 138};
 139
 140static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
 141{
 142    DeviceClass *dc = DEVICE_CLASS(oc);
 143    CPUClass *cc = CPU_CLASS(oc);
 144    XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
 145
 146    xcc->parent_realize = dc->realize;
 147    dc->realize = xtensa_cpu_realizefn;
 148
 149    xcc->parent_reset = cc->reset;
 150    cc->reset = xtensa_cpu_reset;
 151
 152    cc->class_by_name = xtensa_cpu_class_by_name;
 153    cc->has_work = xtensa_cpu_has_work;
 154    cc->do_interrupt = xtensa_cpu_do_interrupt;
 155    cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
 156    cc->dump_state = xtensa_cpu_dump_state;
 157    cc->set_pc = xtensa_cpu_set_pc;
 158    cc->gdb_read_register = xtensa_cpu_gdb_read_register;
 159    cc->gdb_write_register = xtensa_cpu_gdb_write_register;
 160    cc->gdb_stop_before_watchpoint = true;
 161#ifndef CONFIG_USER_ONLY
 162    cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
 163    cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
 164    cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
 165#endif
 166    cc->debug_excp_handler = xtensa_breakpoint_handler;
 167    cc->tcg_initialize = xtensa_translate_init;
 168    dc->vmsd = &vmstate_xtensa_cpu;
 169}
 170
 171static const TypeInfo xtensa_cpu_type_info = {
 172    .name = TYPE_XTENSA_CPU,
 173    .parent = TYPE_CPU,
 174    .instance_size = sizeof(XtensaCPU),
 175    .instance_init = xtensa_cpu_initfn,
 176    .abstract = true,
 177    .class_size = sizeof(XtensaCPUClass),
 178    .class_init = xtensa_cpu_class_init,
 179};
 180
 181static void xtensa_cpu_register_types(void)
 182{
 183    type_register_static(&xtensa_cpu_type_info);
 184}
 185
 186type_init(xtensa_cpu_register_types)
 187