qemu/hw/display/sm501.c
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   1/*
   2 * QEMU SM501 Device
   3 *
   4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
   5 * Copyright (c) 2016 BALATON Zoltan
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25
  26#include "qemu/osdep.h"
  27#include "qemu/cutils.h"
  28#include "qapi/error.h"
  29#include "qemu-common.h"
  30#include "cpu.h"
  31#include "hw/hw.h"
  32#include "hw/char/serial.h"
  33#include "ui/console.h"
  34#include "hw/devices.h"
  35#include "hw/sysbus.h"
  36#include "hw/pci/pci.h"
  37#include "qemu/range.h"
  38#include "ui/pixel_ops.h"
  39#include "exec/address-spaces.h"
  40
  41/*
  42 * Status: 2010/05/07
  43 *   - Minimum implementation for Linux console : mmio regs and CRT layer.
  44 *   - 2D graphics acceleration partially supported : only fill rectangle.
  45 *
  46 * Status: 2016/12/04
  47 *   - Misc fixes: endianness, hardware cursor
  48 *   - Panel support
  49 *
  50 * TODO:
  51 *   - Touch panel support
  52 *   - USB support
  53 *   - UART support
  54 *   - More 2D graphics engine support
  55 *   - Performance tuning
  56 */
  57
  58/*#define DEBUG_SM501*/
  59/*#define DEBUG_BITBLT*/
  60
  61#ifdef DEBUG_SM501
  62#define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
  63#else
  64#define SM501_DPRINTF(fmt, ...) do {} while (0)
  65#endif
  66
  67#define MMIO_BASE_OFFSET 0x3e00000
  68#define MMIO_SIZE 0x200000
  69#define DC_PALETTE_ENTRIES (0x400 * 3)
  70
  71/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
  72
  73/* System Configuration area */
  74/* System config base */
  75#define SM501_SYS_CONFIG                (0x000000)
  76
  77/* config 1 */
  78#define SM501_SYSTEM_CONTROL            (0x000000)
  79
  80#define SM501_SYSCTRL_PANEL_TRISTATE    (1 << 0)
  81#define SM501_SYSCTRL_MEM_TRISTATE      (1 << 1)
  82#define SM501_SYSCTRL_CRT_TRISTATE      (1 << 2)
  83
  84#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
  85#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
  86#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
  87#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
  88#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
  89
  90#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN  (1 << 6)
  91#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
  92#define SM501_SYSCTRL_PCI_SUBSYS_LOCK   (1 << 11)
  93#define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
  94
  95/* miscellaneous control */
  96
  97#define SM501_MISC_CONTROL              (0x000004)
  98
  99#define SM501_MISC_BUS_SH               (0x0)
 100#define SM501_MISC_BUS_PCI              (0x1)
 101#define SM501_MISC_BUS_XSCALE           (0x2)
 102#define SM501_MISC_BUS_NEC              (0x6)
 103#define SM501_MISC_BUS_MASK             (0x7)
 104
 105#define SM501_MISC_VR_62MB              (1 << 3)
 106#define SM501_MISC_CDR_RESET            (1 << 7)
 107#define SM501_MISC_USB_LB               (1 << 8)
 108#define SM501_MISC_USB_SLAVE            (1 << 9)
 109#define SM501_MISC_BL_1                 (1 << 10)
 110#define SM501_MISC_MC                   (1 << 11)
 111#define SM501_MISC_DAC_POWER            (1 << 12)
 112#define SM501_MISC_IRQ_INVERT           (1 << 16)
 113#define SM501_MISC_SH                   (1 << 17)
 114
 115#define SM501_MISC_HOLD_EMPTY           (0 << 18)
 116#define SM501_MISC_HOLD_8               (1 << 18)
 117#define SM501_MISC_HOLD_16              (2 << 18)
 118#define SM501_MISC_HOLD_24              (3 << 18)
 119#define SM501_MISC_HOLD_32              (4 << 18)
 120#define SM501_MISC_HOLD_MASK            (7 << 18)
 121
 122#define SM501_MISC_FREQ_12              (1 << 24)
 123#define SM501_MISC_PNL_24BIT            (1 << 25)
 124#define SM501_MISC_8051_LE              (1 << 26)
 125
 126
 127
 128#define SM501_GPIO31_0_CONTROL          (0x000008)
 129#define SM501_GPIO63_32_CONTROL         (0x00000C)
 130#define SM501_DRAM_CONTROL              (0x000010)
 131
 132/* command list */
 133#define SM501_ARBTRTN_CONTROL           (0x000014)
 134
 135/* command list */
 136#define SM501_COMMAND_LIST_STATUS       (0x000024)
 137
 138/* interrupt debug */
 139#define SM501_RAW_IRQ_STATUS            (0x000028)
 140#define SM501_RAW_IRQ_CLEAR             (0x000028)
 141#define SM501_IRQ_STATUS                (0x00002C)
 142#define SM501_IRQ_MASK                  (0x000030)
 143#define SM501_DEBUG_CONTROL             (0x000034)
 144
 145/* power management */
 146#define SM501_POWERMODE_P2X_SRC         (1 << 29)
 147#define SM501_POWERMODE_V2X_SRC         (1 << 20)
 148#define SM501_POWERMODE_M_SRC           (1 << 12)
 149#define SM501_POWERMODE_M1_SRC          (1 << 4)
 150
 151#define SM501_CURRENT_GATE              (0x000038)
 152#define SM501_CURRENT_CLOCK             (0x00003C)
 153#define SM501_POWER_MODE_0_GATE         (0x000040)
 154#define SM501_POWER_MODE_0_CLOCK        (0x000044)
 155#define SM501_POWER_MODE_1_GATE         (0x000048)
 156#define SM501_POWER_MODE_1_CLOCK        (0x00004C)
 157#define SM501_SLEEP_MODE_GATE           (0x000050)
 158#define SM501_POWER_MODE_CONTROL        (0x000054)
 159
 160/* power gates for units within the 501 */
 161#define SM501_GATE_HOST                 (0)
 162#define SM501_GATE_MEMORY               (1)
 163#define SM501_GATE_DISPLAY              (2)
 164#define SM501_GATE_2D_ENGINE            (3)
 165#define SM501_GATE_CSC                  (4)
 166#define SM501_GATE_ZVPORT               (5)
 167#define SM501_GATE_GPIO                 (6)
 168#define SM501_GATE_UART0                (7)
 169#define SM501_GATE_UART1                (8)
 170#define SM501_GATE_SSP                  (10)
 171#define SM501_GATE_USB_HOST             (11)
 172#define SM501_GATE_USB_GADGET           (12)
 173#define SM501_GATE_UCONTROLLER          (17)
 174#define SM501_GATE_AC97                 (18)
 175
 176/* panel clock */
 177#define SM501_CLOCK_P2XCLK              (24)
 178/* crt clock */
 179#define SM501_CLOCK_V2XCLK              (16)
 180/* main clock */
 181#define SM501_CLOCK_MCLK                (8)
 182/* SDRAM controller clock */
 183#define SM501_CLOCK_M1XCLK              (0)
 184
 185/* config 2 */
 186#define SM501_PCI_MASTER_BASE           (0x000058)
 187#define SM501_ENDIAN_CONTROL            (0x00005C)
 188#define SM501_DEVICEID                  (0x000060)
 189/* 0x050100A0 */
 190
 191#define SM501_DEVICEID_SM501            (0x05010000)
 192#define SM501_DEVICEID_IDMASK           (0xffff0000)
 193#define SM501_DEVICEID_REVMASK          (0x000000ff)
 194
 195#define SM501_PLLCLOCK_COUNT            (0x000064)
 196#define SM501_MISC_TIMING               (0x000068)
 197#define SM501_CURRENT_SDRAM_CLOCK       (0x00006C)
 198
 199#define SM501_PROGRAMMABLE_PLL_CONTROL  (0x000074)
 200
 201/* GPIO base */
 202#define SM501_GPIO                      (0x010000)
 203#define SM501_GPIO_DATA_LOW             (0x00)
 204#define SM501_GPIO_DATA_HIGH            (0x04)
 205#define SM501_GPIO_DDR_LOW              (0x08)
 206#define SM501_GPIO_DDR_HIGH             (0x0C)
 207#define SM501_GPIO_IRQ_SETUP            (0x10)
 208#define SM501_GPIO_IRQ_STATUS           (0x14)
 209#define SM501_GPIO_IRQ_RESET            (0x14)
 210
 211/* I2C controller base */
 212#define SM501_I2C                       (0x010040)
 213#define SM501_I2C_BYTE_COUNT            (0x00)
 214#define SM501_I2C_CONTROL               (0x01)
 215#define SM501_I2C_STATUS                (0x02)
 216#define SM501_I2C_RESET                 (0x02)
 217#define SM501_I2C_SLAVE_ADDRESS         (0x03)
 218#define SM501_I2C_DATA                  (0x04)
 219
 220/* SSP base */
 221#define SM501_SSP                       (0x020000)
 222
 223/* Uart 0 base */
 224#define SM501_UART0                     (0x030000)
 225
 226/* Uart 1 base */
 227#define SM501_UART1                     (0x030020)
 228
 229/* USB host port base */
 230#define SM501_USB_HOST                  (0x040000)
 231
 232/* USB slave/gadget base */
 233#define SM501_USB_GADGET                (0x060000)
 234
 235/* USB slave/gadget data port base */
 236#define SM501_USB_GADGET_DATA           (0x070000)
 237
 238/* Display controller/video engine base */
 239#define SM501_DC                        (0x080000)
 240
 241/* common defines for the SM501 address registers */
 242#define SM501_ADDR_FLIP                 (1 << 31)
 243#define SM501_ADDR_EXT                  (1 << 27)
 244#define SM501_ADDR_CS1                  (1 << 26)
 245#define SM501_ADDR_MASK                 (0x3f << 26)
 246
 247#define SM501_FIFO_MASK                 (0x3 << 16)
 248#define SM501_FIFO_1                    (0x0 << 16)
 249#define SM501_FIFO_3                    (0x1 << 16)
 250#define SM501_FIFO_7                    (0x2 << 16)
 251#define SM501_FIFO_11                   (0x3 << 16)
 252
 253/* common registers for panel and the crt */
 254#define SM501_OFF_DC_H_TOT              (0x000)
 255#define SM501_OFF_DC_V_TOT              (0x008)
 256#define SM501_OFF_DC_H_SYNC             (0x004)
 257#define SM501_OFF_DC_V_SYNC             (0x00C)
 258
 259#define SM501_DC_PANEL_CONTROL          (0x000)
 260
 261#define SM501_DC_PANEL_CONTROL_FPEN     (1 << 27)
 262#define SM501_DC_PANEL_CONTROL_BIAS     (1 << 26)
 263#define SM501_DC_PANEL_CONTROL_DATA     (1 << 25)
 264#define SM501_DC_PANEL_CONTROL_VDD      (1 << 24)
 265#define SM501_DC_PANEL_CONTROL_DP       (1 << 23)
 266
 267#define SM501_DC_PANEL_CONTROL_TFT_888  (0 << 21)
 268#define SM501_DC_PANEL_CONTROL_TFT_333  (1 << 21)
 269#define SM501_DC_PANEL_CONTROL_TFT_444  (2 << 21)
 270
 271#define SM501_DC_PANEL_CONTROL_DE       (1 << 20)
 272
 273#define SM501_DC_PANEL_CONTROL_LCD_TFT  (0 << 18)
 274#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
 275#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
 276
 277#define SM501_DC_PANEL_CONTROL_CP       (1 << 14)
 278#define SM501_DC_PANEL_CONTROL_VSP      (1 << 13)
 279#define SM501_DC_PANEL_CONTROL_HSP      (1 << 12)
 280#define SM501_DC_PANEL_CONTROL_CK       (1 << 9)
 281#define SM501_DC_PANEL_CONTROL_TE       (1 << 8)
 282#define SM501_DC_PANEL_CONTROL_VPD      (1 << 7)
 283#define SM501_DC_PANEL_CONTROL_VP       (1 << 6)
 284#define SM501_DC_PANEL_CONTROL_HPD      (1 << 5)
 285#define SM501_DC_PANEL_CONTROL_HP       (1 << 4)
 286#define SM501_DC_PANEL_CONTROL_GAMMA    (1 << 3)
 287#define SM501_DC_PANEL_CONTROL_EN       (1 << 2)
 288
 289#define SM501_DC_PANEL_CONTROL_8BPP     (0 << 0)
 290#define SM501_DC_PANEL_CONTROL_16BPP    (1 << 0)
 291#define SM501_DC_PANEL_CONTROL_32BPP    (2 << 0)
 292
 293
 294#define SM501_DC_PANEL_PANNING_CONTROL  (0x004)
 295#define SM501_DC_PANEL_COLOR_KEY        (0x008)
 296#define SM501_DC_PANEL_FB_ADDR          (0x00C)
 297#define SM501_DC_PANEL_FB_OFFSET        (0x010)
 298#define SM501_DC_PANEL_FB_WIDTH         (0x014)
 299#define SM501_DC_PANEL_FB_HEIGHT        (0x018)
 300#define SM501_DC_PANEL_TL_LOC           (0x01C)
 301#define SM501_DC_PANEL_BR_LOC           (0x020)
 302#define SM501_DC_PANEL_H_TOT            (0x024)
 303#define SM501_DC_PANEL_H_SYNC           (0x028)
 304#define SM501_DC_PANEL_V_TOT            (0x02C)
 305#define SM501_DC_PANEL_V_SYNC           (0x030)
 306#define SM501_DC_PANEL_CUR_LINE         (0x034)
 307
 308#define SM501_DC_VIDEO_CONTROL          (0x040)
 309#define SM501_DC_VIDEO_FB0_ADDR         (0x044)
 310#define SM501_DC_VIDEO_FB_WIDTH         (0x048)
 311#define SM501_DC_VIDEO_FB0_LAST_ADDR    (0x04C)
 312#define SM501_DC_VIDEO_TL_LOC           (0x050)
 313#define SM501_DC_VIDEO_BR_LOC           (0x054)
 314#define SM501_DC_VIDEO_SCALE            (0x058)
 315#define SM501_DC_VIDEO_INIT_SCALE       (0x05C)
 316#define SM501_DC_VIDEO_YUV_CONSTANTS    (0x060)
 317#define SM501_DC_VIDEO_FB1_ADDR         (0x064)
 318#define SM501_DC_VIDEO_FB1_LAST_ADDR    (0x068)
 319
 320#define SM501_DC_VIDEO_ALPHA_CONTROL    (0x080)
 321#define SM501_DC_VIDEO_ALPHA_FB_ADDR    (0x084)
 322#define SM501_DC_VIDEO_ALPHA_FB_OFFSET  (0x088)
 323#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
 324#define SM501_DC_VIDEO_ALPHA_TL_LOC     (0x090)
 325#define SM501_DC_VIDEO_ALPHA_BR_LOC     (0x094)
 326#define SM501_DC_VIDEO_ALPHA_SCALE      (0x098)
 327#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
 328#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
 329#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
 330
 331#define SM501_DC_PANEL_HWC_BASE         (0x0F0)
 332#define SM501_DC_PANEL_HWC_ADDR         (0x0F0)
 333#define SM501_DC_PANEL_HWC_LOC          (0x0F4)
 334#define SM501_DC_PANEL_HWC_COLOR_1_2    (0x0F8)
 335#define SM501_DC_PANEL_HWC_COLOR_3      (0x0FC)
 336
 337#define SM501_HWC_EN                    (1 << 31)
 338
 339#define SM501_OFF_HWC_ADDR              (0x00)
 340#define SM501_OFF_HWC_LOC               (0x04)
 341#define SM501_OFF_HWC_COLOR_1_2         (0x08)
 342#define SM501_OFF_HWC_COLOR_3           (0x0C)
 343
 344#define SM501_DC_ALPHA_CONTROL          (0x100)
 345#define SM501_DC_ALPHA_FB_ADDR          (0x104)
 346#define SM501_DC_ALPHA_FB_OFFSET        (0x108)
 347#define SM501_DC_ALPHA_TL_LOC           (0x10C)
 348#define SM501_DC_ALPHA_BR_LOC           (0x110)
 349#define SM501_DC_ALPHA_CHROMA_KEY       (0x114)
 350#define SM501_DC_ALPHA_COLOR_LOOKUP     (0x118)
 351
 352#define SM501_DC_CRT_CONTROL            (0x200)
 353
 354#define SM501_DC_CRT_CONTROL_TVP        (1 << 15)
 355#define SM501_DC_CRT_CONTROL_CP         (1 << 14)
 356#define SM501_DC_CRT_CONTROL_VSP        (1 << 13)
 357#define SM501_DC_CRT_CONTROL_HSP        (1 << 12)
 358#define SM501_DC_CRT_CONTROL_VS         (1 << 11)
 359#define SM501_DC_CRT_CONTROL_BLANK      (1 << 10)
 360#define SM501_DC_CRT_CONTROL_SEL        (1 << 9)
 361#define SM501_DC_CRT_CONTROL_TE         (1 << 8)
 362#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
 363#define SM501_DC_CRT_CONTROL_GAMMA      (1 << 3)
 364#define SM501_DC_CRT_CONTROL_ENABLE     (1 << 2)
 365
 366#define SM501_DC_CRT_CONTROL_8BPP       (0 << 0)
 367#define SM501_DC_CRT_CONTROL_16BPP      (1 << 0)
 368#define SM501_DC_CRT_CONTROL_32BPP      (2 << 0)
 369
 370#define SM501_DC_CRT_FB_ADDR            (0x204)
 371#define SM501_DC_CRT_FB_OFFSET          (0x208)
 372#define SM501_DC_CRT_H_TOT              (0x20C)
 373#define SM501_DC_CRT_H_SYNC             (0x210)
 374#define SM501_DC_CRT_V_TOT              (0x214)
 375#define SM501_DC_CRT_V_SYNC             (0x218)
 376#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
 377#define SM501_DC_CRT_CUR_LINE           (0x220)
 378#define SM501_DC_CRT_MONITOR_DETECT     (0x224)
 379
 380#define SM501_DC_CRT_HWC_BASE           (0x230)
 381#define SM501_DC_CRT_HWC_ADDR           (0x230)
 382#define SM501_DC_CRT_HWC_LOC            (0x234)
 383#define SM501_DC_CRT_HWC_COLOR_1_2      (0x238)
 384#define SM501_DC_CRT_HWC_COLOR_3        (0x23C)
 385
 386#define SM501_DC_PANEL_PALETTE          (0x400)
 387
 388#define SM501_DC_VIDEO_PALETTE          (0x800)
 389
 390#define SM501_DC_CRT_PALETTE            (0xC00)
 391
 392/* Zoom Video port base */
 393#define SM501_ZVPORT                    (0x090000)
 394
 395/* AC97/I2S base */
 396#define SM501_AC97                      (0x0A0000)
 397
 398/* 8051 micro controller base */
 399#define SM501_UCONTROLLER               (0x0B0000)
 400
 401/* 8051 micro controller SRAM base */
 402#define SM501_UCONTROLLER_SRAM          (0x0C0000)
 403
 404/* DMA base */
 405#define SM501_DMA                       (0x0D0000)
 406
 407/* 2d engine base */
 408#define SM501_2D_ENGINE                 (0x100000)
 409#define SM501_2D_SOURCE                 (0x00)
 410#define SM501_2D_DESTINATION            (0x04)
 411#define SM501_2D_DIMENSION              (0x08)
 412#define SM501_2D_CONTROL                (0x0C)
 413#define SM501_2D_PITCH                  (0x10)
 414#define SM501_2D_FOREGROUND             (0x14)
 415#define SM501_2D_BACKGROUND             (0x18)
 416#define SM501_2D_STRETCH                (0x1C)
 417#define SM501_2D_COLOR_COMPARE          (0x20)
 418#define SM501_2D_COLOR_COMPARE_MASK     (0x24)
 419#define SM501_2D_MASK                   (0x28)
 420#define SM501_2D_CLIP_TL                (0x2C)
 421#define SM501_2D_CLIP_BR                (0x30)
 422#define SM501_2D_MONO_PATTERN_LOW       (0x34)
 423#define SM501_2D_MONO_PATTERN_HIGH      (0x38)
 424#define SM501_2D_WINDOW_WIDTH           (0x3C)
 425#define SM501_2D_SOURCE_BASE            (0x40)
 426#define SM501_2D_DESTINATION_BASE       (0x44)
 427#define SM501_2D_ALPHA                  (0x48)
 428#define SM501_2D_WRAP                   (0x4C)
 429#define SM501_2D_STATUS                 (0x50)
 430
 431#define SM501_CSC_Y_SOURCE_BASE         (0xC8)
 432#define SM501_CSC_CONSTANTS             (0xCC)
 433#define SM501_CSC_Y_SOURCE_X            (0xD0)
 434#define SM501_CSC_Y_SOURCE_Y            (0xD4)
 435#define SM501_CSC_U_SOURCE_BASE         (0xD8)
 436#define SM501_CSC_V_SOURCE_BASE         (0xDC)
 437#define SM501_CSC_SOURCE_DIMENSION      (0xE0)
 438#define SM501_CSC_SOURCE_PITCH          (0xE4)
 439#define SM501_CSC_DESTINATION           (0xE8)
 440#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
 441#define SM501_CSC_DESTINATION_PITCH     (0xF0)
 442#define SM501_CSC_SCALE_FACTOR          (0xF4)
 443#define SM501_CSC_DESTINATION_BASE      (0xF8)
 444#define SM501_CSC_CONTROL               (0xFC)
 445
 446/* 2d engine data port base */
 447#define SM501_2D_ENGINE_DATA            (0x110000)
 448
 449/* end of register definitions */
 450
 451#define SM501_HWC_WIDTH                       (64)
 452#define SM501_HWC_HEIGHT                      (64)
 453
 454/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
 455static const uint32_t sm501_mem_local_size[] = {
 456    [0] = 4 * M_BYTE,
 457    [1] = 8 * M_BYTE,
 458    [2] = 16 * M_BYTE,
 459    [3] = 32 * M_BYTE,
 460    [4] = 64 * M_BYTE,
 461    [5] = 2 * M_BYTE,
 462};
 463#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
 464
 465typedef struct SM501State {
 466    /* graphic console status */
 467    QemuConsole *con;
 468
 469    /* status & internal resources */
 470    uint32_t local_mem_size_index;
 471    uint8_t *local_mem;
 472    MemoryRegion local_mem_region;
 473    MemoryRegion mmio_region;
 474    MemoryRegion system_config_region;
 475    MemoryRegion disp_ctrl_region;
 476    MemoryRegion twoD_engine_region;
 477    uint32_t last_width;
 478    uint32_t last_height;
 479
 480    /* mmio registers */
 481    uint32_t system_control;
 482    uint32_t misc_control;
 483    uint32_t gpio_31_0_control;
 484    uint32_t gpio_63_32_control;
 485    uint32_t dram_control;
 486    uint32_t arbitration_control;
 487    uint32_t irq_mask;
 488    uint32_t misc_timing;
 489    uint32_t power_mode_control;
 490
 491    uint32_t uart0_ier;
 492    uint32_t uart0_lcr;
 493    uint32_t uart0_mcr;
 494    uint32_t uart0_scr;
 495
 496    uint8_t dc_palette[DC_PALETTE_ENTRIES];
 497
 498    uint32_t dc_panel_control;
 499    uint32_t dc_panel_panning_control;
 500    uint32_t dc_panel_fb_addr;
 501    uint32_t dc_panel_fb_offset;
 502    uint32_t dc_panel_fb_width;
 503    uint32_t dc_panel_fb_height;
 504    uint32_t dc_panel_tl_location;
 505    uint32_t dc_panel_br_location;
 506    uint32_t dc_panel_h_total;
 507    uint32_t dc_panel_h_sync;
 508    uint32_t dc_panel_v_total;
 509    uint32_t dc_panel_v_sync;
 510
 511    uint32_t dc_panel_hwc_addr;
 512    uint32_t dc_panel_hwc_location;
 513    uint32_t dc_panel_hwc_color_1_2;
 514    uint32_t dc_panel_hwc_color_3;
 515
 516    uint32_t dc_video_control;
 517
 518    uint32_t dc_crt_control;
 519    uint32_t dc_crt_fb_addr;
 520    uint32_t dc_crt_fb_offset;
 521    uint32_t dc_crt_h_total;
 522    uint32_t dc_crt_h_sync;
 523    uint32_t dc_crt_v_total;
 524    uint32_t dc_crt_v_sync;
 525
 526    uint32_t dc_crt_hwc_addr;
 527    uint32_t dc_crt_hwc_location;
 528    uint32_t dc_crt_hwc_color_1_2;
 529    uint32_t dc_crt_hwc_color_3;
 530
 531    uint32_t twoD_source;
 532    uint32_t twoD_destination;
 533    uint32_t twoD_dimension;
 534    uint32_t twoD_control;
 535    uint32_t twoD_pitch;
 536    uint32_t twoD_foreground;
 537    uint32_t twoD_background;
 538    uint32_t twoD_stretch;
 539    uint32_t twoD_color_compare;
 540    uint32_t twoD_color_compare_mask;
 541    uint32_t twoD_mask;
 542    uint32_t twoD_clip_tl;
 543    uint32_t twoD_clip_br;
 544    uint32_t twoD_mono_pattern_low;
 545    uint32_t twoD_mono_pattern_high;
 546    uint32_t twoD_window_width;
 547    uint32_t twoD_source_base;
 548    uint32_t twoD_destination_base;
 549    uint32_t twoD_alpha;
 550    uint32_t twoD_wrap;
 551} SM501State;
 552
 553static uint32_t get_local_mem_size_index(uint32_t size)
 554{
 555    uint32_t norm_size = 0;
 556    int i, index = 0;
 557
 558    for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) {
 559        uint32_t new_size = sm501_mem_local_size[i];
 560        if (new_size >= size) {
 561            if (norm_size == 0 || norm_size > new_size) {
 562                norm_size = new_size;
 563                index = i;
 564            }
 565        }
 566    }
 567
 568    return index;
 569}
 570
 571static inline int get_width(SM501State *s, int crt)
 572{
 573    int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total;
 574    return (width & 0x00000FFF) + 1;
 575}
 576
 577static inline int get_height(SM501State *s, int crt)
 578{
 579    int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total;
 580    return (height & 0x00000FFF) + 1;
 581}
 582
 583static inline int get_bpp(SM501State *s, int crt)
 584{
 585    int bpp = crt ? s->dc_crt_control : s->dc_panel_control;
 586    return 1 << (bpp & 3);
 587}
 588
 589/**
 590 * Check the availability of hardware cursor.
 591 * @param crt  0 for PANEL, 1 for CRT.
 592 */
 593static inline int is_hwc_enabled(SM501State *state, int crt)
 594{
 595    uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
 596    return addr & SM501_HWC_EN;
 597}
 598
 599/**
 600 * Get the address which holds cursor pattern data.
 601 * @param crt  0 for PANEL, 1 for CRT.
 602 */
 603static inline uint8_t *get_hwc_address(SM501State *state, int crt)
 604{
 605    uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
 606    return state->local_mem + (addr & 0x03FFFFF0);
 607}
 608
 609/**
 610 * Get the cursor position in y coordinate.
 611 * @param crt  0 for PANEL, 1 for CRT.
 612 */
 613static inline uint32_t get_hwc_y(SM501State *state, int crt)
 614{
 615    uint32_t location = crt ? state->dc_crt_hwc_location
 616                            : state->dc_panel_hwc_location;
 617    return (location & 0x07FF0000) >> 16;
 618}
 619
 620/**
 621 * Get the cursor position in x coordinate.
 622 * @param crt  0 for PANEL, 1 for CRT.
 623 */
 624static inline uint32_t get_hwc_x(SM501State *state, int crt)
 625{
 626    uint32_t location = crt ? state->dc_crt_hwc_location
 627                            : state->dc_panel_hwc_location;
 628    return location & 0x000007FF;
 629}
 630
 631/**
 632 * Get the hardware cursor palette.
 633 * @param crt  0 for PANEL, 1 for CRT.
 634 * @param palette  pointer to a [3 * 3] array to store color values in
 635 */
 636static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette)
 637{
 638    int i;
 639    uint32_t color_reg;
 640    uint16_t rgb565;
 641
 642    for (i = 0; i < 3; i++) {
 643        if (i + 1 == 3) {
 644            color_reg = crt ? state->dc_crt_hwc_color_3
 645                            : state->dc_panel_hwc_color_3;
 646        } else {
 647            color_reg = crt ? state->dc_crt_hwc_color_1_2
 648                            : state->dc_panel_hwc_color_1_2;
 649        }
 650
 651        if (i + 1 == 2) {
 652            rgb565 = (color_reg >> 16) & 0xFFFF;
 653        } else {
 654            rgb565 = color_reg & 0xFFFF;
 655        }
 656        palette[i * 3 + 0] = (rgb565 << 3) & 0xf8; /* red */
 657        palette[i * 3 + 1] = (rgb565 >> 3) & 0xfc; /* green */
 658        palette[i * 3 + 2] = (rgb565 >> 8) & 0xf8; /* blue */
 659    }
 660}
 661
 662static inline void hwc_invalidate(SM501State *s, int crt)
 663{
 664    int w = get_width(s, crt);
 665    int h = get_height(s, crt);
 666    int bpp = get_bpp(s, crt);
 667    int start = get_hwc_y(s, crt);
 668    int end = MIN(h, start + SM501_HWC_HEIGHT) + 1;
 669
 670    start *= w * bpp;
 671    end *= w * bpp;
 672
 673    memory_region_set_dirty(&s->local_mem_region, start, end - start);
 674}
 675
 676static void sm501_2d_operation(SM501State *s)
 677{
 678    /* obtain operation parameters */
 679    int operation = (s->twoD_control >> 16) & 0x1f;
 680    int rtl = s->twoD_control & 0x8000000;
 681    int src_x = (s->twoD_source >> 16) & 0x01FFF;
 682    int src_y = s->twoD_source & 0xFFFF;
 683    int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
 684    int dst_y = s->twoD_destination & 0xFFFF;
 685    int operation_width = (s->twoD_dimension >> 16) & 0x1FFF;
 686    int operation_height = s->twoD_dimension & 0xFFFF;
 687    uint32_t color = s->twoD_foreground;
 688    int format_flags = (s->twoD_stretch >> 20) & 0x3;
 689    int addressing = (s->twoD_stretch >> 16) & 0xF;
 690
 691    /* get frame buffer info */
 692    uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
 693    uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
 694    int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
 695    int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
 696
 697    if (addressing != 0x0) {
 698        printf("%s: only XY addressing is supported.\n", __func__);
 699        abort();
 700    }
 701
 702    if ((s->twoD_source_base & 0x08000000) ||
 703        (s->twoD_destination_base & 0x08000000)) {
 704        printf("%s: only local memory is supported.\n", __func__);
 705        abort();
 706    }
 707
 708    switch (operation) {
 709    case 0x00: /* copy area */
 710#define COPY_AREA(_bpp, _pixel_type, rtl) {                                   \
 711        int y, x, index_d, index_s;                                           \
 712        for (y = 0; y < operation_height; y++) {                              \
 713            for (x = 0; x < operation_width; x++) {                           \
 714                if (rtl) {                                                    \
 715                    index_s = ((src_y - y) * src_width + src_x - x) * _bpp;   \
 716                    index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp;   \
 717                } else {                                                      \
 718                    index_s = ((src_y + y) * src_width + src_x + x) * _bpp;   \
 719                    index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp;   \
 720                }                                                             \
 721                *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\
 722            }                                                                 \
 723        }                                                                     \
 724    }
 725        switch (format_flags) {
 726        case 0:
 727            COPY_AREA(1, uint8_t, rtl);
 728            break;
 729        case 1:
 730            COPY_AREA(2, uint16_t, rtl);
 731            break;
 732        case 2:
 733            COPY_AREA(4, uint32_t, rtl);
 734            break;
 735        }
 736        break;
 737
 738    case 0x01: /* fill rectangle */
 739#define FILL_RECT(_bpp, _pixel_type) {                                      \
 740        int y, x;                                                           \
 741        for (y = 0; y < operation_height; y++) {                            \
 742            for (x = 0; x < operation_width; x++) {                         \
 743                int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp;   \
 744                *(_pixel_type *)&dst[index] = (_pixel_type)color;           \
 745            }                                                               \
 746        }                                                                   \
 747    }
 748
 749        switch (format_flags) {
 750        case 0:
 751            FILL_RECT(1, uint8_t);
 752            break;
 753        case 1:
 754            FILL_RECT(2, uint16_t);
 755            break;
 756        case 2:
 757            FILL_RECT(4, uint32_t);
 758            break;
 759        }
 760        break;
 761
 762    default:
 763        printf("non-implemented SM501 2D operation. %d\n", operation);
 764        abort();
 765        break;
 766    }
 767}
 768
 769static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
 770                                         unsigned size)
 771{
 772    SM501State *s = (SM501State *)opaque;
 773    uint32_t ret = 0;
 774    SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
 775
 776    switch (addr) {
 777    case SM501_SYSTEM_CONTROL:
 778        ret = s->system_control;
 779        break;
 780    case SM501_MISC_CONTROL:
 781        ret = s->misc_control;
 782        break;
 783    case SM501_GPIO31_0_CONTROL:
 784        ret = s->gpio_31_0_control;
 785        break;
 786    case SM501_GPIO63_32_CONTROL:
 787        ret = s->gpio_63_32_control;
 788        break;
 789    case SM501_DEVICEID:
 790        ret = 0x050100A0;
 791        break;
 792    case SM501_DRAM_CONTROL:
 793        ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
 794        break;
 795    case SM501_ARBTRTN_CONTROL:
 796        ret = s->arbitration_control;
 797        break;
 798    case SM501_IRQ_MASK:
 799        ret = s->irq_mask;
 800        break;
 801    case SM501_MISC_TIMING:
 802        /* TODO : simulate gate control */
 803        ret = s->misc_timing;
 804        break;
 805    case SM501_CURRENT_GATE:
 806        /* TODO : simulate gate control */
 807        ret = 0x00021807;
 808        break;
 809    case SM501_CURRENT_CLOCK:
 810        ret = 0x2A1A0A09;
 811        break;
 812    case SM501_POWER_MODE_CONTROL:
 813        ret = s->power_mode_control;
 814        break;
 815
 816    default:
 817        printf("sm501 system config : not implemented register read."
 818               " addr=%x\n", (int)addr);
 819        abort();
 820    }
 821
 822    return ret;
 823}
 824
 825static void sm501_system_config_write(void *opaque, hwaddr addr,
 826                                      uint64_t value, unsigned size)
 827{
 828    SM501State *s = (SM501State *)opaque;
 829    SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
 830                  (uint32_t)addr, (uint32_t)value);
 831
 832    switch (addr) {
 833    case SM501_SYSTEM_CONTROL:
 834        s->system_control = value & 0xE300B8F7;
 835        break;
 836    case SM501_MISC_CONTROL:
 837        s->misc_control = value & 0xFF7FFF20;
 838        break;
 839    case SM501_GPIO31_0_CONTROL:
 840        s->gpio_31_0_control = value;
 841        break;
 842    case SM501_GPIO63_32_CONTROL:
 843        s->gpio_63_32_control = value;
 844        break;
 845    case SM501_DRAM_CONTROL:
 846        s->local_mem_size_index = (value >> 13) & 0x7;
 847        /* TODO : check validity of size change */
 848        s->dram_control |=  value & 0x7FFFFFC3;
 849        break;
 850    case SM501_ARBTRTN_CONTROL:
 851        s->arbitration_control =  value & 0x37777777;
 852        break;
 853    case SM501_IRQ_MASK:
 854        s->irq_mask = value;
 855        break;
 856    case SM501_MISC_TIMING:
 857        s->misc_timing = value & 0xF31F1FFF;
 858        break;
 859    case SM501_POWER_MODE_0_GATE:
 860    case SM501_POWER_MODE_1_GATE:
 861    case SM501_POWER_MODE_0_CLOCK:
 862    case SM501_POWER_MODE_1_CLOCK:
 863        /* TODO : simulate gate & clock control */
 864        break;
 865    case SM501_POWER_MODE_CONTROL:
 866        s->power_mode_control = value & 0x00000003;
 867        break;
 868
 869    default:
 870        printf("sm501 system config : not implemented register write."
 871               " addr=%x, val=%x\n", (int)addr, (uint32_t)value);
 872        abort();
 873    }
 874}
 875
 876static const MemoryRegionOps sm501_system_config_ops = {
 877    .read = sm501_system_config_read,
 878    .write = sm501_system_config_write,
 879    .valid = {
 880        .min_access_size = 4,
 881        .max_access_size = 4,
 882    },
 883    .endianness = DEVICE_LITTLE_ENDIAN,
 884};
 885
 886static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
 887{
 888    SM501State *s = (SM501State *)opaque;
 889    SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
 890
 891    /* TODO : consider BYTE/WORD access */
 892    /* TODO : consider endian */
 893
 894    assert(range_covers_byte(0, 0x400 * 3, addr));
 895    return *(uint32_t *)&s->dc_palette[addr];
 896}
 897
 898static void sm501_palette_write(void *opaque, hwaddr addr,
 899                                uint32_t value)
 900{
 901    SM501State *s = (SM501State *)opaque;
 902    SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
 903                  (int)addr, value);
 904
 905    /* TODO : consider BYTE/WORD access */
 906    /* TODO : consider endian */
 907
 908    assert(range_covers_byte(0, 0x400 * 3, addr));
 909    *(uint32_t *)&s->dc_palette[addr] = value;
 910}
 911
 912static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
 913                                     unsigned size)
 914{
 915    SM501State *s = (SM501State *)opaque;
 916    uint32_t ret = 0;
 917    SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
 918
 919    switch (addr) {
 920
 921    case SM501_DC_PANEL_CONTROL:
 922        ret = s->dc_panel_control;
 923        break;
 924    case SM501_DC_PANEL_PANNING_CONTROL:
 925        ret = s->dc_panel_panning_control;
 926        break;
 927    case SM501_DC_PANEL_FB_ADDR:
 928        ret = s->dc_panel_fb_addr;
 929        break;
 930    case SM501_DC_PANEL_FB_OFFSET:
 931        ret = s->dc_panel_fb_offset;
 932        break;
 933    case SM501_DC_PANEL_FB_WIDTH:
 934        ret = s->dc_panel_fb_width;
 935        break;
 936    case SM501_DC_PANEL_FB_HEIGHT:
 937        ret = s->dc_panel_fb_height;
 938        break;
 939    case SM501_DC_PANEL_TL_LOC:
 940        ret = s->dc_panel_tl_location;
 941        break;
 942    case SM501_DC_PANEL_BR_LOC:
 943        ret = s->dc_panel_br_location;
 944        break;
 945
 946    case SM501_DC_PANEL_H_TOT:
 947        ret = s->dc_panel_h_total;
 948        break;
 949    case SM501_DC_PANEL_H_SYNC:
 950        ret = s->dc_panel_h_sync;
 951        break;
 952    case SM501_DC_PANEL_V_TOT:
 953        ret = s->dc_panel_v_total;
 954        break;
 955    case SM501_DC_PANEL_V_SYNC:
 956        ret = s->dc_panel_v_sync;
 957        break;
 958
 959    case SM501_DC_VIDEO_CONTROL:
 960        ret = s->dc_video_control;
 961        break;
 962
 963    case SM501_DC_CRT_CONTROL:
 964        ret = s->dc_crt_control;
 965        break;
 966    case SM501_DC_CRT_FB_ADDR:
 967        ret = s->dc_crt_fb_addr;
 968        break;
 969    case SM501_DC_CRT_FB_OFFSET:
 970        ret = s->dc_crt_fb_offset;
 971        break;
 972    case SM501_DC_CRT_H_TOT:
 973        ret = s->dc_crt_h_total;
 974        break;
 975    case SM501_DC_CRT_H_SYNC:
 976        ret = s->dc_crt_h_sync;
 977        break;
 978    case SM501_DC_CRT_V_TOT:
 979        ret = s->dc_crt_v_total;
 980        break;
 981    case SM501_DC_CRT_V_SYNC:
 982        ret = s->dc_crt_v_sync;
 983        break;
 984
 985    case SM501_DC_CRT_HWC_ADDR:
 986        ret = s->dc_crt_hwc_addr;
 987        break;
 988    case SM501_DC_CRT_HWC_LOC:
 989        ret = s->dc_crt_hwc_location;
 990        break;
 991    case SM501_DC_CRT_HWC_COLOR_1_2:
 992        ret = s->dc_crt_hwc_color_1_2;
 993        break;
 994    case SM501_DC_CRT_HWC_COLOR_3:
 995        ret = s->dc_crt_hwc_color_3;
 996        break;
 997
 998    case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
 999        ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
1000        break;
1001
1002    default:
1003        printf("sm501 disp ctrl : not implemented register read."
1004               " addr=%x\n", (int)addr);
1005        abort();
1006    }
1007
1008    return ret;
1009}
1010
1011static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
1012                                  uint64_t value, unsigned size)
1013{
1014    SM501State *s = (SM501State *)opaque;
1015    SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
1016                  (unsigned)addr, (unsigned)value);
1017
1018    switch (addr) {
1019    case SM501_DC_PANEL_CONTROL:
1020        s->dc_panel_control = value & 0x0FFF73FF;
1021        break;
1022    case SM501_DC_PANEL_PANNING_CONTROL:
1023        s->dc_panel_panning_control = value & 0xFF3FFF3F;
1024        break;
1025    case SM501_DC_PANEL_FB_ADDR:
1026        s->dc_panel_fb_addr = value & 0x8FFFFFF0;
1027        break;
1028    case SM501_DC_PANEL_FB_OFFSET:
1029        s->dc_panel_fb_offset = value & 0x3FF03FF0;
1030        break;
1031    case SM501_DC_PANEL_FB_WIDTH:
1032        s->dc_panel_fb_width = value & 0x0FFF0FFF;
1033        break;
1034    case SM501_DC_PANEL_FB_HEIGHT:
1035        s->dc_panel_fb_height = value & 0x0FFF0FFF;
1036        break;
1037    case SM501_DC_PANEL_TL_LOC:
1038        s->dc_panel_tl_location = value & 0x07FF07FF;
1039        break;
1040    case SM501_DC_PANEL_BR_LOC:
1041        s->dc_panel_br_location = value & 0x07FF07FF;
1042        break;
1043
1044    case SM501_DC_PANEL_H_TOT:
1045        s->dc_panel_h_total = value & 0x0FFF0FFF;
1046        break;
1047    case SM501_DC_PANEL_H_SYNC:
1048        s->dc_panel_h_sync = value & 0x00FF0FFF;
1049        break;
1050    case SM501_DC_PANEL_V_TOT:
1051        s->dc_panel_v_total = value & 0x0FFF0FFF;
1052        break;
1053    case SM501_DC_PANEL_V_SYNC:
1054        s->dc_panel_v_sync = value & 0x003F0FFF;
1055        break;
1056
1057    case SM501_DC_PANEL_HWC_ADDR:
1058        value &= 0x8FFFFFF0;
1059        if (value != s->dc_panel_hwc_addr) {
1060            hwc_invalidate(s, 0);
1061            s->dc_panel_hwc_addr = value;
1062        }
1063        break;
1064    case SM501_DC_PANEL_HWC_LOC:
1065        value &= 0x0FFF0FFF;
1066        if (value != s->dc_panel_hwc_location) {
1067            hwc_invalidate(s, 0);
1068            s->dc_panel_hwc_location = value;
1069        }
1070        break;
1071    case SM501_DC_PANEL_HWC_COLOR_1_2:
1072        s->dc_panel_hwc_color_1_2 = value;
1073        break;
1074    case SM501_DC_PANEL_HWC_COLOR_3:
1075        s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
1076        break;
1077
1078    case SM501_DC_VIDEO_CONTROL:
1079        s->dc_video_control = value & 0x00037FFF;
1080        break;
1081
1082    case SM501_DC_CRT_CONTROL:
1083        s->dc_crt_control = value & 0x0003FFFF;
1084        break;
1085    case SM501_DC_CRT_FB_ADDR:
1086        s->dc_crt_fb_addr = value & 0x8FFFFFF0;
1087        break;
1088    case SM501_DC_CRT_FB_OFFSET:
1089        s->dc_crt_fb_offset = value & 0x3FF03FF0;
1090        break;
1091    case SM501_DC_CRT_H_TOT:
1092        s->dc_crt_h_total = value & 0x0FFF0FFF;
1093        break;
1094    case SM501_DC_CRT_H_SYNC:
1095        s->dc_crt_h_sync = value & 0x00FF0FFF;
1096        break;
1097    case SM501_DC_CRT_V_TOT:
1098        s->dc_crt_v_total = value & 0x0FFF0FFF;
1099        break;
1100    case SM501_DC_CRT_V_SYNC:
1101        s->dc_crt_v_sync = value & 0x003F0FFF;
1102        break;
1103
1104    case SM501_DC_CRT_HWC_ADDR:
1105        value &= 0x8FFFFFF0;
1106        if (value != s->dc_crt_hwc_addr) {
1107            hwc_invalidate(s, 1);
1108            s->dc_crt_hwc_addr = value;
1109        }
1110        break;
1111    case SM501_DC_CRT_HWC_LOC:
1112        value &= 0x0FFF0FFF;
1113        if (value != s->dc_crt_hwc_location) {
1114            hwc_invalidate(s, 1);
1115            s->dc_crt_hwc_location = value;
1116        }
1117        break;
1118    case SM501_DC_CRT_HWC_COLOR_1_2:
1119        s->dc_crt_hwc_color_1_2 = value;
1120        break;
1121    case SM501_DC_CRT_HWC_COLOR_3:
1122        s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
1123        break;
1124
1125    case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1126        sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
1127        break;
1128
1129    default:
1130        printf("sm501 disp ctrl : not implemented register write."
1131               " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1132        abort();
1133    }
1134}
1135
1136static const MemoryRegionOps sm501_disp_ctrl_ops = {
1137    .read = sm501_disp_ctrl_read,
1138    .write = sm501_disp_ctrl_write,
1139    .valid = {
1140        .min_access_size = 4,
1141        .max_access_size = 4,
1142    },
1143    .endianness = DEVICE_LITTLE_ENDIAN,
1144};
1145
1146static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
1147                                     unsigned size)
1148{
1149    SM501State *s = (SM501State *)opaque;
1150    uint32_t ret = 0;
1151    SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr);
1152
1153    switch (addr) {
1154    case SM501_2D_SOURCE:
1155        ret = s->twoD_source;
1156        break;
1157    case SM501_2D_DESTINATION:
1158        ret = s->twoD_destination;
1159        break;
1160    case SM501_2D_DIMENSION:
1161        ret = s->twoD_dimension;
1162        break;
1163    case SM501_2D_CONTROL:
1164        ret = s->twoD_control;
1165        break;
1166    case SM501_2D_PITCH:
1167        ret = s->twoD_pitch;
1168        break;
1169    case SM501_2D_FOREGROUND:
1170        ret = s->twoD_foreground;
1171        break;
1172    case SM501_2D_BACKGROUND:
1173        ret = s->twoD_background;
1174        break;
1175    case SM501_2D_STRETCH:
1176        ret = s->twoD_stretch;
1177        break;
1178    case SM501_2D_COLOR_COMPARE:
1179        ret = s->twoD_color_compare;
1180        break;
1181    case SM501_2D_COLOR_COMPARE_MASK:
1182        ret = s->twoD_color_compare_mask;
1183        break;
1184    case SM501_2D_MASK:
1185        ret = s->twoD_mask;
1186        break;
1187    case SM501_2D_CLIP_TL:
1188        ret = s->twoD_clip_tl;
1189        break;
1190    case SM501_2D_CLIP_BR:
1191        ret = s->twoD_clip_br;
1192        break;
1193    case SM501_2D_MONO_PATTERN_LOW:
1194        ret = s->twoD_mono_pattern_low;
1195        break;
1196    case SM501_2D_MONO_PATTERN_HIGH:
1197        ret = s->twoD_mono_pattern_high;
1198        break;
1199    case SM501_2D_WINDOW_WIDTH:
1200        ret = s->twoD_window_width;
1201        break;
1202    case SM501_2D_SOURCE_BASE:
1203        ret = s->twoD_source_base;
1204        break;
1205    case SM501_2D_DESTINATION_BASE:
1206        ret = s->twoD_destination_base;
1207        break;
1208    case SM501_2D_ALPHA:
1209        ret = s->twoD_alpha;
1210        break;
1211    case SM501_2D_WRAP:
1212        ret = s->twoD_wrap;
1213        break;
1214    case SM501_2D_STATUS:
1215        ret = 0; /* Should return interrupt status */
1216        break;
1217    default:
1218        printf("sm501 disp ctrl : not implemented register read."
1219               " addr=%x\n", (int)addr);
1220        abort();
1221    }
1222
1223    return ret;
1224}
1225
1226static void sm501_2d_engine_write(void *opaque, hwaddr addr,
1227                                  uint64_t value, unsigned size)
1228{
1229    SM501State *s = (SM501State *)opaque;
1230    SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
1231                  (unsigned)addr, (unsigned)value);
1232
1233    switch (addr) {
1234    case SM501_2D_SOURCE:
1235        s->twoD_source = value;
1236        break;
1237    case SM501_2D_DESTINATION:
1238        s->twoD_destination = value;
1239        break;
1240    case SM501_2D_DIMENSION:
1241        s->twoD_dimension = value;
1242        break;
1243    case SM501_2D_CONTROL:
1244        s->twoD_control = value;
1245
1246        /* do 2d operation if start flag is set. */
1247        if (value & 0x80000000) {
1248            sm501_2d_operation(s);
1249            s->twoD_control &= ~0x80000000; /* start flag down */
1250        }
1251
1252        break;
1253    case SM501_2D_PITCH:
1254        s->twoD_pitch = value;
1255        break;
1256    case SM501_2D_FOREGROUND:
1257        s->twoD_foreground = value;
1258        break;
1259    case SM501_2D_BACKGROUND:
1260        s->twoD_background = value;
1261        break;
1262    case SM501_2D_STRETCH:
1263        s->twoD_stretch = value;
1264        break;
1265    case SM501_2D_COLOR_COMPARE:
1266        s->twoD_color_compare = value;
1267        break;
1268    case SM501_2D_COLOR_COMPARE_MASK:
1269        s->twoD_color_compare_mask = value;
1270        break;
1271    case SM501_2D_MASK:
1272        s->twoD_mask = value;
1273        break;
1274    case SM501_2D_CLIP_TL:
1275        s->twoD_clip_tl = value;
1276        break;
1277    case SM501_2D_CLIP_BR:
1278        s->twoD_clip_br = value;
1279        break;
1280    case SM501_2D_MONO_PATTERN_LOW:
1281        s->twoD_mono_pattern_low = value;
1282        break;
1283    case SM501_2D_MONO_PATTERN_HIGH:
1284        s->twoD_mono_pattern_high = value;
1285        break;
1286    case SM501_2D_WINDOW_WIDTH:
1287        s->twoD_window_width = value;
1288        break;
1289    case SM501_2D_SOURCE_BASE:
1290        s->twoD_source_base = value;
1291        break;
1292    case SM501_2D_DESTINATION_BASE:
1293        s->twoD_destination_base = value;
1294        break;
1295    case SM501_2D_ALPHA:
1296        s->twoD_alpha = value;
1297        break;
1298    case SM501_2D_WRAP:
1299        s->twoD_wrap = value;
1300        break;
1301    case SM501_2D_STATUS:
1302        /* ignored, writing 0 should clear interrupt status */
1303        break;
1304    default:
1305        printf("sm501 2d engine : not implemented register write."
1306               " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1307        abort();
1308    }
1309}
1310
1311static const MemoryRegionOps sm501_2d_engine_ops = {
1312    .read = sm501_2d_engine_read,
1313    .write = sm501_2d_engine_write,
1314    .valid = {
1315        .min_access_size = 4,
1316        .max_access_size = 4,
1317    },
1318    .endianness = DEVICE_LITTLE_ENDIAN,
1319};
1320
1321/* draw line functions for all console modes */
1322
1323typedef void draw_line_func(uint8_t *d, const uint8_t *s,
1324                            int width, const uint32_t *pal);
1325
1326typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s,
1327                                int width, const uint8_t *palette,
1328                                int c_x, int c_y);
1329
1330#define DEPTH 8
1331#include "sm501_template.h"
1332
1333#define DEPTH 15
1334#include "sm501_template.h"
1335
1336#define BGR_FORMAT
1337#define DEPTH 15
1338#include "sm501_template.h"
1339
1340#define DEPTH 16
1341#include "sm501_template.h"
1342
1343#define BGR_FORMAT
1344#define DEPTH 16
1345#include "sm501_template.h"
1346
1347#define DEPTH 32
1348#include "sm501_template.h"
1349
1350#define BGR_FORMAT
1351#define DEPTH 32
1352#include "sm501_template.h"
1353
1354static draw_line_func *draw_line8_funcs[] = {
1355    draw_line8_8,
1356    draw_line8_15,
1357    draw_line8_16,
1358    draw_line8_32,
1359    draw_line8_32bgr,
1360    draw_line8_15bgr,
1361    draw_line8_16bgr,
1362};
1363
1364static draw_line_func *draw_line16_funcs[] = {
1365    draw_line16_8,
1366    draw_line16_15,
1367    draw_line16_16,
1368    draw_line16_32,
1369    draw_line16_32bgr,
1370    draw_line16_15bgr,
1371    draw_line16_16bgr,
1372};
1373
1374static draw_line_func *draw_line32_funcs[] = {
1375    draw_line32_8,
1376    draw_line32_15,
1377    draw_line32_16,
1378    draw_line32_32,
1379    draw_line32_32bgr,
1380    draw_line32_15bgr,
1381    draw_line32_16bgr,
1382};
1383
1384static draw_hwc_line_func *draw_hwc_line_funcs[] = {
1385    draw_hwc_line_8,
1386    draw_hwc_line_15,
1387    draw_hwc_line_16,
1388    draw_hwc_line_32,
1389    draw_hwc_line_32bgr,
1390    draw_hwc_line_15bgr,
1391    draw_hwc_line_16bgr,
1392};
1393
1394static inline int get_depth_index(DisplaySurface *surface)
1395{
1396    switch (surface_bits_per_pixel(surface)) {
1397    default:
1398    case 8:
1399        return 0;
1400    case 15:
1401        return 1;
1402    case 16:
1403        return 2;
1404    case 32:
1405        if (is_surface_bgr(surface)) {
1406            return 4;
1407        } else {
1408            return 3;
1409        }
1410    }
1411}
1412
1413static void sm501_update_display(void *opaque)
1414{
1415    SM501State *s = (SM501State *)opaque;
1416    DisplaySurface *surface = qemu_console_surface(s->con);
1417    DirtyBitmapSnapshot *snap;
1418    int y, c_x = 0, c_y = 0;
1419    int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
1420    int width = get_width(s, crt);
1421    int height = get_height(s, crt);
1422    int src_bpp = get_bpp(s, crt);
1423    int dst_bpp = surface_bytes_per_pixel(surface);
1424    int dst_depth_index = get_depth_index(surface);
1425    draw_line_func *draw_line = NULL;
1426    draw_hwc_line_func *draw_hwc_line = NULL;
1427    int full_update = 0;
1428    int y_start = -1;
1429    ram_addr_t offset = 0;
1430    uint32_t *palette;
1431    uint8_t hwc_palette[3 * 3];
1432    uint8_t *hwc_src = NULL;
1433
1434    if (!((crt ? s->dc_crt_control : s->dc_panel_control)
1435          & SM501_DC_CRT_CONTROL_ENABLE)) {
1436        return;
1437    }
1438
1439    palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE -
1440                                                SM501_DC_PANEL_PALETTE]
1441                               : &s->dc_palette[0]);
1442
1443    /* choose draw_line function */
1444    switch (src_bpp) {
1445    case 1:
1446        draw_line = draw_line8_funcs[dst_depth_index];
1447        break;
1448    case 2:
1449        draw_line = draw_line16_funcs[dst_depth_index];
1450        break;
1451    case 4:
1452        draw_line = draw_line32_funcs[dst_depth_index];
1453        break;
1454    default:
1455        printf("sm501 update display : invalid control register value.\n");
1456        abort();
1457        break;
1458    }
1459
1460    /* set up to draw hardware cursor */
1461    if (is_hwc_enabled(s, crt)) {
1462        /* choose cursor draw line function */
1463        draw_hwc_line = draw_hwc_line_funcs[dst_depth_index];
1464        hwc_src = get_hwc_address(s, crt);
1465        c_x = get_hwc_x(s, crt);
1466        c_y = get_hwc_y(s, crt);
1467        get_hwc_palette(s, crt, hwc_palette);
1468    }
1469
1470    /* adjust console size */
1471    if (s->last_width != width || s->last_height != height) {
1472        qemu_console_resize(s->con, width, height);
1473        surface = qemu_console_surface(s->con);
1474        s->last_width = width;
1475        s->last_height = height;
1476        full_update = 1;
1477    }
1478
1479    /* draw each line according to conditions */
1480    memory_region_sync_dirty_bitmap(&s->local_mem_region);
1481    snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region,
1482              offset, width * height * src_bpp, DIRTY_MEMORY_VGA);
1483    for (y = 0, offset = 0; y < height; y++, offset += width * src_bpp) {
1484        int update, update_hwc;
1485
1486        /* check if hardware cursor is enabled and we're within its range */
1487        update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT;
1488        update = full_update || update_hwc;
1489        /* check dirty flags for each line */
1490        update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap,
1491                                                   offset, width * src_bpp);
1492
1493        /* draw line and change status */
1494        if (update) {
1495            uint8_t *d = surface_data(surface);
1496            d +=  y * width * dst_bpp;
1497
1498            /* draw graphics layer */
1499            draw_line(d, s->local_mem + offset, width, palette);
1500
1501            /* draw hardware cursor */
1502            if (update_hwc) {
1503                draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y);
1504            }
1505
1506            if (y_start < 0) {
1507                y_start = y;
1508            }
1509        } else {
1510            if (y_start >= 0) {
1511                /* flush to display */
1512                dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1513                y_start = -1;
1514            }
1515        }
1516    }
1517    g_free(snap);
1518
1519    /* complete flush to display */
1520    if (y_start >= 0) {
1521        dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1522    }
1523}
1524
1525static const GraphicHwOps sm501_ops = {
1526    .gfx_update  = sm501_update_display,
1527};
1528
1529static void sm501_reset(SM501State *s)
1530{
1531    s->system_control = 0x00100000; /* 2D engine FIFO empty */
1532    /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
1533     * to be determined at reset by GPIO lines which set config bits.
1534     * We hardwire them:
1535     *  SH = 0 : Hitachi Ready Polarity == Active Low
1536     *  CDR = 0 : do not reset clock divider
1537     *  TEST = 0 : Normal mode (not testing the silicon)
1538     *  BUS = 0 : Hitachi SH3/SH4
1539     */
1540    s->misc_control = SM501_MISC_DAC_POWER;
1541    s->gpio_31_0_control = 0;
1542    s->gpio_63_32_control = 0;
1543    s->dram_control = 0;
1544    s->arbitration_control = 0x05146732;
1545    s->irq_mask = 0;
1546    s->misc_timing = 0;
1547    s->power_mode_control = 0;
1548    s->dc_panel_control = 0x00010000; /* FIFO level 3 */
1549    s->dc_video_control = 0;
1550    s->dc_crt_control = 0x00010000;
1551    s->twoD_source = 0;
1552    s->twoD_destination = 0;
1553    s->twoD_dimension = 0;
1554    s->twoD_control = 0;
1555    s->twoD_pitch = 0;
1556    s->twoD_foreground = 0;
1557    s->twoD_background = 0;
1558    s->twoD_stretch = 0;
1559    s->twoD_color_compare = 0;
1560    s->twoD_color_compare_mask = 0;
1561    s->twoD_mask = 0;
1562    s->twoD_clip_tl = 0;
1563    s->twoD_clip_br = 0;
1564    s->twoD_mono_pattern_low = 0;
1565    s->twoD_mono_pattern_high = 0;
1566    s->twoD_window_width = 0;
1567    s->twoD_source_base = 0;
1568    s->twoD_destination_base = 0;
1569    s->twoD_alpha = 0;
1570    s->twoD_wrap = 0;
1571}
1572
1573static void sm501_init(SM501State *s, DeviceState *dev,
1574                       uint32_t local_mem_bytes)
1575{
1576    s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
1577    SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s),
1578                  s->local_mem_size_index);
1579
1580    /* local memory */
1581    memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local",
1582                           get_local_mem_size(s), &error_fatal);
1583    memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
1584    s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
1585
1586    /* mmio */
1587    memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
1588    memory_region_init_io(&s->system_config_region, OBJECT(dev),
1589                          &sm501_system_config_ops, s,
1590                          "sm501-system-config", 0x6c);
1591    memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG,
1592                                &s->system_config_region);
1593    memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev),
1594                          &sm501_disp_ctrl_ops, s,
1595                          "sm501-disp-ctrl", 0x1000);
1596    memory_region_add_subregion(&s->mmio_region, SM501_DC,
1597                                &s->disp_ctrl_region);
1598    memory_region_init_io(&s->twoD_engine_region, OBJECT(dev),
1599                          &sm501_2d_engine_ops, s,
1600                          "sm501-2d-engine", 0x54);
1601    memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE,
1602                                &s->twoD_engine_region);
1603
1604    /* create qemu graphic console */
1605    s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
1606}
1607
1608static const VMStateDescription vmstate_sm501_state = {
1609    .name = "sm501-state",
1610    .version_id = 1,
1611    .minimum_version_id = 1,
1612    .fields = (VMStateField[]) {
1613        VMSTATE_UINT32(local_mem_size_index, SM501State),
1614        VMSTATE_UINT32(system_control, SM501State),
1615        VMSTATE_UINT32(misc_control, SM501State),
1616        VMSTATE_UINT32(gpio_31_0_control, SM501State),
1617        VMSTATE_UINT32(gpio_63_32_control, SM501State),
1618        VMSTATE_UINT32(dram_control, SM501State),
1619        VMSTATE_UINT32(arbitration_control, SM501State),
1620        VMSTATE_UINT32(irq_mask, SM501State),
1621        VMSTATE_UINT32(misc_timing, SM501State),
1622        VMSTATE_UINT32(power_mode_control, SM501State),
1623        VMSTATE_UINT32(uart0_ier, SM501State),
1624        VMSTATE_UINT32(uart0_lcr, SM501State),
1625        VMSTATE_UINT32(uart0_mcr, SM501State),
1626        VMSTATE_UINT32(uart0_scr, SM501State),
1627        VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES),
1628        VMSTATE_UINT32(dc_panel_control, SM501State),
1629        VMSTATE_UINT32(dc_panel_panning_control, SM501State),
1630        VMSTATE_UINT32(dc_panel_fb_addr, SM501State),
1631        VMSTATE_UINT32(dc_panel_fb_offset, SM501State),
1632        VMSTATE_UINT32(dc_panel_fb_width, SM501State),
1633        VMSTATE_UINT32(dc_panel_fb_height, SM501State),
1634        VMSTATE_UINT32(dc_panel_tl_location, SM501State),
1635        VMSTATE_UINT32(dc_panel_br_location, SM501State),
1636        VMSTATE_UINT32(dc_panel_h_total, SM501State),
1637        VMSTATE_UINT32(dc_panel_h_sync, SM501State),
1638        VMSTATE_UINT32(dc_panel_v_total, SM501State),
1639        VMSTATE_UINT32(dc_panel_v_sync, SM501State),
1640        VMSTATE_UINT32(dc_panel_hwc_addr, SM501State),
1641        VMSTATE_UINT32(dc_panel_hwc_location, SM501State),
1642        VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State),
1643        VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State),
1644        VMSTATE_UINT32(dc_video_control, SM501State),
1645        VMSTATE_UINT32(dc_crt_control, SM501State),
1646        VMSTATE_UINT32(dc_crt_fb_addr, SM501State),
1647        VMSTATE_UINT32(dc_crt_fb_offset, SM501State),
1648        VMSTATE_UINT32(dc_crt_h_total, SM501State),
1649        VMSTATE_UINT32(dc_crt_h_sync, SM501State),
1650        VMSTATE_UINT32(dc_crt_v_total, SM501State),
1651        VMSTATE_UINT32(dc_crt_v_sync, SM501State),
1652        VMSTATE_UINT32(dc_crt_hwc_addr, SM501State),
1653        VMSTATE_UINT32(dc_crt_hwc_location, SM501State),
1654        VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State),
1655        VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State),
1656        VMSTATE_UINT32(twoD_source, SM501State),
1657        VMSTATE_UINT32(twoD_destination, SM501State),
1658        VMSTATE_UINT32(twoD_dimension, SM501State),
1659        VMSTATE_UINT32(twoD_control, SM501State),
1660        VMSTATE_UINT32(twoD_pitch, SM501State),
1661        VMSTATE_UINT32(twoD_foreground, SM501State),
1662        VMSTATE_UINT32(twoD_background, SM501State),
1663        VMSTATE_UINT32(twoD_stretch, SM501State),
1664        VMSTATE_UINT32(twoD_color_compare, SM501State),
1665        VMSTATE_UINT32(twoD_color_compare_mask, SM501State),
1666        VMSTATE_UINT32(twoD_mask, SM501State),
1667        VMSTATE_UINT32(twoD_clip_tl, SM501State),
1668        VMSTATE_UINT32(twoD_clip_br, SM501State),
1669        VMSTATE_UINT32(twoD_mono_pattern_low, SM501State),
1670        VMSTATE_UINT32(twoD_mono_pattern_high, SM501State),
1671        VMSTATE_UINT32(twoD_window_width, SM501State),
1672        VMSTATE_UINT32(twoD_source_base, SM501State),
1673        VMSTATE_UINT32(twoD_destination_base, SM501State),
1674        VMSTATE_UINT32(twoD_alpha, SM501State),
1675        VMSTATE_UINT32(twoD_wrap, SM501State),
1676        VMSTATE_END_OF_LIST()
1677     }
1678};
1679
1680#define TYPE_SYSBUS_SM501 "sysbus-sm501"
1681#define SYSBUS_SM501(obj) \
1682    OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
1683
1684typedef struct {
1685    /*< private >*/
1686    SysBusDevice parent_obj;
1687    /*< public >*/
1688    SM501State state;
1689    uint32_t vram_size;
1690    uint32_t base;
1691    void *chr_state;
1692} SM501SysBusState;
1693
1694static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
1695{
1696    SM501SysBusState *s = SYSBUS_SM501(dev);
1697    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1698    DeviceState *usb_dev;
1699
1700    sm501_init(&s->state, dev, s->vram_size);
1701    if (get_local_mem_size(&s->state) != s->vram_size) {
1702        error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
1703                   get_local_mem_size(&s->state));
1704        return;
1705    }
1706    sysbus_init_mmio(sbd, &s->state.local_mem_region);
1707    sysbus_init_mmio(sbd, &s->state.mmio_region);
1708
1709    /* bridge to usb host emulation module */
1710    usb_dev = qdev_create(NULL, "sysbus-ohci");
1711    qdev_prop_set_uint32(usb_dev, "num-ports", 2);
1712    qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
1713    qdev_init_nofail(usb_dev);
1714    memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
1715                       sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
1716    sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
1717
1718    /* bridge to serial emulation module */
1719    if (s->chr_state) {
1720        serial_mm_init(&s->state.mmio_region, SM501_UART0, 2,
1721                       NULL, /* TODO : chain irq to IRL */
1722                       115200, s->chr_state, DEVICE_LITTLE_ENDIAN);
1723    }
1724}
1725
1726static Property sm501_sysbus_properties[] = {
1727    DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
1728    DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
1729    DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state),
1730    DEFINE_PROP_END_OF_LIST(),
1731};
1732
1733static void sm501_reset_sysbus(DeviceState *dev)
1734{
1735    SM501SysBusState *s = SYSBUS_SM501(dev);
1736    sm501_reset(&s->state);
1737}
1738
1739static const VMStateDescription vmstate_sm501_sysbus = {
1740    .name = TYPE_SYSBUS_SM501,
1741    .version_id = 1,
1742    .minimum_version_id = 1,
1743    .fields = (VMStateField[]) {
1744        VMSTATE_STRUCT(state, SM501SysBusState, 1,
1745                       vmstate_sm501_state, SM501State),
1746        VMSTATE_END_OF_LIST()
1747     }
1748};
1749
1750static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
1751{
1752    DeviceClass *dc = DEVICE_CLASS(klass);
1753
1754    dc->realize = sm501_realize_sysbus;
1755    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1756    dc->desc = "SM501 Multimedia Companion";
1757    dc->props = sm501_sysbus_properties;
1758    dc->reset = sm501_reset_sysbus;
1759    dc->vmsd = &vmstate_sm501_sysbus;
1760    /* Note: pointer property "chr-state" may remain null, thus
1761     * no need for dc->user_creatable = false;
1762     */
1763}
1764
1765static const TypeInfo sm501_sysbus_info = {
1766    .name          = TYPE_SYSBUS_SM501,
1767    .parent        = TYPE_SYS_BUS_DEVICE,
1768    .instance_size = sizeof(SM501SysBusState),
1769    .class_init    = sm501_sysbus_class_init,
1770};
1771
1772#define TYPE_PCI_SM501 "sm501"
1773#define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501)
1774
1775typedef struct {
1776    /*< private >*/
1777    PCIDevice parent_obj;
1778    /*< public >*/
1779    SM501State state;
1780    uint32_t vram_size;
1781} SM501PCIState;
1782
1783static void sm501_realize_pci(PCIDevice *dev, Error **errp)
1784{
1785    SM501PCIState *s = PCI_SM501(dev);
1786
1787    sm501_init(&s->state, DEVICE(dev), s->vram_size);
1788    if (get_local_mem_size(&s->state) != s->vram_size) {
1789        error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
1790                   get_local_mem_size(&s->state));
1791        return;
1792    }
1793    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
1794                     &s->state.local_mem_region);
1795    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
1796                     &s->state.mmio_region);
1797}
1798
1799static Property sm501_pci_properties[] = {
1800    DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE),
1801    DEFINE_PROP_END_OF_LIST(),
1802};
1803
1804static void sm501_reset_pci(DeviceState *dev)
1805{
1806    SM501PCIState *s = PCI_SM501(dev);
1807    sm501_reset(&s->state);
1808    /* Bits 2:0 of misc_control register is 001 for PCI */
1809    s->state.misc_control |= 1;
1810}
1811
1812static const VMStateDescription vmstate_sm501_pci = {
1813    .name = TYPE_PCI_SM501,
1814    .version_id = 1,
1815    .minimum_version_id = 1,
1816    .fields = (VMStateField[]) {
1817        VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState),
1818        VMSTATE_STRUCT(state, SM501PCIState, 1,
1819                       vmstate_sm501_state, SM501State),
1820        VMSTATE_END_OF_LIST()
1821     }
1822};
1823
1824static void sm501_pci_class_init(ObjectClass *klass, void *data)
1825{
1826    DeviceClass *dc = DEVICE_CLASS(klass);
1827    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1828
1829    k->realize = sm501_realize_pci;
1830    k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION;
1831    k->device_id = PCI_DEVICE_ID_SM501;
1832    k->class_id = PCI_CLASS_DISPLAY_OTHER;
1833    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1834    dc->desc = "SM501 Display Controller";
1835    dc->props = sm501_pci_properties;
1836    dc->reset = sm501_reset_pci;
1837    dc->hotpluggable = false;
1838    dc->vmsd = &vmstate_sm501_pci;
1839}
1840
1841static const TypeInfo sm501_pci_info = {
1842    .name          = TYPE_PCI_SM501,
1843    .parent        = TYPE_PCI_DEVICE,
1844    .instance_size = sizeof(SM501PCIState),
1845    .class_init    = sm501_pci_class_init,
1846    .interfaces = (InterfaceInfo[]) {
1847        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1848        { },
1849    },
1850};
1851
1852static void sm501_register_types(void)
1853{
1854    type_register_static(&sm501_sysbus_info);
1855    type_register_static(&sm501_pci_info);
1856}
1857
1858type_init(sm501_register_types)
1859