LXR qemu/hw/microblaze/petalogix_ml605

   1/*
   2 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605
   3 * board.
   4 *
   5 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
   6 * Copyright (c) 2011 PetaLogix
   7 * Copyright (c) 2009 Edgar E. Iglesias.
   8 *
   9 * Permission is hereby granted, free of charge, to any person obtaining a copy
  10 * of this software and associated documentation files (the "Software"), to deal
  11 * in the Software without restriction, including without limitation the rights
  12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 * copies of the Software, and to permit persons to whom the Software is
  14 * furnished to do so, subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in
  17 * all copies or substantial portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25 * THE SOFTWARE.
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "qapi/error.h"
  30#include "qemu-common.h"
  31#include "cpu.h"
  32#include "hw/sysbus.h"
  33#include "hw/hw.h"
  34#include "net/net.h"
  35#include "hw/block/flash.h"
  36#include "sysemu/sysemu.h"
  37#include "hw/devices.h"
  38#include "hw/boards.h"
  39#include "sysemu/block-backend.h"
  40#include "hw/char/serial.h"
  41#include "exec/address-spaces.h"
  42#include "hw/ssi/ssi.h"
  43
  44#include "boot.h"
  45
  46#include "hw/stream.h"
  47
  48#define LMB_BRAM_SIZE  (128 * 1024)
  49#define FLASH_SIZE     (32 * 1024 * 1024)
  50
  51#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
  52
  53#define NUM_SPI_FLASHES 4
  54
  55#define SPI_BASEADDR 0x40a00000
  56#define MEMORY_BASEADDR 0x50000000
  57#define FLASH_BASEADDR 0x86000000
  58#define INTC_BASEADDR 0x81800000
  59#define TIMER_BASEADDR 0x83c00000
  60#define UART16550_BASEADDR 0x83e00000
  61#define AXIENET_BASEADDR 0x82780000
  62#define AXIDMA_BASEADDR 0x84600000
  63
  64#define AXIDMA_IRQ1         0
  65#define AXIDMA_IRQ0         1
  66#define TIMER_IRQ           2
  67#define AXIENET_IRQ         3
  68#define SPI_IRQ             4
  69#define UART16550_IRQ       5
  70
  71static void
  72petalogix_ml605_init(MachineState *machine)
  73{
  74    ram_addr_t ram_size = machine->ram_size;
  75    MemoryRegion *address_space_mem = get_system_memory();
  76    DeviceState *dev, *dma, *eth0;
  77    Object *ds, *cs;
  78    MicroBlazeCPU *cpu;
  79    SysBusDevice *busdev;
  80    DriveInfo *dinfo;
  81    int i;
  82    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
  83    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  84    qemu_irq irq[32];
  85
  86    /* init CPUs */
  87    cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
  88    object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort);
  89    /* Use FPU but don't use floating point conversion and square
  90     * root instructions
  91     */
  92    object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
  93    object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
  94                             &error_abort);
  95    object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
  96    object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
  97
  98    /* Attach emulated BRAM through the LMB.  */
  99    memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
 100                           LMB_BRAM_SIZE, &error_fatal);
 101    memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
 102
 103    memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size,
 104                           &error_fatal);
 105    memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram);
 106
 107    dinfo = drive_get(IF_PFLASH, 0, 0);
 108    /* 5th parameter 2 means bank-width
 109     * 10th paremeter 0 means little-endian */
 110    pflash_cfi01_register(FLASH_BASEADDR,
 111                          NULL, "petalogix_ml605.flash", FLASH_SIZE,
 112                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 113                          (64 * 1024), FLASH_SIZE >> 16,
 114                          2, 0x89, 0x18, 0x0000, 0x0, 0);
 115
 116
 117    dev = qdev_create(NULL, "xlnx.xps-intc");
 118    qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
 119    qdev_init_nofail(dev);
 120    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
 121    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 122                       qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
 123    for (i = 0; i < 32; i++) {
 124        irq[i] = qdev_get_gpio_in(dev, i);
 125    }
 126
 127    serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
 128                   irq[UART16550_IRQ], 115200, serial_hds[0],
 129                   DEVICE_LITTLE_ENDIAN);
 130
 131    /* 2 timers at irq 2 @ 100 Mhz.  */
 132    dev = qdev_create(NULL, "xlnx.xps-timer");
 133    qdev_prop_set_uint32(dev, "one-timer-only", 0);
 134    qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
 135    qdev_init_nofail(dev);
 136    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
 137    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
 138
 139    /* axi ethernet and dma initialization. */
 140    qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
 141    eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
 142    dma = qdev_create(NULL, "xlnx.axi-dma");
 143
 144    /* FIXME: attach to the sysbus instead */
 145    object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0),
 146                              NULL);
 147    object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma),
 148                              NULL);
 149
 150    ds = object_property_get_link(OBJECT(dma),
 151                                  "axistream-connected-target", NULL);
 152    cs = object_property_get_link(OBJECT(dma),
 153                                  "axistream-control-connected-target", NULL);
 154    qdev_set_nic_properties(eth0, &nd_table[0]);
 155    qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
 156    qdev_prop_set_uint32(eth0, "txmem", 0x1000);
 157    object_property_set_link(OBJECT(eth0), OBJECT(ds),
 158                             "axistream-connected", &error_abort);
 159    object_property_set_link(OBJECT(eth0), OBJECT(cs),
 160                             "axistream-control-connected", &error_abort);
 161    qdev_init_nofail(eth0);
 162    sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
 163    sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
 164
 165    ds = object_property_get_link(OBJECT(eth0),
 166                                  "axistream-connected-target", NULL);
 167    cs = object_property_get_link(OBJECT(eth0),
 168                                  "axistream-control-connected-target", NULL);
 169    qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000);
 170    object_property_set_link(OBJECT(dma), OBJECT(ds),
 171                             "axistream-connected", &error_abort);
 172    object_property_set_link(OBJECT(dma), OBJECT(cs),
 173                             "axistream-control-connected", &error_abort);
 174    qdev_init_nofail(dma);
 175    sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
 176    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
 177    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
 178
 179    {
 180        SSIBus *spi;
 181
 182        dev = qdev_create(NULL, "xlnx.xps-spi");
 183        qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
 184        qdev_init_nofail(dev);
 185        busdev = SYS_BUS_DEVICE(dev);
 186        sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
 187        sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
 188
 189        spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
 190
 191        for (i = 0; i < NUM_SPI_FLASHES; i++) {
 192            DriveInfo *dinfo = drive_get_next(IF_MTD);
 193            qemu_irq cs_line;
 194
 195            dev = ssi_create_slave_no_init(spi, "n25q128");
 196            if (dinfo) {
 197                qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
 198                                    &error_fatal);
 199            }
 200            qdev_init_nofail(dev);
 201
 202            cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
 203            sysbus_connect_irq(busdev, i+1, cs_line);
 204        }
 205    }
 206
 207    /* setup PVR to match kernel settings */
 208    cpu->env.pvr.regs[4] = 0xc56b8000;
 209    cpu->env.pvr.regs[5] = 0xc56be000;
 210    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
 211
 212    microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
 213                           machine->initrd_filename,
 214                           BINARY_DEVICE_TREE_FILE,
 215                           NULL);
 216
 217}
 218
 219static void petalogix_ml605_machine_init(MachineClass *mc)
 220{
 221    mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian";
 222    mc->init = petalogix_ml605_init;
 223    mc->is_default = 0;
 224}
 225
 226DEFINE_MACHINE("petalogix-ml605", petalogix_ml605_machine_init)
 227