1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "qemu-common.h"
31#include "cpu.h"
32#include "hw/hw.h"
33#include "trace.h"
34#include "qemu/timer.h"
35#include "hw/ppc/xics.h"
36#include "qemu/error-report.h"
37#include "qapi/visitor.h"
38#include "monitor/monitor.h"
39#include "hw/intc/intc.h"
40
41void icp_pic_print_info(ICPState *icp, Monitor *mon)
42{
43 ICPStateClass *icpc = ICP_GET_CLASS(icp);
44 int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
45
46 if (!icp->output) {
47 return;
48 }
49
50 if (icpc->synchronize_state) {
51 icpc->synchronize_state(icp);
52 }
53
54 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
55 cpu_index, icp->xirr, icp->xirr_owner,
56 icp->pending_priority, icp->mfrr);
57}
58
59void ics_pic_print_info(ICSState *ics, Monitor *mon)
60{
61 ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
62 uint32_t i;
63
64 monitor_printf(mon, "ICS %4x..%4x %p\n",
65 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
66
67 if (!ics->irqs) {
68 return;
69 }
70
71 if (icsc->synchronize_state) {
72 icsc->synchronize_state(ics);
73 }
74
75 for (i = 0; i < ics->nr_irqs; i++) {
76 ICSIRQState *irq = ics->irqs + i;
77
78 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
79 continue;
80 }
81 monitor_printf(mon, " %4x %s %02x %02x\n",
82 ics->offset + i,
83 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
84 "LSI" : "MSI",
85 irq->priority, irq->status);
86 }
87}
88
89
90
91
92
93#define XISR_MASK 0x00ffffff
94#define CPPR_MASK 0xff000000
95
96#define XISR(icp) (((icp)->xirr) & XISR_MASK)
97#define CPPR(icp) (((icp)->xirr) >> 24)
98
99static void ics_reject(ICSState *ics, uint32_t nr)
100{
101 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
102
103 if (k->reject) {
104 k->reject(ics, nr);
105 }
106}
107
108void ics_resend(ICSState *ics)
109{
110 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
111
112 if (k->resend) {
113 k->resend(ics);
114 }
115}
116
117static void ics_eoi(ICSState *ics, int nr)
118{
119 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
120
121 if (k->eoi) {
122 k->eoi(ics, nr);
123 }
124}
125
126static void icp_check_ipi(ICPState *icp)
127{
128 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
129 return;
130 }
131
132 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
133
134 if (XISR(icp) && icp->xirr_owner) {
135 ics_reject(icp->xirr_owner, XISR(icp));
136 }
137
138 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
139 icp->pending_priority = icp->mfrr;
140 icp->xirr_owner = NULL;
141 qemu_irq_raise(icp->output);
142}
143
144void icp_resend(ICPState *icp)
145{
146 XICSFabric *xi = icp->xics;
147 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
148
149 if (icp->mfrr < CPPR(icp)) {
150 icp_check_ipi(icp);
151 }
152
153 xic->ics_resend(xi);
154}
155
156void icp_set_cppr(ICPState *icp, uint8_t cppr)
157{
158 uint8_t old_cppr;
159 uint32_t old_xisr;
160
161 old_cppr = CPPR(icp);
162 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
163
164 if (cppr < old_cppr) {
165 if (XISR(icp) && (cppr <= icp->pending_priority)) {
166 old_xisr = XISR(icp);
167 icp->xirr &= ~XISR_MASK;
168 icp->pending_priority = 0xff;
169 qemu_irq_lower(icp->output);
170 if (icp->xirr_owner) {
171 ics_reject(icp->xirr_owner, old_xisr);
172 icp->xirr_owner = NULL;
173 }
174 }
175 } else {
176 if (!XISR(icp)) {
177 icp_resend(icp);
178 }
179 }
180}
181
182void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
183{
184 icp->mfrr = mfrr;
185 if (mfrr < CPPR(icp)) {
186 icp_check_ipi(icp);
187 }
188}
189
190uint32_t icp_accept(ICPState *icp)
191{
192 uint32_t xirr = icp->xirr;
193
194 qemu_irq_lower(icp->output);
195 icp->xirr = icp->pending_priority << 24;
196 icp->pending_priority = 0xff;
197 icp->xirr_owner = NULL;
198
199 trace_xics_icp_accept(xirr, icp->xirr);
200
201 return xirr;
202}
203
204uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
205{
206 if (mfrr) {
207 *mfrr = icp->mfrr;
208 }
209 return icp->xirr;
210}
211
212void icp_eoi(ICPState *icp, uint32_t xirr)
213{
214 XICSFabric *xi = icp->xics;
215 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
216 ICSState *ics;
217 uint32_t irq;
218
219
220 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
221 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
222 irq = xirr & XISR_MASK;
223
224 ics = xic->ics_get(xi, irq);
225 if (ics) {
226 ics_eoi(ics, irq);
227 }
228 if (!XISR(icp)) {
229 icp_resend(icp);
230 }
231}
232
233static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
234{
235 ICPState *icp = xics_icp_get(ics->xics, server);
236
237 trace_xics_icp_irq(server, nr, priority);
238
239 if ((priority >= CPPR(icp))
240 || (XISR(icp) && (icp->pending_priority <= priority))) {
241 ics_reject(ics, nr);
242 } else {
243 if (XISR(icp) && icp->xirr_owner) {
244 ics_reject(icp->xirr_owner, XISR(icp));
245 icp->xirr_owner = NULL;
246 }
247 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
248 icp->xirr_owner = ics;
249 icp->pending_priority = priority;
250 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
251 qemu_irq_raise(icp->output);
252 }
253}
254
255static int icp_dispatch_pre_save(void *opaque)
256{
257 ICPState *icp = opaque;
258 ICPStateClass *info = ICP_GET_CLASS(icp);
259
260 if (info->pre_save) {
261 info->pre_save(icp);
262 }
263
264 return 0;
265}
266
267static int icp_dispatch_post_load(void *opaque, int version_id)
268{
269 ICPState *icp = opaque;
270 ICPStateClass *info = ICP_GET_CLASS(icp);
271
272 if (info->post_load) {
273 return info->post_load(icp, version_id);
274 }
275
276 return 0;
277}
278
279static const VMStateDescription vmstate_icp_server = {
280 .name = "icp/server",
281 .version_id = 1,
282 .minimum_version_id = 1,
283 .pre_save = icp_dispatch_pre_save,
284 .post_load = icp_dispatch_post_load,
285 .fields = (VMStateField[]) {
286
287 VMSTATE_UINT32(xirr, ICPState),
288 VMSTATE_UINT8(pending_priority, ICPState),
289 VMSTATE_UINT8(mfrr, ICPState),
290 VMSTATE_END_OF_LIST()
291 },
292};
293
294static void icp_reset(void *dev)
295{
296 ICPState *icp = ICP(dev);
297 ICPStateClass *icpc = ICP_GET_CLASS(icp);
298
299 icp->xirr = 0;
300 icp->pending_priority = 0xff;
301 icp->mfrr = 0xff;
302
303
304 qemu_set_irq(icp->output, 0);
305
306 if (icpc->reset) {
307 icpc->reset(icp);
308 }
309}
310
311static void icp_realize(DeviceState *dev, Error **errp)
312{
313 ICPState *icp = ICP(dev);
314 ICPStateClass *icpc = ICP_GET_CLASS(dev);
315 PowerPCCPU *cpu;
316 CPUPPCState *env;
317 Object *obj;
318 Error *err = NULL;
319
320 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
321 if (!obj) {
322 error_propagate(errp, err);
323 error_prepend(errp, "required link '" ICP_PROP_XICS "' not found: ");
324 return;
325 }
326
327 icp->xics = XICS_FABRIC(obj);
328
329 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
330 if (!obj) {
331 error_propagate(errp, err);
332 error_prepend(errp, "required link '" ICP_PROP_CPU "' not found: ");
333 return;
334 }
335
336 cpu = POWERPC_CPU(obj);
337 cpu->intc = OBJECT(icp);
338 icp->cs = CPU(obj);
339
340 env = &cpu->env;
341 switch (PPC_INPUT(env)) {
342 case PPC_FLAGS_INPUT_POWER7:
343 icp->output = env->irq_inputs[POWER7_INPUT_INT];
344 break;
345
346 case PPC_FLAGS_INPUT_970:
347 icp->output = env->irq_inputs[PPC970_INPUT_INT];
348 break;
349
350 default:
351 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
352 return;
353 }
354
355 if (icpc->realize) {
356 icpc->realize(icp, errp);
357 }
358
359 qemu_register_reset(icp_reset, dev);
360 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
361}
362
363static void icp_unrealize(DeviceState *dev, Error **errp)
364{
365 ICPState *icp = ICP(dev);
366
367 vmstate_unregister(NULL, &vmstate_icp_server, icp);
368 qemu_unregister_reset(icp_reset, dev);
369}
370
371static void icp_class_init(ObjectClass *klass, void *data)
372{
373 DeviceClass *dc = DEVICE_CLASS(klass);
374
375 dc->realize = icp_realize;
376 dc->unrealize = icp_unrealize;
377}
378
379static const TypeInfo icp_info = {
380 .name = TYPE_ICP,
381 .parent = TYPE_DEVICE,
382 .instance_size = sizeof(ICPState),
383 .class_init = icp_class_init,
384 .class_size = sizeof(ICPStateClass),
385};
386
387
388
389
390static void ics_simple_resend_msi(ICSState *ics, int srcno)
391{
392 ICSIRQState *irq = ics->irqs + srcno;
393
394
395 if (irq->status & XICS_STATUS_REJECTED) {
396 irq->status &= ~XICS_STATUS_REJECTED;
397 if (irq->priority != 0xff) {
398 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
399 }
400 }
401}
402
403static void ics_simple_resend_lsi(ICSState *ics, int srcno)
404{
405 ICSIRQState *irq = ics->irqs + srcno;
406
407 if ((irq->priority != 0xff)
408 && (irq->status & XICS_STATUS_ASSERTED)
409 && !(irq->status & XICS_STATUS_SENT)) {
410 irq->status |= XICS_STATUS_SENT;
411 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
412 }
413}
414
415static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
416{
417 ICSIRQState *irq = ics->irqs + srcno;
418
419 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
420
421 if (val) {
422 if (irq->priority == 0xff) {
423 irq->status |= XICS_STATUS_MASKED_PENDING;
424 trace_xics_masked_pending();
425 } else {
426 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
427 }
428 }
429}
430
431static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
432{
433 ICSIRQState *irq = ics->irqs + srcno;
434
435 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
436 if (val) {
437 irq->status |= XICS_STATUS_ASSERTED;
438 } else {
439 irq->status &= ~XICS_STATUS_ASSERTED;
440 }
441 ics_simple_resend_lsi(ics, srcno);
442}
443
444static void ics_simple_set_irq(void *opaque, int srcno, int val)
445{
446 ICSState *ics = (ICSState *)opaque;
447
448 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
449 ics_simple_set_irq_lsi(ics, srcno, val);
450 } else {
451 ics_simple_set_irq_msi(ics, srcno, val);
452 }
453}
454
455static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
456{
457 ICSIRQState *irq = ics->irqs + srcno;
458
459 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
460 || (irq->priority == 0xff)) {
461 return;
462 }
463
464 irq->status &= ~XICS_STATUS_MASKED_PENDING;
465 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
466}
467
468static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
469{
470 ics_simple_resend_lsi(ics, srcno);
471}
472
473void ics_simple_write_xive(ICSState *ics, int srcno, int server,
474 uint8_t priority, uint8_t saved_priority)
475{
476 ICSIRQState *irq = ics->irqs + srcno;
477
478 irq->server = server;
479 irq->priority = priority;
480 irq->saved_priority = saved_priority;
481
482 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
483 priority);
484
485 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
486 ics_simple_write_xive_lsi(ics, srcno);
487 } else {
488 ics_simple_write_xive_msi(ics, srcno);
489 }
490}
491
492static void ics_simple_reject(ICSState *ics, uint32_t nr)
493{
494 ICSIRQState *irq = ics->irqs + nr - ics->offset;
495
496 trace_xics_ics_simple_reject(nr, nr - ics->offset);
497 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
498 irq->status |= XICS_STATUS_REJECTED;
499 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
500 irq->status &= ~XICS_STATUS_SENT;
501 }
502}
503
504static void ics_simple_resend(ICSState *ics)
505{
506 int i;
507
508 for (i = 0; i < ics->nr_irqs; i++) {
509
510 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
511 ics_simple_resend_lsi(ics, i);
512 } else {
513 ics_simple_resend_msi(ics, i);
514 }
515 }
516}
517
518static void ics_simple_eoi(ICSState *ics, uint32_t nr)
519{
520 int srcno = nr - ics->offset;
521 ICSIRQState *irq = ics->irqs + srcno;
522
523 trace_xics_ics_simple_eoi(nr);
524
525 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
526 irq->status &= ~XICS_STATUS_SENT;
527 }
528}
529
530static void ics_simple_reset(void *dev)
531{
532 ICSState *ics = ICS_SIMPLE(dev);
533 int i;
534 uint8_t flags[ics->nr_irqs];
535
536 for (i = 0; i < ics->nr_irqs; i++) {
537 flags[i] = ics->irqs[i].flags;
538 }
539
540 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
541
542 for (i = 0; i < ics->nr_irqs; i++) {
543 ics->irqs[i].priority = 0xff;
544 ics->irqs[i].saved_priority = 0xff;
545 ics->irqs[i].flags = flags[i];
546 }
547}
548
549static int ics_simple_dispatch_pre_save(void *opaque)
550{
551 ICSState *ics = opaque;
552 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
553
554 if (info->pre_save) {
555 info->pre_save(ics);
556 }
557
558 return 0;
559}
560
561static int ics_simple_dispatch_post_load(void *opaque, int version_id)
562{
563 ICSState *ics = opaque;
564 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
565
566 if (info->post_load) {
567 return info->post_load(ics, version_id);
568 }
569
570 return 0;
571}
572
573static const VMStateDescription vmstate_ics_simple_irq = {
574 .name = "ics/irq",
575 .version_id = 2,
576 .minimum_version_id = 1,
577 .fields = (VMStateField[]) {
578 VMSTATE_UINT32(server, ICSIRQState),
579 VMSTATE_UINT8(priority, ICSIRQState),
580 VMSTATE_UINT8(saved_priority, ICSIRQState),
581 VMSTATE_UINT8(status, ICSIRQState),
582 VMSTATE_UINT8(flags, ICSIRQState),
583 VMSTATE_END_OF_LIST()
584 },
585};
586
587static const VMStateDescription vmstate_ics_simple = {
588 .name = "ics",
589 .version_id = 1,
590 .minimum_version_id = 1,
591 .pre_save = ics_simple_dispatch_pre_save,
592 .post_load = ics_simple_dispatch_post_load,
593 .fields = (VMStateField[]) {
594
595 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
596
597 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
598 vmstate_ics_simple_irq,
599 ICSIRQState),
600 VMSTATE_END_OF_LIST()
601 },
602};
603
604static void ics_simple_initfn(Object *obj)
605{
606 ICSState *ics = ICS_SIMPLE(obj);
607
608 ics->offset = XICS_IRQ_BASE;
609}
610
611static void ics_simple_realize(ICSState *ics, Error **errp)
612{
613 if (!ics->nr_irqs) {
614 error_setg(errp, "Number of interrupts needs to be greater 0");
615 return;
616 }
617 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
618 ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
619
620 qemu_register_reset(ics_simple_reset, ics);
621}
622
623static Property ics_simple_properties[] = {
624 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
625 DEFINE_PROP_END_OF_LIST(),
626};
627
628static void ics_simple_class_init(ObjectClass *klass, void *data)
629{
630 DeviceClass *dc = DEVICE_CLASS(klass);
631 ICSStateClass *isc = ICS_BASE_CLASS(klass);
632
633 isc->realize = ics_simple_realize;
634 dc->props = ics_simple_properties;
635 dc->vmsd = &vmstate_ics_simple;
636 isc->reject = ics_simple_reject;
637 isc->resend = ics_simple_resend;
638 isc->eoi = ics_simple_eoi;
639}
640
641static const TypeInfo ics_simple_info = {
642 .name = TYPE_ICS_SIMPLE,
643 .parent = TYPE_ICS_BASE,
644 .instance_size = sizeof(ICSState),
645 .class_init = ics_simple_class_init,
646 .class_size = sizeof(ICSStateClass),
647 .instance_init = ics_simple_initfn,
648};
649
650static void ics_base_realize(DeviceState *dev, Error **errp)
651{
652 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
653 ICSState *ics = ICS_BASE(dev);
654 Object *obj;
655 Error *err = NULL;
656
657 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
658 if (!obj) {
659 error_propagate(errp, err);
660 error_prepend(errp, "required link '" ICS_PROP_XICS "' not found: ");
661 return;
662 }
663 ics->xics = XICS_FABRIC(obj);
664
665
666 if (icsc->realize) {
667 icsc->realize(ics, errp);
668 }
669}
670
671static void ics_base_class_init(ObjectClass *klass, void *data)
672{
673 DeviceClass *dc = DEVICE_CLASS(klass);
674
675 dc->realize = ics_base_realize;
676}
677
678static const TypeInfo ics_base_info = {
679 .name = TYPE_ICS_BASE,
680 .parent = TYPE_DEVICE,
681 .abstract = true,
682 .instance_size = sizeof(ICSState),
683 .class_init = ics_base_class_init,
684 .class_size = sizeof(ICSStateClass),
685};
686
687static const TypeInfo xics_fabric_info = {
688 .name = TYPE_XICS_FABRIC,
689 .parent = TYPE_INTERFACE,
690 .class_size = sizeof(XICSFabricClass),
691};
692
693
694
695
696qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
697{
698 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
699 ICSState *ics = xic->ics_get(xi, irq);
700
701 if (ics) {
702 return ics->qirqs[irq - ics->offset];
703 }
704
705 return NULL;
706}
707
708ICPState *xics_icp_get(XICSFabric *xi, int server)
709{
710 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
711
712 return xic->icp_get(xi, server);
713}
714
715void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
716{
717 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
718
719 ics->irqs[srcno].flags |=
720 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
721}
722
723static void xics_register_types(void)
724{
725 type_register_static(&ics_simple_info);
726 type_register_static(&ics_base_info);
727 type_register_static(&icp_info);
728 type_register_static(&xics_fabric_info);
729}
730
731type_init(xics_register_types)
732
