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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu-common.h"
24#include "hw/pci/pci_bridge.h"
25#include "hw/pci/pcie.h"
26#include "hw/pci/msix.h"
27#include "hw/pci/msi.h"
28#include "hw/pci/pci_bus.h"
29#include "hw/pci/pcie_regs.h"
30#include "qemu/range.h"
31
32
33#ifdef DEBUG_PCIE
34# define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
36#else
37# define PCIE_DPRINTF(fmt, ...) do {} while (0)
38#endif
39#define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
41
42
43
44
45
46
47static void
48pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
49{
50 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
51 uint8_t *cmask = dev->cmask + dev->exp.exp_cap;
52
53
54
55 pci_set_word(exp_cap + PCI_EXP_FLAGS,
56 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
57 version);
58
59
60
61
62
63
64
65
66 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
67
68 pci_set_long(exp_cap + PCI_EXP_LNKCAP,
69 (port << PCI_EXP_LNKCAP_PN_SHIFT) |
70 PCI_EXP_LNKCAP_ASPMS_0S |
71 PCI_EXP_LNK_MLW_1 |
72 PCI_EXP_LNK_LS_25);
73
74 pci_set_word(exp_cap + PCI_EXP_LNKSTA,
75 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
76
77 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
78 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
79 PCI_EXP_LNKSTA_DLLLA);
80 }
81
82
83
84
85
86 pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
87}
88
89int pcie_cap_init(PCIDevice *dev, uint8_t offset,
90 uint8_t type, uint8_t port,
91 Error **errp)
92{
93
94 int pos;
95 uint8_t *exp_cap;
96
97 assert(pci_is_express(dev));
98
99 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
100 PCI_EXP_VER2_SIZEOF, errp);
101 if (pos < 0) {
102 return pos;
103 }
104 dev->exp.exp_cap = pos;
105 exp_cap = dev->config + pos;
106
107
108 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2);
109
110
111 pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
112 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
113
114 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
115
116 if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
117
118 pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
119 }
120
121 return pos;
122}
123
124int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
125 uint8_t port)
126{
127
128 int pos;
129 Error *local_err = NULL;
130
131 assert(pci_is_express(dev));
132
133 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
134 PCI_EXP_VER1_SIZEOF, &local_err);
135 if (pos < 0) {
136 error_report_err(local_err);
137 return pos;
138 }
139 dev->exp.exp_cap = pos;
140
141 pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1);
142
143 return pos;
144}
145
146static int
147pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
148{
149 uint8_t type = PCI_EXP_TYPE_ENDPOINT;
150 Error *local_err = NULL;
151 int ret;
152
153
154
155
156
157
158 if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) {
159 type = PCI_EXP_TYPE_RC_END;
160 }
161
162 if (cap_size == PCI_EXP_VER1_SIZEOF) {
163 return pcie_cap_v1_init(dev, offset, type, 0);
164 } else {
165 ret = pcie_cap_init(dev, offset, type, 0, &local_err);
166
167 if (ret < 0) {
168 error_report_err(local_err);
169 }
170
171 return ret;
172 }
173}
174
175int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
176{
177 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
178}
179
180int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
181{
182 return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
183}
184
185void pcie_cap_exit(PCIDevice *dev)
186{
187 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
188}
189
190void pcie_cap_v1_exit(PCIDevice *dev)
191{
192 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
193}
194
195uint8_t pcie_cap_get_type(const PCIDevice *dev)
196{
197 uint32_t pos = dev->exp.exp_cap;
198 assert(pos > 0);
199 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
200 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
201}
202
203
204
205
206void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
207{
208 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
209 assert(vector < 32);
210 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
211 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
212 vector << PCI_EXP_FLAGS_IRQ_SHIFT);
213}
214
215uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
216{
217 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
218 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
219}
220
221void pcie_cap_deverr_init(PCIDevice *dev)
222{
223 uint32_t pos = dev->exp.exp_cap;
224 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
225 PCI_EXP_DEVCAP_RBER);
226 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
227 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
228 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
229 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
230 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
231 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
232}
233
234void pcie_cap_deverr_reset(PCIDevice *dev)
235{
236 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
237 pci_long_test_and_clear_mask(devctl,
238 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
239 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
240}
241
242void pcie_cap_lnkctl_init(PCIDevice *dev)
243{
244 uint32_t pos = dev->exp.exp_cap;
245 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
246 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
247}
248
249void pcie_cap_lnkctl_reset(PCIDevice *dev)
250{
251 uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
252 pci_long_test_and_clear_mask(lnkctl,
253 PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
254}
255
256static void hotplug_event_update_event_status(PCIDevice *dev)
257{
258 uint32_t pos = dev->exp.exp_cap;
259 uint8_t *exp_cap = dev->config + pos;
260 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
261 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
262
263 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
264 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
265}
266
267static void hotplug_event_notify(PCIDevice *dev)
268{
269 bool prev = dev->exp.hpev_notified;
270
271 hotplug_event_update_event_status(dev);
272
273 if (prev == dev->exp.hpev_notified) {
274 return;
275 }
276
277
278
279
280
281
282
283 if (msix_enabled(dev)) {
284 msix_notify(dev, pcie_cap_flags_get_vector(dev));
285 } else if (msi_enabled(dev)) {
286 msi_notify(dev, pcie_cap_flags_get_vector(dev));
287 } else {
288 pci_set_irq(dev, dev->exp.hpev_notified);
289 }
290}
291
292static void hotplug_event_clear(PCIDevice *dev)
293{
294 hotplug_event_update_event_status(dev);
295 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
296 pci_irq_deassert(dev);
297 }
298}
299
300
301
302
303
304
305
306
307static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
308{
309
310 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
311 PCI_EXP_SLTSTA, event)) {
312 return;
313 }
314 hotplug_event_notify(dev);
315}
316
317static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev,
318 DeviceState *dev,
319 uint8_t **exp_cap, Error **errp)
320{
321 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
322 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA);
323
324 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
325 if (sltsta & PCI_EXP_SLTSTA_EIS) {
326
327
328
329 error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
330 }
331}
332
333void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
334 Error **errp)
335{
336 uint8_t *exp_cap;
337 PCIDevice *pci_dev = PCI_DEVICE(dev);
338
339 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
340
341
342
343
344 if (!dev->hotplugged) {
345 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
346 PCI_EXP_SLTSTA_PDS);
347 return;
348 }
349
350
351
352
353
354 if (pci_get_function_0(pci_dev)) {
355 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
356 PCI_EXP_SLTSTA_PDS);
357 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
358 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
359 }
360}
361
362static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
363{
364 object_unparent(OBJECT(dev));
365}
366
367void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev,
368 DeviceState *dev, Error **errp)
369{
370 uint8_t *exp_cap;
371 PCIDevice *pci_dev = PCI_DEVICE(dev);
372 PCIBus *bus = pci_dev->bus;
373
374 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
375
376
377
378
379
380 if (pci_dev->devfn &&
381 !bus->devices[0]) {
382 pcie_unplug_device(bus, pci_dev, NULL);
383
384 return;
385 }
386
387 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
388}
389
390
391
392void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
393{
394 uint32_t pos = dev->exp.exp_cap;
395
396 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
397 PCI_EXP_FLAGS_SLOT);
398
399 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
400 ~PCI_EXP_SLTCAP_PSN);
401 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
402 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
403 PCI_EXP_SLTCAP_EIP |
404 PCI_EXP_SLTCAP_HPS |
405 PCI_EXP_SLTCAP_HPC |
406 PCI_EXP_SLTCAP_PIP |
407 PCI_EXP_SLTCAP_AIP |
408 PCI_EXP_SLTCAP_ABP);
409
410 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
411 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
412 PCI_EXP_SLTCAP_PCP);
413 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
414 PCI_EXP_SLTCTL_PCC);
415 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
416 PCI_EXP_SLTCTL_PCC);
417 }
418
419 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
420 PCI_EXP_SLTCTL_PIC |
421 PCI_EXP_SLTCTL_AIC);
422 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
423 PCI_EXP_SLTCTL_PIC_OFF |
424 PCI_EXP_SLTCTL_AIC_OFF);
425 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
426 PCI_EXP_SLTCTL_PIC |
427 PCI_EXP_SLTCTL_AIC |
428 PCI_EXP_SLTCTL_HPIE |
429 PCI_EXP_SLTCTL_CCIE |
430 PCI_EXP_SLTCTL_PDCE |
431 PCI_EXP_SLTCTL_ABPE);
432
433
434
435
436
437 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
438 PCI_EXP_SLTCTL_EIC);
439
440 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
441 PCI_EXP_HP_EV_SUPPORTED);
442
443 dev->exp.hpev_notified = false;
444
445 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
446 DEVICE(dev), NULL);
447}
448
449void pcie_cap_slot_reset(PCIDevice *dev)
450{
451 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
452 uint8_t port_type = pcie_cap_get_type(dev);
453
454 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
455 port_type == PCI_EXP_TYPE_ROOT_PORT);
456
457 PCIE_DEV_PRINTF(dev, "reset\n");
458
459 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
460 PCI_EXP_SLTCTL_EIC |
461 PCI_EXP_SLTCTL_PIC |
462 PCI_EXP_SLTCTL_AIC |
463 PCI_EXP_SLTCTL_HPIE |
464 PCI_EXP_SLTCTL_CCIE |
465 PCI_EXP_SLTCTL_PDCE |
466 PCI_EXP_SLTCTL_ABPE);
467 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
468 PCI_EXP_SLTCTL_AIC_OFF);
469
470 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
471
472 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
473 uint16_t pic;
474
475 if (populated) {
476 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
477 PCI_EXP_SLTCTL_PCC);
478 } else {
479 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
480 PCI_EXP_SLTCTL_PCC);
481 }
482
483 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
484 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
485 }
486
487 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
488 PCI_EXP_SLTSTA_EIS |
489
490 PCI_EXP_SLTSTA_CC |
491 PCI_EXP_SLTSTA_PDC |
492 PCI_EXP_SLTSTA_ABP);
493
494 hotplug_event_update_event_status(dev);
495}
496
497void pcie_cap_slot_write_config(PCIDevice *dev,
498 uint32_t addr, uint32_t val, int len)
499{
500 uint32_t pos = dev->exp.exp_cap;
501 uint8_t *exp_cap = dev->config + pos;
502 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
503
504 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
505 hotplug_event_clear(dev);
506 }
507
508 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
509 return;
510 }
511
512 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
513 PCI_EXP_SLTCTL_EIC)) {
514 sltsta ^= PCI_EXP_SLTSTA_EIS;
515 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
516 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
517 "sltsta -> 0x%02"PRIx16"\n",
518 sltsta);
519 }
520
521
522
523
524
525 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
526 ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) {
527 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
528 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
529 pcie_unplug_device, NULL);
530
531 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
532 PCI_EXP_SLTSTA_PDS);
533 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
534 PCI_EXP_SLTSTA_PDC);
535 }
536
537 hotplug_event_notify(dev);
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
556}
557
558int pcie_cap_slot_post_load(void *opaque, int version_id)
559{
560 PCIDevice *dev = opaque;
561 hotplug_event_update_event_status(dev);
562 return 0;
563}
564
565void pcie_cap_slot_push_attention_button(PCIDevice *dev)
566{
567 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
568}
569
570
571void pcie_cap_root_init(PCIDevice *dev)
572{
573 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
574 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
575 PCI_EXP_RTCTL_SEFEE);
576}
577
578void pcie_cap_root_reset(PCIDevice *dev)
579{
580 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
581}
582
583
584void pcie_cap_flr_init(PCIDevice *dev)
585{
586 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
587 PCI_EXP_DEVCAP_FLR);
588
589
590
591
592
593
594 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
595 PCI_EXP_DEVCTL_BCR_FLR);
596}
597
598void pcie_cap_flr_write_config(PCIDevice *dev,
599 uint32_t addr, uint32_t val, int len)
600{
601 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
602 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
603
604
605 pci_device_reset(dev);
606 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
607 }
608}
609
610
611
612
613void pcie_cap_arifwd_init(PCIDevice *dev)
614{
615 uint32_t pos = dev->exp.exp_cap;
616 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
617 PCI_EXP_DEVCAP2_ARI);
618 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
619 PCI_EXP_DEVCTL2_ARI);
620}
621
622void pcie_cap_arifwd_reset(PCIDevice *dev)
623{
624 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
625 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
626}
627
628bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
629{
630 if (!pci_is_express(dev)) {
631 return false;
632 }
633 if (!dev->exp.exp_cap) {
634 return false;
635 }
636
637 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
638 PCI_EXP_DEVCTL2_ARI;
639}
640
641
642
643
644
645
646
647
648
649
650static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id,
651 uint16_t *prev_p)
652{
653 uint16_t prev = 0;
654 uint16_t next;
655 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
656
657 if (!header) {
658
659 next = 0;
660 goto out;
661 }
662 for (next = PCI_CONFIG_SPACE_SIZE; next;
663 prev = next, next = PCI_EXT_CAP_NEXT(header)) {
664
665 assert(next >= PCI_CONFIG_SPACE_SIZE);
666 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
667
668 header = pci_get_long(dev->config + next);
669 if (PCI_EXT_CAP_ID(header) == cap_id) {
670 break;
671 }
672 }
673
674out:
675 if (prev_p) {
676 *prev_p = prev;
677 }
678 return next;
679}
680
681uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
682{
683 return pcie_find_capability_list(dev, cap_id, NULL);
684}
685
686static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
687{
688 uint32_t header = pci_get_long(dev->config + pos);
689 assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
690 header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
691 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
692 pci_set_long(dev->config + pos, header);
693}
694
695
696
697
698
699
700void pcie_add_capability(PCIDevice *dev,
701 uint16_t cap_id, uint8_t cap_ver,
702 uint16_t offset, uint16_t size)
703{
704 assert(offset >= PCI_CONFIG_SPACE_SIZE);
705 assert(offset < offset + size);
706 assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
707 assert(size >= 8);
708 assert(pci_is_express(dev));
709
710 if (offset != PCI_CONFIG_SPACE_SIZE) {
711 uint16_t prev;
712
713
714
715
716
717 pcie_find_capability_list(dev, 0xffffffff, &prev);
718 assert(prev >= PCI_CONFIG_SPACE_SIZE);
719 pcie_ext_cap_set_next(dev, prev, offset);
720 }
721 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0));
722
723
724 memset(dev->wmask + offset, 0, size);
725 memset(dev->w1cmask + offset, 0, size);
726
727 memset(dev->cmask + offset, 0xFF, size);
728}
729
730
731
732
733
734
735void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
736{
737 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
738 offset, PCI_ARI_SIZEOF);
739 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
740}
741
742void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
743{
744 static const int pci_dsn_ver = 1;
745 static const int pci_dsn_cap = 4;
746
747 pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset,
748 PCI_EXT_CAP_DSN_SIZEOF);
749 pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
750}
751
752void pcie_ats_init(PCIDevice *dev, uint16_t offset)
753{
754 pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
755 offset, PCI_EXT_CAP_ATS_SIZEOF);
756
757 dev->exp.ats_cap = offset;
758
759
760 pci_set_word(dev->config + offset + PCI_ATS_CAP, 0);
761
762 pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
763
764 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f);
765}
766