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19#include "qemu/osdep.h"
20#include "sysemu/sysemu.h"
21#include "qapi/error.h"
22#include "qemu/log.h"
23#include "target/ppc/cpu.h"
24#include "hw/ppc/ppc.h"
25#include "hw/ppc/pnv.h"
26#include "hw/ppc/pnv_core.h"
27#include "hw/ppc/pnv_xscom.h"
28#include "hw/ppc/xics.h"
29
30static const char *pnv_core_cpu_typename(PnvCore *pc)
31{
32 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
33 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
34 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
35 const char *cpu_type = object_class_get_name(object_class_by_name(s));
36 g_free(s);
37 return cpu_type;
38}
39
40static void powernv_cpu_reset(void *opaque)
41{
42 PowerPCCPU *cpu = opaque;
43 CPUState *cs = CPU(cpu);
44 CPUPPCState *env = &cpu->env;
45
46 cpu_reset(cs);
47
48
49
50
51
52 env->gpr[3] = PNV_FDT_ADDR;
53 env->nip = 0x10;
54 env->msr |= MSR_HVB;
55}
56
57static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
58{
59 CPUPPCState *env = &cpu->env;
60 int core_pir;
61 int thread_index = 0;
62 ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
63
64 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
65
66
67
68
69
70
71 pir->default_value = core_pir + thread_index;
72
73
74 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
75
76 qemu_register_reset(powernv_cpu_reset, cpu);
77}
78
79
80
81
82#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
83#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
84
85static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
86 unsigned int width)
87{
88 uint32_t offset = addr >> 3;
89 uint64_t val = 0;
90
91
92 switch (offset) {
93 case PNV_XSCOM_EX_DTS_RESULT0:
94 val = 0x26f024f023f0000ull;
95 break;
96 case PNV_XSCOM_EX_DTS_RESULT1:
97 val = 0x24f000000000000ull;
98 break;
99 default:
100 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx,
101 addr);
102 }
103
104 return val;
105}
106
107static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
108 unsigned int width)
109{
110 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx,
111 addr);
112}
113
114static const MemoryRegionOps pnv_core_xscom_ops = {
115 .read = pnv_core_xscom_read,
116 .write = pnv_core_xscom_write,
117 .valid.min_access_size = 8,
118 .valid.max_access_size = 8,
119 .impl.min_access_size = 8,
120 .impl.max_access_size = 8,
121 .endianness = DEVICE_BIG_ENDIAN,
122};
123
124static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp)
125{
126 Error *local_err = NULL;
127 CPUState *cs = CPU(child);
128 PowerPCCPU *cpu = POWERPC_CPU(cs);
129 Object *obj;
130
131 object_property_set_bool(child, true, "realized", &local_err);
132 if (local_err) {
133 error_propagate(errp, local_err);
134 return;
135 }
136
137 obj = object_new(TYPE_PNV_ICP);
138 object_property_add_child(child, "icp", obj, NULL);
139 object_unref(obj);
140 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
141 &error_abort);
142 object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort);
143 object_property_set_bool(obj, true, "realized", &local_err);
144 if (local_err) {
145 error_propagate(errp, local_err);
146 return;
147 }
148
149 powernv_cpu_init(cpu, &local_err);
150 if (local_err) {
151 object_unparent(obj);
152 error_propagate(errp, local_err);
153 return;
154 }
155}
156
157static void pnv_core_realize(DeviceState *dev, Error **errp)
158{
159 PnvCore *pc = PNV_CORE(OBJECT(dev));
160 CPUCore *cc = CPU_CORE(OBJECT(dev));
161 const char *typename = pnv_core_cpu_typename(pc);
162 size_t size = object_type_get_instance_size(typename);
163 Error *local_err = NULL;
164 void *obj;
165 int i, j;
166 char name[32];
167 Object *xi;
168
169 xi = object_property_get_link(OBJECT(dev), "xics", &local_err);
170 if (!xi) {
171 error_setg(errp, "%s: required link 'xics' not found: %s",
172 __func__, error_get_pretty(local_err));
173 return;
174 }
175
176 pc->threads = g_malloc0(size * cc->nr_threads);
177 for (i = 0; i < cc->nr_threads; i++) {
178 obj = pc->threads + i * size;
179
180 object_initialize(obj, size, typename);
181
182 snprintf(name, sizeof(name), "thread[%d]", i);
183 object_property_add_child(OBJECT(pc), name, obj, &local_err);
184 object_property_add_alias(obj, "core-pir", OBJECT(pc),
185 "pir", &local_err);
186 if (local_err) {
187 goto err;
188 }
189 object_unref(obj);
190 }
191
192 for (j = 0; j < cc->nr_threads; j++) {
193 obj = pc->threads + j * size;
194
195 pnv_core_realize_child(obj, XICS_FABRIC(xi), &local_err);
196 if (local_err) {
197 goto err;
198 }
199 }
200
201 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
202 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
203 pc, name, PNV_XSCOM_EX_CORE_SIZE);
204 return;
205
206err:
207 while (--i >= 0) {
208 obj = pc->threads + i * size;
209 object_unparent(obj);
210 }
211 g_free(pc->threads);
212 error_propagate(errp, local_err);
213}
214
215static Property pnv_core_properties[] = {
216 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
217 DEFINE_PROP_END_OF_LIST(),
218};
219
220static void pnv_core_class_init(ObjectClass *oc, void *data)
221{
222 DeviceClass *dc = DEVICE_CLASS(oc);
223
224 dc->realize = pnv_core_realize;
225 dc->props = pnv_core_properties;
226}
227
228#define DEFINE_PNV_CORE_TYPE(cpu_model) \
229 { \
230 .parent = TYPE_PNV_CORE, \
231 .name = PNV_CORE_TYPE_NAME(cpu_model), \
232 }
233
234static const TypeInfo pnv_core_infos[] = {
235 {
236 .name = TYPE_PNV_CORE,
237 .parent = TYPE_CPU_CORE,
238 .instance_size = sizeof(PnvCore),
239 .class_size = sizeof(PnvCoreClass),
240 .class_init = pnv_core_class_init,
241 .abstract = true,
242 },
243 DEFINE_PNV_CORE_TYPE("power8e_v2.1"),
244 DEFINE_PNV_CORE_TYPE("power8_v2.0"),
245 DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"),
246 DEFINE_PNV_CORE_TYPE("power9_v2.0"),
247};
248
249DEFINE_TYPES(pnv_core_infos)
250
