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19#ifndef hw_omap_h
20#include "exec/memory.h"
21# define hw_omap_h "omap.h"
22#include "hw/irq.h"
23#include "target/arm/cpu-qom.h"
24
25# define OMAP_EMIFS_BASE 0x00000000
26# define OMAP2_Q0_BASE 0x00000000
27# define OMAP_CS0_BASE 0x00000000
28# define OMAP_CS1_BASE 0x04000000
29# define OMAP_CS2_BASE 0x08000000
30# define OMAP_CS3_BASE 0x0c000000
31# define OMAP_EMIFF_BASE 0x10000000
32# define OMAP_IMIF_BASE 0x20000000
33# define OMAP_LOCALBUS_BASE 0x30000000
34# define OMAP2_Q1_BASE 0x40000000
35# define OMAP2_L4_BASE 0x48000000
36# define OMAP2_SRAM_BASE 0x40200000
37# define OMAP2_L3_BASE 0x68000000
38# define OMAP2_Q2_BASE 0x80000000
39# define OMAP2_Q3_BASE 0xc0000000
40# define OMAP_MPUI_BASE 0xe1000000
41
42# define OMAP730_SRAM_SIZE 0x00032000
43# define OMAP15XX_SRAM_SIZE 0x00030000
44# define OMAP16XX_SRAM_SIZE 0x00004000
45# define OMAP1611_SRAM_SIZE 0x0003e800
46# define OMAP242X_SRAM_SIZE 0x000a0000
47# define OMAP243X_SRAM_SIZE 0x00010000
48# define OMAP_CS0_SIZE 0x04000000
49# define OMAP_CS1_SIZE 0x04000000
50# define OMAP_CS2_SIZE 0x04000000
51# define OMAP_CS3_SIZE 0x04000000
52
53
54struct omap_mpu_state_s;
55typedef struct clk *omap_clk;
56omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
57void omap_clk_init(struct omap_mpu_state_s *mpu);
58void omap_clk_adduser(struct clk *clk, qemu_irq user);
59void omap_clk_get(omap_clk clk);
60void omap_clk_put(omap_clk clk);
61void omap_clk_onoff(omap_clk clk, int on);
62void omap_clk_canidle(omap_clk clk, int can);
63void omap_clk_setrate(omap_clk clk, int divide, int multiply);
64int64_t omap_clk_getrate(omap_clk clk);
65void omap_clk_reparent(omap_clk clk, omap_clk parent);
66
67
68struct omap_l4_s;
69struct omap_l4_region_s {
70 hwaddr offset;
71 size_t size;
72 int access;
73};
74struct omap_l4_agent_info_s {
75 int ta;
76 int region;
77 int regions;
78 int ta_region;
79};
80struct omap_target_agent_s {
81 MemoryRegion iomem;
82 struct omap_l4_s *bus;
83 int regions;
84 const struct omap_l4_region_s *start;
85 hwaddr base;
86 uint32_t component;
87 uint32_t control;
88 uint32_t status;
89};
90struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
91 hwaddr base, int ta_num);
92
93struct omap_target_agent_s;
94struct omap_target_agent_s *omap_l4ta_get(
95 struct omap_l4_s *bus,
96 const struct omap_l4_region_s *regions,
97 const struct omap_l4_agent_info_s *agents,
98 int cs);
99hwaddr omap_l4_attach(struct omap_target_agent_s *ta,
100 int region, MemoryRegion *mr);
101hwaddr omap_l4_region_base(struct omap_target_agent_s *ta,
102 int region);
103hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
104 int region);
105
106
107struct omap_sdrc_s;
108struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
109 hwaddr base);
110void omap_sdrc_reset(struct omap_sdrc_s *s);
111
112
113struct omap_gpmc_s;
114struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
115 hwaddr base,
116 qemu_irq irq, qemu_irq drq);
117void omap_gpmc_reset(struct omap_gpmc_s *s);
118void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
119void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
120
121
122
123
124
125# define OMAP_INT_CAMERA 1
126# define OMAP_INT_FIQ 3
127# define OMAP_INT_RTDX 6
128# define OMAP_INT_DSP_MMU_ABORT 7
129# define OMAP_INT_HOST 8
130# define OMAP_INT_ABORT 9
131# define OMAP_INT_BRIDGE_PRIV 13
132# define OMAP_INT_GPIO_BANK1 14
133# define OMAP_INT_UART3 15
134# define OMAP_INT_TIMER3 16
135# define OMAP_INT_DMA_CH0_6 19
136# define OMAP_INT_DMA_CH1_7 20
137# define OMAP_INT_DMA_CH2_8 21
138# define OMAP_INT_DMA_CH3 22
139# define OMAP_INT_DMA_CH4 23
140# define OMAP_INT_DMA_CH5 24
141# define OMAP_INT_DMA_LCD 25
142# define OMAP_INT_TIMER1 26
143# define OMAP_INT_WD_TIMER 27
144# define OMAP_INT_BRIDGE_PUB 28
145# define OMAP_INT_TIMER2 30
146# define OMAP_INT_LCD_CTRL 31
147
148
149
150
151# define OMAP_INT_15XX_IH2_IRQ 0
152# define OMAP_INT_15XX_LB_MMU 17
153# define OMAP_INT_15XX_LOCAL_BUS 29
154
155
156
157
158# define OMAP_INT_1510_SPI_TX 4
159# define OMAP_INT_1510_SPI_RX 5
160# define OMAP_INT_1510_DSP_MAILBOX1 10
161# define OMAP_INT_1510_DSP_MAILBOX2 11
162
163
164
165
166# define OMAP_INT_310_McBSP2_TX 4
167# define OMAP_INT_310_McBSP2_RX 5
168# define OMAP_INT_310_HSB_MAILBOX1 12
169# define OMAP_INT_310_HSAB_MMU 18
170
171
172
173
174# define OMAP_INT_1610_IH2_IRQ 0
175# define OMAP_INT_1610_IH2_FIQ 2
176# define OMAP_INT_1610_McBSP2_TX 4
177# define OMAP_INT_1610_McBSP2_RX 5
178# define OMAP_INT_1610_DSP_MAILBOX1 10
179# define OMAP_INT_1610_DSP_MAILBOX2 11
180# define OMAP_INT_1610_LCD_LINE 12
181# define OMAP_INT_1610_GPTIMER1 17
182# define OMAP_INT_1610_GPTIMER2 18
183# define OMAP_INT_1610_SSR_FIFO_0 29
184
185
186
187
188# define OMAP_INT_730_IH2_FIQ 0
189# define OMAP_INT_730_IH2_IRQ 1
190# define OMAP_INT_730_USB_NON_ISO 2
191# define OMAP_INT_730_USB_ISO 3
192# define OMAP_INT_730_ICR 4
193# define OMAP_INT_730_EAC 5
194# define OMAP_INT_730_GPIO_BANK1 6
195# define OMAP_INT_730_GPIO_BANK2 7
196# define OMAP_INT_730_GPIO_BANK3 8
197# define OMAP_INT_730_McBSP2TX 10
198# define OMAP_INT_730_McBSP2RX 11
199# define OMAP_INT_730_McBSP2RX_OVF 12
200# define OMAP_INT_730_LCD_LINE 14
201# define OMAP_INT_730_GSM_PROTECT 15
202# define OMAP_INT_730_TIMER3 16
203# define OMAP_INT_730_GPIO_BANK5 17
204# define OMAP_INT_730_GPIO_BANK6 18
205# define OMAP_INT_730_SPGIO_WR 29
206
207
208
209
210# define OMAP_INT_KEYBOARD 1
211# define OMAP_INT_uWireTX 2
212# define OMAP_INT_uWireRX 3
213# define OMAP_INT_I2C 4
214# define OMAP_INT_MPUIO 5
215# define OMAP_INT_USB_HHC_1 6
216# define OMAP_INT_McBSP3TX 10
217# define OMAP_INT_McBSP3RX 11
218# define OMAP_INT_McBSP1TX 12
219# define OMAP_INT_McBSP1RX 13
220# define OMAP_INT_UART1 14
221# define OMAP_INT_UART2 15
222# define OMAP_INT_USB_W2FC 20
223# define OMAP_INT_1WIRE 21
224# define OMAP_INT_OS_TIMER 22
225# define OMAP_INT_OQN 23
226# define OMAP_INT_GAUGE_32K 24
227# define OMAP_INT_RTC_TIMER 25
228# define OMAP_INT_RTC_ALARM 26
229# define OMAP_INT_DSP_MMU 28
230
231
232
233
234# define OMAP_INT_1510_BT_MCSI1TX 16
235# define OMAP_INT_1510_BT_MCSI1RX 17
236# define OMAP_INT_1510_SoSSI_MATCH 19
237# define OMAP_INT_1510_MEM_STICK 27
238# define OMAP_INT_1510_COM_SPI_RO 31
239
240
241
242
243# define OMAP_INT_310_FAC 0
244# define OMAP_INT_310_USB_HHC_2 7
245# define OMAP_INT_310_MCSI1_FE 16
246# define OMAP_INT_310_MCSI2_FE 17
247# define OMAP_INT_310_USB_W2FC_ISO 29
248# define OMAP_INT_310_USB_W2FC_NON_ISO 30
249# define OMAP_INT_310_McBSP2RX_OF 31
250
251
252
253
254# define OMAP_INT_1610_FAC 0
255# define OMAP_INT_1610_USB_HHC_2 7
256# define OMAP_INT_1610_USB_OTG 8
257# define OMAP_INT_1610_SoSSI 9
258# define OMAP_INT_1610_BT_MCSI1TX 16
259# define OMAP_INT_1610_BT_MCSI1RX 17
260# define OMAP_INT_1610_SoSSI_MATCH 19
261# define OMAP_INT_1610_MEM_STICK 27
262# define OMAP_INT_1610_McBSP2RX_OF 31
263# define OMAP_INT_1610_STI 32
264# define OMAP_INT_1610_STI_WAKEUP 33
265# define OMAP_INT_1610_GPTIMER3 34
266# define OMAP_INT_1610_GPTIMER4 35
267# define OMAP_INT_1610_GPTIMER5 36
268# define OMAP_INT_1610_GPTIMER6 37
269# define OMAP_INT_1610_GPTIMER7 38
270# define OMAP_INT_1610_GPTIMER8 39
271# define OMAP_INT_1610_GPIO_BANK2 40
272# define OMAP_INT_1610_GPIO_BANK3 41
273# define OMAP_INT_1610_MMC2 42
274# define OMAP_INT_1610_CF 43
275# define OMAP_INT_1610_WAKE_UP_REQ 46
276# define OMAP_INT_1610_GPIO_BANK4 48
277# define OMAP_INT_1610_SPI 49
278# define OMAP_INT_1610_DMA_CH6 53
279# define OMAP_INT_1610_DMA_CH7 54
280# define OMAP_INT_1610_DMA_CH8 55
281# define OMAP_INT_1610_DMA_CH9 56
282# define OMAP_INT_1610_DMA_CH10 57
283# define OMAP_INT_1610_DMA_CH11 58
284# define OMAP_INT_1610_DMA_CH12 59
285# define OMAP_INT_1610_DMA_CH13 60
286# define OMAP_INT_1610_DMA_CH14 61
287# define OMAP_INT_1610_DMA_CH15 62
288# define OMAP_INT_1610_NAND 63
289
290
291
292
293# define OMAP_INT_730_HW_ERRORS 0
294# define OMAP_INT_730_NFIQ_PWR_FAIL 1
295# define OMAP_INT_730_CFCD 2
296# define OMAP_INT_730_CFIREQ 3
297# define OMAP_INT_730_I2C 4
298# define OMAP_INT_730_PCC 5
299# define OMAP_INT_730_MPU_EXT_NIRQ 6
300# define OMAP_INT_730_SPI_100K_1 7
301# define OMAP_INT_730_SYREN_SPI 8
302# define OMAP_INT_730_VLYNQ 9
303# define OMAP_INT_730_GPIO_BANK4 10
304# define OMAP_INT_730_McBSP1TX 11
305# define OMAP_INT_730_McBSP1RX 12
306# define OMAP_INT_730_McBSP1RX_OF 13
307# define OMAP_INT_730_UART_MODEM_IRDA_2 14
308# define OMAP_INT_730_UART_MODEM_1 15
309# define OMAP_INT_730_MCSI 16
310# define OMAP_INT_730_uWireTX 17
311# define OMAP_INT_730_uWireRX 18
312# define OMAP_INT_730_SMC_CD 19
313# define OMAP_INT_730_SMC_IREQ 20
314# define OMAP_INT_730_HDQ_1WIRE 21
315# define OMAP_INT_730_TIMER32K 22
316# define OMAP_INT_730_MMC_SDIO 23
317# define OMAP_INT_730_UPLD 24
318# define OMAP_INT_730_USB_HHC_1 27
319# define OMAP_INT_730_USB_HHC_2 28
320# define OMAP_INT_730_USB_GENI 29
321# define OMAP_INT_730_USB_OTG 30
322# define OMAP_INT_730_CAMERA_IF 31
323# define OMAP_INT_730_RNG 32
324# define OMAP_INT_730_DUAL_MODE_TIMER 33
325# define OMAP_INT_730_DBB_RF_EN 34
326# define OMAP_INT_730_MPUIO_KEYPAD 35
327# define OMAP_INT_730_SHA1_MD5 36
328# define OMAP_INT_730_SPI_100K_2 37
329# define OMAP_INT_730_RNG_IDLE 38
330# define OMAP_INT_730_MPUIO 39
331# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
332# define OMAP_INT_730_LLPC_OE_FALLING 41
333# define OMAP_INT_730_LLPC_OE_RISING 42
334# define OMAP_INT_730_LLPC_VSYNC 43
335# define OMAP_INT_730_WAKE_UP_REQ 46
336# define OMAP_INT_730_DMA_CH6 53
337# define OMAP_INT_730_DMA_CH7 54
338# define OMAP_INT_730_DMA_CH8 55
339# define OMAP_INT_730_DMA_CH9 56
340# define OMAP_INT_730_DMA_CH10 57
341# define OMAP_INT_730_DMA_CH11 58
342# define OMAP_INT_730_DMA_CH12 59
343# define OMAP_INT_730_DMA_CH13 60
344# define OMAP_INT_730_DMA_CH14 61
345# define OMAP_INT_730_DMA_CH15 62
346# define OMAP_INT_730_NAND 63
347
348
349
350
351# define OMAP_INT_24XX_STI 4
352# define OMAP_INT_24XX_SYS_NIRQ 7
353# define OMAP_INT_24XX_L3_IRQ 10
354# define OMAP_INT_24XX_PRCM_MPU_IRQ 11
355# define OMAP_INT_24XX_SDMA_IRQ0 12
356# define OMAP_INT_24XX_SDMA_IRQ1 13
357# define OMAP_INT_24XX_SDMA_IRQ2 14
358# define OMAP_INT_24XX_SDMA_IRQ3 15
359# define OMAP_INT_243X_MCBSP2_IRQ 16
360# define OMAP_INT_243X_MCBSP3_IRQ 17
361# define OMAP_INT_243X_MCBSP4_IRQ 18
362# define OMAP_INT_243X_MCBSP5_IRQ 19
363# define OMAP_INT_24XX_GPMC_IRQ 20
364# define OMAP_INT_24XX_GUFFAW_IRQ 21
365# define OMAP_INT_24XX_IVA_IRQ 22
366# define OMAP_INT_24XX_EAC_IRQ 23
367# define OMAP_INT_24XX_CAM_IRQ 24
368# define OMAP_INT_24XX_DSS_IRQ 25
369# define OMAP_INT_24XX_MAIL_U0_MPU 26
370# define OMAP_INT_24XX_DSP_UMA 27
371# define OMAP_INT_24XX_DSP_MMU 28
372# define OMAP_INT_24XX_GPIO_BANK1 29
373# define OMAP_INT_24XX_GPIO_BANK2 30
374# define OMAP_INT_24XX_GPIO_BANK3 31
375# define OMAP_INT_24XX_GPIO_BANK4 32
376# define OMAP_INT_243X_GPIO_BANK5 33
377# define OMAP_INT_24XX_MAIL_U3_MPU 34
378# define OMAP_INT_24XX_WDT3 35
379# define OMAP_INT_24XX_WDT4 36
380# define OMAP_INT_24XX_GPTIMER1 37
381# define OMAP_INT_24XX_GPTIMER2 38
382# define OMAP_INT_24XX_GPTIMER3 39
383# define OMAP_INT_24XX_GPTIMER4 40
384# define OMAP_INT_24XX_GPTIMER5 41
385# define OMAP_INT_24XX_GPTIMER6 42
386# define OMAP_INT_24XX_GPTIMER7 43
387# define OMAP_INT_24XX_GPTIMER8 44
388# define OMAP_INT_24XX_GPTIMER9 45
389# define OMAP_INT_24XX_GPTIMER10 46
390# define OMAP_INT_24XX_GPTIMER11 47
391# define OMAP_INT_24XX_GPTIMER12 48
392# define OMAP_INT_24XX_PKA_IRQ 50
393# define OMAP_INT_24XX_SHA1MD5_IRQ 51
394# define OMAP_INT_24XX_RNG_IRQ 52
395# define OMAP_INT_24XX_MG_IRQ 53
396# define OMAP_INT_24XX_I2C1_IRQ 56
397# define OMAP_INT_24XX_I2C2_IRQ 57
398# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
399# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
400# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
401# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
402# define OMAP_INT_243X_MCBSP1_IRQ 64
403# define OMAP_INT_24XX_MCSPI1_IRQ 65
404# define OMAP_INT_24XX_MCSPI2_IRQ 66
405# define OMAP_INT_24XX_SSI1_IRQ0 67
406# define OMAP_INT_24XX_SSI1_IRQ1 68
407# define OMAP_INT_24XX_SSI2_IRQ0 69
408# define OMAP_INT_24XX_SSI2_IRQ1 70
409# define OMAP_INT_24XX_SSI_GDD_IRQ 71
410# define OMAP_INT_24XX_UART1_IRQ 72
411# define OMAP_INT_24XX_UART2_IRQ 73
412# define OMAP_INT_24XX_UART3_IRQ 74
413# define OMAP_INT_24XX_USB_IRQ_GEN 75
414# define OMAP_INT_24XX_USB_IRQ_NISO 76
415# define OMAP_INT_24XX_USB_IRQ_ISO 77
416# define OMAP_INT_24XX_USB_IRQ_HGEN 78
417# define OMAP_INT_24XX_USB_IRQ_HSOF 79
418# define OMAP_INT_24XX_USB_IRQ_OTG 80
419# define OMAP_INT_24XX_VLYNQ_IRQ 81
420# define OMAP_INT_24XX_MMC_IRQ 83
421# define OMAP_INT_24XX_MS_IRQ 84
422# define OMAP_INT_24XX_FAC_IRQ 85
423# define OMAP_INT_24XX_MCSPI3_IRQ 91
424# define OMAP_INT_243X_HS_USB_MC 92
425# define OMAP_INT_243X_HS_USB_DMA 93
426# define OMAP_INT_243X_CARKIT 94
427# define OMAP_INT_34XX_GPTIMER12 95
428
429
430enum omap_dma_model {
431 omap_dma_3_0,
432 omap_dma_3_1,
433 omap_dma_3_2,
434 omap_dma_4,
435};
436
437struct soc_dma_s;
438struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
439 MemoryRegion *sysmem,
440 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
441 enum omap_dma_model model);
442struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
443 MemoryRegion *sysmem,
444 struct omap_mpu_state_s *mpu, int fifo,
445 int chans, omap_clk iclk, omap_clk fclk);
446void omap_dma_reset(struct soc_dma_s *s);
447
448struct dma_irq_map {
449 int ih;
450 int intr;
451};
452
453
454enum omap_dma_port {
455 emiff = 0,
456 emifs,
457 imif,
458 tipb,
459 local,
460 tipb_mpui,
461 __omap_dma_port_last,
462};
463
464typedef enum {
465 constant = 0,
466 post_incremented,
467 single_index,
468 double_index,
469} omap_dma_addressing_t;
470
471
472struct omap_dma_lcd_channel_s {
473 enum omap_dma_port src;
474 hwaddr src_f1_top;
475 hwaddr src_f1_bottom;
476 hwaddr src_f2_top;
477 hwaddr src_f2_bottom;
478
479
480 unsigned char brust_f1;
481 unsigned char pack_f1;
482 unsigned char data_type_f1;
483 unsigned char brust_f2;
484 unsigned char pack_f2;
485 unsigned char data_type_f2;
486 unsigned char end_prog;
487 unsigned char repeat;
488 unsigned char auto_init;
489 unsigned char priority;
490 unsigned char fs;
491 unsigned char running;
492 unsigned char bs;
493 unsigned char omap_3_1_compatible_disable;
494 unsigned char dst;
495 unsigned char lch_type;
496 int16_t element_index_f1;
497 int16_t element_index_f2;
498 int32_t frame_index_f1;
499 int32_t frame_index_f2;
500 uint16_t elements_f1;
501 uint16_t frames_f1;
502 uint16_t elements_f2;
503 uint16_t frames_f2;
504 omap_dma_addressing_t mode_f1;
505 omap_dma_addressing_t mode_f2;
506
507
508 int interrupts;
509 int condition;
510 int dual;
511
512 int current_frame;
513 hwaddr phys_framebuffer[2];
514 qemu_irq irq;
515 struct omap_mpu_state_s *mpu;
516} *omap_dma_get_lcdch(struct soc_dma_s *s);
517
518
519
520
521
522# define OMAP_DMA_NO_DEVICE 0
523# define OMAP_DMA_MCSI1_TX 1
524# define OMAP_DMA_MCSI1_RX 2
525# define OMAP_DMA_I2C_RX 3
526# define OMAP_DMA_I2C_TX 4
527# define OMAP_DMA_EXT_NDMA_REQ0 5
528# define OMAP_DMA_EXT_NDMA_REQ1 6
529# define OMAP_DMA_UWIRE_TX 7
530# define OMAP_DMA_MCBSP1_TX 8
531# define OMAP_DMA_MCBSP1_RX 9
532# define OMAP_DMA_MCBSP3_TX 10
533# define OMAP_DMA_MCBSP3_RX 11
534# define OMAP_DMA_UART1_TX 12
535# define OMAP_DMA_UART1_RX 13
536# define OMAP_DMA_UART2_TX 14
537# define OMAP_DMA_UART2_RX 15
538# define OMAP_DMA_MCBSP2_TX 16
539# define OMAP_DMA_MCBSP2_RX 17
540# define OMAP_DMA_UART3_TX 18
541# define OMAP_DMA_UART3_RX 19
542# define OMAP_DMA_CAMERA_IF_RX 20
543# define OMAP_DMA_MMC_TX 21
544# define OMAP_DMA_MMC_RX 22
545# define OMAP_DMA_NAND 23
546# define OMAP_DMA_IRQ_LCD_LINE 24
547# define OMAP_DMA_MEMORY_STICK 25
548# define OMAP_DMA_USB_W2FC_RX0 26
549# define OMAP_DMA_USB_W2FC_RX1 27
550# define OMAP_DMA_USB_W2FC_RX2 28
551# define OMAP_DMA_USB_W2FC_TX0 29
552# define OMAP_DMA_USB_W2FC_TX1 30
553# define OMAP_DMA_USB_W2FC_TX2 31
554
555
556# define OMAP_DMA_CRYPTO_DES_IN 32
557# define OMAP_DMA_SPI_TX 33
558# define OMAP_DMA_SPI_RX 34
559# define OMAP_DMA_CRYPTO_HASH 35
560# define OMAP_DMA_CCP_ATTN 36
561# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
562# define OMAP_DMA_CMT_APE_TX_CHAN_0 38
563# define OMAP_DMA_CMT_APE_RV_CHAN_0 39
564# define OMAP_DMA_CMT_APE_TX_CHAN_1 40
565# define OMAP_DMA_CMT_APE_RV_CHAN_1 41
566# define OMAP_DMA_CMT_APE_TX_CHAN_2 42
567# define OMAP_DMA_CMT_APE_RV_CHAN_2 43
568# define OMAP_DMA_CMT_APE_TX_CHAN_3 44
569# define OMAP_DMA_CMT_APE_RV_CHAN_3 45
570# define OMAP_DMA_CMT_APE_TX_CHAN_4 46
571# define OMAP_DMA_CMT_APE_RV_CHAN_4 47
572# define OMAP_DMA_CMT_APE_TX_CHAN_5 48
573# define OMAP_DMA_CMT_APE_RV_CHAN_5 49
574# define OMAP_DMA_CMT_APE_TX_CHAN_6 50
575# define OMAP_DMA_CMT_APE_RV_CHAN_6 51
576# define OMAP_DMA_CMT_APE_TX_CHAN_7 52
577# define OMAP_DMA_CMT_APE_RV_CHAN_7 53
578# define OMAP_DMA_MMC2_TX 54
579# define OMAP_DMA_MMC2_RX 55
580# define OMAP_DMA_CRYPTO_DES_OUT 56
581
582
583
584
585# define OMAP24XX_DMA_NO_DEVICE 0
586# define OMAP24XX_DMA_XTI_DMA 1
587# define OMAP24XX_DMA_EXT_DMAREQ0 2
588# define OMAP24XX_DMA_EXT_DMAREQ1 3
589# define OMAP24XX_DMA_GPMC 4
590# define OMAP24XX_DMA_GFX 5
591# define OMAP24XX_DMA_DSS 6
592# define OMAP24XX_DMA_VLYNQ_TX 7
593# define OMAP24XX_DMA_CWT 8
594# define OMAP24XX_DMA_AES_TX 9
595# define OMAP24XX_DMA_AES_RX 10
596# define OMAP24XX_DMA_DES_TX 11
597# define OMAP24XX_DMA_DES_RX 12
598# define OMAP24XX_DMA_SHA1MD5_RX 13
599# define OMAP24XX_DMA_EXT_DMAREQ2 14
600# define OMAP24XX_DMA_EXT_DMAREQ3 15
601# define OMAP24XX_DMA_EXT_DMAREQ4 16
602# define OMAP24XX_DMA_EAC_AC_RD 17
603# define OMAP24XX_DMA_EAC_AC_WR 18
604# define OMAP24XX_DMA_EAC_MD_UL_RD 19
605# define OMAP24XX_DMA_EAC_MD_UL_WR 20
606# define OMAP24XX_DMA_EAC_MD_DL_RD 21
607# define OMAP24XX_DMA_EAC_MD_DL_WR 22
608# define OMAP24XX_DMA_EAC_BT_UL_RD 23
609# define OMAP24XX_DMA_EAC_BT_UL_WR 24
610# define OMAP24XX_DMA_EAC_BT_DL_RD 25
611# define OMAP24XX_DMA_EAC_BT_DL_WR 26
612# define OMAP24XX_DMA_I2C1_TX 27
613# define OMAP24XX_DMA_I2C1_RX 28
614# define OMAP24XX_DMA_I2C2_TX 29
615# define OMAP24XX_DMA_I2C2_RX 30
616# define OMAP24XX_DMA_MCBSP1_TX 31
617# define OMAP24XX_DMA_MCBSP1_RX 32
618# define OMAP24XX_DMA_MCBSP2_TX 33
619# define OMAP24XX_DMA_MCBSP2_RX 34
620# define OMAP24XX_DMA_SPI1_TX0 35
621# define OMAP24XX_DMA_SPI1_RX0 36
622# define OMAP24XX_DMA_SPI1_TX1 37
623# define OMAP24XX_DMA_SPI1_RX1 38
624# define OMAP24XX_DMA_SPI1_TX2 39
625# define OMAP24XX_DMA_SPI1_RX2 40
626# define OMAP24XX_DMA_SPI1_TX3 41
627# define OMAP24XX_DMA_SPI1_RX3 42
628# define OMAP24XX_DMA_SPI2_TX0 43
629# define OMAP24XX_DMA_SPI2_RX0 44
630# define OMAP24XX_DMA_SPI2_TX1 45
631# define OMAP24XX_DMA_SPI2_RX1 46
632
633# define OMAP24XX_DMA_UART1_TX 49
634# define OMAP24XX_DMA_UART1_RX 50
635# define OMAP24XX_DMA_UART2_TX 51
636# define OMAP24XX_DMA_UART2_RX 52
637# define OMAP24XX_DMA_UART3_TX 53
638# define OMAP24XX_DMA_UART3_RX 54
639# define OMAP24XX_DMA_USB_W2FC_TX0 55
640# define OMAP24XX_DMA_USB_W2FC_RX0 56
641# define OMAP24XX_DMA_USB_W2FC_TX1 57
642# define OMAP24XX_DMA_USB_W2FC_RX1 58
643# define OMAP24XX_DMA_USB_W2FC_TX2 59
644# define OMAP24XX_DMA_USB_W2FC_RX2 60
645# define OMAP24XX_DMA_MMC1_TX 61
646# define OMAP24XX_DMA_MMC1_RX 62
647# define OMAP24XX_DMA_MS 63
648# define OMAP24XX_DMA_EXT_DMAREQ5 64
649
650
651
652struct omap_gp_timer_s;
653struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
654 qemu_irq irq, omap_clk fclk, omap_clk iclk);
655void omap_gp_timer_reset(struct omap_gp_timer_s *s);
656
657
658struct omap_synctimer_s;
659struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
660 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
661void omap_synctimer_reset(struct omap_synctimer_s *s);
662
663struct omap_uart_s;
664struct omap_uart_s *omap_uart_init(hwaddr base,
665 qemu_irq irq, omap_clk fclk, omap_clk iclk,
666 qemu_irq txdma, qemu_irq rxdma,
667 const char *label, Chardev *chr);
668struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
669 struct omap_target_agent_s *ta,
670 qemu_irq irq, omap_clk fclk, omap_clk iclk,
671 qemu_irq txdma, qemu_irq rxdma,
672 const char *label, Chardev *chr);
673void omap_uart_reset(struct omap_uart_s *s);
674void omap_uart_attach(struct omap_uart_s *s, Chardev *chr);
675
676struct omap_mpuio_s;
677qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
678void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
679void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
680
681struct uWireSlave {
682 uint16_t (*receive)(void *opaque);
683 void (*send)(void *opaque, uint16_t data);
684 void *opaque;
685};
686struct omap_uwire_s;
687void omap_uwire_attach(struct omap_uwire_s *s,
688 uWireSlave *slave, int chipselect);
689
690
691struct omap_mcspi_s;
692struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
693 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
694void omap_mcspi_attach(struct omap_mcspi_s *s,
695 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
696 int chipselect);
697void omap_mcspi_reset(struct omap_mcspi_s *s);
698
699struct I2SCodec {
700 void *opaque;
701
702
703
704
705 void (*set_rate)(void *opaque, int in, int out);
706
707 void (*tx_swallow)(void *opaque);
708 qemu_irq rx_swallow;
709 qemu_irq tx_start;
710
711 int tx_rate;
712 int cts;
713 int rx_rate;
714 int rts;
715
716 struct i2s_fifo_s {
717 uint8_t *fifo;
718 int len;
719 int start;
720 int size;
721 } in, out;
722};
723struct omap_mcbsp_s;
724void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
725
726void omap_tap_init(struct omap_target_agent_s *ta,
727 struct omap_mpu_state_s *mpu);
728
729
730struct omap_lcd_panel_s;
731void omap_lcdc_reset(struct omap_lcd_panel_s *s);
732struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
733 hwaddr base,
734 qemu_irq irq,
735 struct omap_dma_lcd_channel_s *dma,
736 omap_clk clk);
737
738
739struct rfbi_chip_s {
740 void *opaque;
741 void (*write)(void *opaque, int dc, uint16_t value);
742 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
743 uint16_t (*read)(void *opaque, int dc);
744};
745struct omap_dss_s;
746void omap_dss_reset(struct omap_dss_s *s);
747struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
748 MemoryRegion *sysmem,
749 hwaddr l3_base,
750 qemu_irq irq, qemu_irq drq,
751 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
752 omap_clk ick1, omap_clk ick2);
753void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
754
755
756struct omap_mmc_s;
757struct omap_mmc_s *omap_mmc_init(hwaddr base,
758 MemoryRegion *sysmem,
759 BlockBackend *blk,
760 qemu_irq irq, qemu_irq dma[], omap_clk clk);
761struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
762 BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
763 omap_clk fclk, omap_clk iclk);
764void omap_mmc_reset(struct omap_mmc_s *s);
765void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
766void omap_mmc_enable(struct omap_mmc_s *s, int enable);
767
768
769I2CBus *omap_i2c_bus(DeviceState *omap_i2c);
770
771# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
772# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
773# define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
774# define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
775# define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
776# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
777# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
778# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
779# define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630)
780
781# define cpu_is_omap15xx(cpu) \
782 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
783# define cpu_is_omap16xx(cpu) \
784 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
785# define cpu_is_omap24xx(cpu) \
786 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
787
788# define cpu_class_omap1(cpu) \
789 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
790# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
791# define cpu_class_omap3(cpu) \
792 (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
793
794struct omap_mpu_state_s {
795 enum omap_mpu_model {
796 omap310,
797 omap1510,
798 omap1610,
799 omap1710,
800 omap2410,
801 omap2420,
802 omap2422,
803 omap2423,
804 omap2430,
805 omap3430,
806 omap3630,
807 } mpu_model;
808
809 ARMCPU *cpu;
810
811 qemu_irq *drq;
812
813 qemu_irq wakeup;
814
815 MemoryRegion ulpd_pm_iomem;
816 MemoryRegion pin_cfg_iomem;
817 MemoryRegion id_iomem;
818 MemoryRegion id_iomem_e18;
819 MemoryRegion id_iomem_ed4;
820 MemoryRegion id_iomem_e20;
821 MemoryRegion mpui_iomem;
822 MemoryRegion tcmi_iomem;
823 MemoryRegion clkm_iomem;
824 MemoryRegion clkdsp_iomem;
825 MemoryRegion mpui_io_iomem;
826 MemoryRegion tap_iomem;
827 MemoryRegion imif_ram;
828 MemoryRegion emiff_ram;
829 MemoryRegion sdram;
830 MemoryRegion sram;
831
832 struct omap_dma_port_if_s {
833 uint32_t (*read[3])(struct omap_mpu_state_s *s,
834 hwaddr offset);
835 void (*write[3])(struct omap_mpu_state_s *s,
836 hwaddr offset, uint32_t value);
837 int (*addr_valid)(struct omap_mpu_state_s *s,
838 hwaddr addr);
839 } port[__omap_dma_port_last];
840
841 unsigned long sdram_size;
842 unsigned long sram_size;
843
844
845 struct omap_uart_s *uart[3];
846
847 DeviceState *gpio;
848
849 struct omap_mcbsp_s *mcbsp1;
850 struct omap_mcbsp_s *mcbsp3;
851
852
853 struct omap_32khz_timer_s *os_timer;
854
855 struct omap_mmc_s *mmc;
856
857 struct omap_mpuio_s *mpuio;
858
859 struct omap_uwire_s *microwire;
860
861 struct omap_pwl_s *pwl;
862 struct omap_pwt_s *pwt;
863 DeviceState *i2c[2];
864
865 struct omap_rtc_s *rtc;
866
867 struct omap_mcbsp_s *mcbsp2;
868
869 struct omap_lpg_s *led[2];
870
871
872 DeviceState *ih[2];
873
874 struct soc_dma_s *dma;
875
876 struct omap_mpu_timer_s *timer[3];
877 struct omap_watchdog_timer_s *wdt;
878
879 struct omap_lcd_panel_s *lcd;
880
881 uint32_t ulpd_pm_regs[21];
882 int64_t ulpd_gauge_start;
883
884 uint32_t func_mux_ctrl[14];
885 uint32_t comp_mode_ctrl[1];
886 uint32_t pull_dwn_ctrl[4];
887 uint32_t gate_inh_ctrl[1];
888 uint32_t voltage_ctrl[1];
889 uint32_t test_dbg_ctrl[1];
890 uint32_t mod_conf_ctrl[1];
891 int compat1509;
892
893 uint32_t mpui_ctrl;
894
895 struct omap_tipb_bridge_s *private_tipb;
896 struct omap_tipb_bridge_s *public_tipb;
897
898 uint32_t tcmi_regs[17];
899
900 struct dpll_ctl_s *dpll[3];
901
902 omap_clk clks;
903 struct {
904 int cold_start;
905 int clocking_scheme;
906 uint16_t arm_ckctl;
907 uint16_t arm_idlect1;
908 uint16_t arm_idlect2;
909 uint16_t arm_ewupct;
910 uint16_t arm_rstct1;
911 uint16_t arm_rstct2;
912 uint16_t arm_ckout1;
913 int dpll1_mode;
914 uint16_t dsp_idlect1;
915 uint16_t dsp_idlect2;
916 uint16_t dsp_rstct2;
917 } clkm;
918
919
920 struct omap_l4_s *l4;
921
922 struct omap_gp_timer_s *gptimer[12];
923 struct omap_synctimer_s *synctimer;
924
925 struct omap_prcm_s *prcm;
926 struct omap_sdrc_s *sdrc;
927 struct omap_gpmc_s *gpmc;
928 struct omap_sysctl_s *sysc;
929
930 struct omap_mcspi_s *mcspi[2];
931
932 struct omap_dss_s *dss;
933
934 struct omap_eac_s *eac;
935};
936
937
938struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
939 unsigned long sdram_size,
940 const char *core);
941
942
943struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
944 unsigned long sdram_size,
945 const char *core);
946
947#define OMAP_FMT_plx "%#08" HWADDR_PRIx
948
949uint32_t omap_badwidth_read8(void *opaque, hwaddr addr);
950void omap_badwidth_write8(void *opaque, hwaddr addr,
951 uint32_t value);
952uint32_t omap_badwidth_read16(void *opaque, hwaddr addr);
953void omap_badwidth_write16(void *opaque, hwaddr addr,
954 uint32_t value);
955uint32_t omap_badwidth_read32(void *opaque, hwaddr addr);
956void omap_badwidth_write32(void *opaque, hwaddr addr,
957 uint32_t value);
958
959void omap_mpu_wakeup(void *opaque, int irq, int req);
960
961# define OMAP_BAD_REG(paddr) \
962 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
963 __FUNCTION__, paddr)
964# define OMAP_RO_REG(paddr) \
965 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
966 __FUNCTION__, paddr)
967
968
969
970#define OMAP_TAG_CLOCK 0x4f01
971#define OMAP_TAG_MMC 0x4f02
972#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
973#define OMAP_TAG_USB 0x4f04
974#define OMAP_TAG_LCD 0x4f05
975#define OMAP_TAG_GPIO_SWITCH 0x4f06
976#define OMAP_TAG_UART 0x4f07
977#define OMAP_TAG_FBMEM 0x4f08
978#define OMAP_TAG_STI_CONSOLE 0x4f09
979#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
980#define OMAP_TAG_PARTITION 0x4f0b
981#define OMAP_TAG_TEA5761 0x4f10
982#define OMAP_TAG_TMP105 0x4f11
983#define OMAP_TAG_BOOT_REASON 0x4f80
984#define OMAP_TAG_FLASH_PART_STR 0x4f81
985#define OMAP_TAG_VERSION_STR 0x4f82
986
987enum {
988 OMAP_GPIOSW_TYPE_COVER = 0 << 4,
989 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
990 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
991};
992
993#define OMAP_GPIOSW_INVERTED 0x0001
994#define OMAP_GPIOSW_OUTPUT 0x0002
995
996# define TCMI_VERBOSE 1
997
998# ifdef TCMI_VERBOSE
999# define OMAP_8B_REG(paddr) \
1000 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1001 __FUNCTION__, paddr)
1002# define OMAP_16B_REG(paddr) \
1003 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1004 __FUNCTION__, paddr)
1005# define OMAP_32B_REG(paddr) \
1006 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1007 __FUNCTION__, paddr)
1008# else
1009# define OMAP_8B_REG(paddr)
1010# define OMAP_16B_REG(paddr)
1011# define OMAP_32B_REG(paddr)
1012# endif
1013
1014# define OMAP_MPUI_REG_MASK 0x000007ff
1015
1016#endif
1017