1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#ifndef QEMU_PCI_BRIDGE_H
27#define QEMU_PCI_BRIDGE_H
28
29#include "hw/pci/pci.h"
30
31#define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr"
32#define PCI_BRIDGE_DEV_PROP_MSI "msi"
33#define PCI_BRIDGE_DEV_PROP_SHPC "shpc"
34
35int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
36 uint16_t svid, uint16_t ssid,
37 Error **errp);
38
39PCIDevice *pci_bridge_get_device(PCIBus *bus);
40PCIBus *pci_bridge_get_sec_bus(PCIBridge *br);
41
42pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type);
43pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type);
44
45void pci_bridge_update_mappings(PCIBridge *br);
46void pci_bridge_write_config(PCIDevice *d,
47 uint32_t address, uint32_t val, int len);
48void pci_bridge_disable_base_limit(PCIDevice *dev);
49void pci_bridge_reset(DeviceState *qdev);
50
51void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename);
52void pci_bridge_exitfn(PCIDevice *pci_dev);
53
54
55
56
57
58
59
60void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
61 pci_map_irq_fn map_irq);
62
63
64#define PCI_BRIDGE_CTL_VGA_16BIT 0x10
65#define PCI_BRIDGE_CTL_DISCARD 0x100
66#define PCI_BRIDGE_CTL_SEC_DISCARD 0x200
67#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400
68#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800
69
70typedef struct PCIBridgeQemuCap {
71 uint8_t id;
72 uint8_t next;
73 uint8_t len;
74 uint8_t type;
75
76
77 uint32_t bus_res;
78 uint64_t io;
79 uint32_t mem;
80
81
82 uint32_t mem_pref_32;
83 uint64_t mem_pref_64;
84} PCIBridgeQemuCap;
85
86#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1
87
88int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
89 uint32_t bus_reserve, uint64_t io_reserve,
90 uint32_t mem_non_pref_reserve,
91 uint32_t mem_pref_32_reserve,
92 uint64_t mem_pref_64_reserve,
93 Error **errp);
94
95#endif
96