1/* 2 * QEMU CPU model 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20#ifndef QEMU_CPU_H 21#define QEMU_CPU_H 22 23#include "hw/qdev-core.h" 24#include "disas/bfd.h" 25#include "exec/hwaddr.h" 26#include "exec/memattrs.h" 27#include "qemu/bitmap.h" 28#include "qemu/queue.h" 29#include "qemu/thread.h" 30 31typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, 32 void *opaque); 33 34/** 35 * vaddr: 36 * Type wide enough to contain any #target_ulong virtual address. 37 */ 38typedef uint64_t vaddr; 39#define VADDR_PRId PRId64 40#define VADDR_PRIu PRIu64 41#define VADDR_PRIo PRIo64 42#define VADDR_PRIx PRIx64 43#define VADDR_PRIX PRIX64 44#define VADDR_MAX UINT64_MAX 45 46/** 47 * SECTION:cpu 48 * @section_id: QEMU-cpu 49 * @title: CPU Class 50 * @short_description: Base class for all CPUs 51 */ 52 53#define TYPE_CPU "cpu" 54 55/* Since this macro is used a lot in hot code paths and in conjunction with 56 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using 57 * an unchecked cast. 58 */ 59#define CPU(obj) ((CPUState *)(obj)) 60 61#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) 62#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) 63 64typedef enum MMUAccessType { 65 MMU_DATA_LOAD = 0, 66 MMU_DATA_STORE = 1, 67 MMU_INST_FETCH = 2 68} MMUAccessType; 69 70typedef struct CPUWatchpoint CPUWatchpoint; 71 72typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, 73 bool is_write, bool is_exec, int opaque, 74 unsigned size); 75 76struct TranslationBlock; 77 78/** 79 * CPUClass: 80 * @class_by_name: Callback to map -cpu command line model name to an 81 * instantiatable CPU type. 82 * @parse_features: Callback to parse command line arguments. 83 * @reset: Callback to reset the #CPUState to its initial state. 84 * @reset_dump_flags: #CPUDumpFlags to use for reset logging. 85 * @has_work: Callback for checking if there is work to do. 86 * @do_interrupt: Callback for interrupt handling. 87 * @do_unassigned_access: Callback for unassigned access handling. 88 * (this is deprecated: new targets should use do_transaction_failed instead) 89 * @do_unaligned_access: Callback for unaligned access handling, if 90 * the target defines #ALIGNED_ONLY. 91 * @do_transaction_failed: Callback for handling failed memory transactions 92 * (ie bus faults or external aborts; not MMU faults) 93 * @virtio_is_big_endian: Callback to return %true if a CPU which supports 94 * runtime configurable endianness is currently big-endian. Non-configurable 95 * CPUs can use the default implementation of this method. This method should 96 * not be used by any callers other than the pre-1.0 virtio devices. 97 * @memory_rw_debug: Callback for GDB memory access. 98 * @dump_state: Callback for dumping state. 99 * @dump_statistics: Callback for dumping statistics. 100 * @get_arch_id: Callback for getting architecture-dependent CPU ID. 101 * @get_paging_enabled: Callback for inquiring whether paging is enabled. 102 * @get_memory_mapping: Callback for obtaining the memory mappings. 103 * @set_pc: Callback for setting the Program Counter register. 104 * @synchronize_from_tb: Callback for synchronizing state from a TCG 105 * #TranslationBlock. 106 * @handle_mmu_fault: Callback for handling an MMU fault. 107 * @get_phys_page_debug: Callback for obtaining a physical address. 108 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the 109 * associated memory transaction attributes to use for the access. 110 * CPUs which use memory transaction attributes should implement this 111 * instead of get_phys_page_debug. 112 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for 113 * a memory access with the specified memory transaction attributes. 114 * @gdb_read_register: Callback for letting GDB read a register. 115 * @gdb_write_register: Callback for letting GDB write a register. 116 * @debug_check_watchpoint: Callback: return true if the architectural 117 * watchpoint whose address has matched should really fire. 118 * @debug_excp_handler: Callback for handling debug exceptions. 119 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a 120 * 64-bit VM coredump. 121 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF 122 * note to a 32-bit VM coredump. 123 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a 124 * 32-bit VM coredump. 125 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF 126 * note to a 32-bit VM coredump. 127 * @vmsd: State description for migration. 128 * @gdb_num_core_regs: Number of core registers accessible to GDB. 129 * @gdb_core_xml_file: File name for core registers GDB XML description. 130 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop 131 * before the insn which triggers a watchpoint rather than after it. 132 * @gdb_arch_name: Optional callback that returns the architecture name known 133 * to GDB. The caller must free the returned string with g_free. 134 * @cpu_exec_enter: Callback for cpu_exec preparation. 135 * @cpu_exec_exit: Callback for cpu_exec cleanup. 136 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. 137 * @disas_set_info: Setup architecture specific components of disassembly info 138 * @adjust_watchpoint_address: Perform a target-specific adjustment to an 139 * address before attempting to match it against watchpoints. 140 * 141 * Represents a CPU family or model. 142 */ 143typedef struct CPUClass { 144 /*< private >*/ 145 DeviceClass parent_class; 146 /*< public >*/ 147 148 ObjectClass *(*class_by_name)(const char *cpu_model); 149 void (*parse_features)(const char *typename, char *str, Error **errp); 150 151 void (*reset)(CPUState *cpu); 152 int reset_dump_flags; 153 bool (*has_work)(CPUState *cpu); 154 void (*do_interrupt)(CPUState *cpu); 155 CPUUnassignedAccess do_unassigned_access; 156 void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 157 MMUAccessType access_type, 158 int mmu_idx, uintptr_t retaddr); 159 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 160 unsigned size, MMUAccessType access_type, 161 int mmu_idx, MemTxAttrs attrs, 162 MemTxResult response, uintptr_t retaddr); 163 bool (*virtio_is_big_endian)(CPUState *cpu); 164 int (*memory_rw_debug)(CPUState *cpu, vaddr addr, 165 uint8_t *buf, int len, bool is_write); 166 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 167 int flags); 168 GuestPanicInformation* (*get_crash_info)(CPUState *cpu); 169 void (*dump_statistics)(CPUState *cpu, FILE *f, 170 fprintf_function cpu_fprintf, int flags); 171 int64_t (*get_arch_id)(CPUState *cpu); 172 bool (*get_paging_enabled)(const CPUState *cpu); 173 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, 174 Error **errp); 175 void (*set_pc)(CPUState *cpu, vaddr value); 176 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); 177 int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, 178 int mmu_index); 179 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); 180 hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, 181 MemTxAttrs *attrs); 182 int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); 183 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); 184 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); 185 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 186 void (*debug_excp_handler)(CPUState *cpu); 187 188 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, 189 int cpuid, void *opaque); 190 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, 191 void *opaque); 192 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, 193 int cpuid, void *opaque); 194 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, 195 void *opaque); 196 197 const struct VMStateDescription *vmsd; 198 const char *gdb_core_xml_file; 199 gchar * (*gdb_arch_name)(CPUState *cpu); 200 201 void (*cpu_exec_enter)(CPUState *cpu); 202 void (*cpu_exec_exit)(CPUState *cpu); 203 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 204 205 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); 206 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 207 void (*tcg_initialize)(void); 208 209 /* Keep non-pointer data at the end to minimize holes. */ 210 int gdb_num_core_regs; 211 bool gdb_stop_before_watchpoint; 212} CPUClass; 213 214#ifdef HOST_WORDS_BIGENDIAN 215typedef struct icount_decr_u16 { 216 uint16_t high; 217 uint16_t low; 218} icount_decr_u16; 219#else 220typedef struct icount_decr_u16 { 221 uint16_t low; 222 uint16_t high; 223} icount_decr_u16; 224#endif 225 226typedef struct CPUBreakpoint { 227 vaddr pc; 228 int flags; /* BP_* */ 229 QTAILQ_ENTRY(CPUBreakpoint) entry; 230} CPUBreakpoint; 231 232struct CPUWatchpoint { 233 vaddr vaddr; 234 vaddr len; 235 vaddr hitaddr; 236 MemTxAttrs hitattrs; 237 int flags; /* BP_* */ 238 QTAILQ_ENTRY(CPUWatchpoint) entry; 239}; 240 241struct KVMState; 242struct kvm_run; 243 244struct hax_vcpu_state; 245 246#define TB_JMP_CACHE_BITS 12 247#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) 248 249/* work queue */ 250 251/* The union type allows passing of 64 bit target pointers on 32 bit 252 * hosts in a single parameter 253 */ 254typedef union { 255 int host_int; 256 unsigned long host_ulong; 257 void *host_ptr; 258 vaddr target_ptr; 259} run_on_cpu_data; 260 261#define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) 262#define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) 263#define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) 264#define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) 265#define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) 266 267typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); 268 269struct qemu_work_item; 270 271#define CPU_UNSET_NUMA_NODE_ID -1 272#define CPU_TRACE_DSTATE_MAX_EVENTS 32 273 274/** 275 * CPUState: 276 * @cpu_index: CPU index (informative). 277 * @nr_cores: Number of cores within this CPU package. 278 * @nr_threads: Number of threads within this CPU. 279 * @running: #true if CPU is currently running (lockless). 280 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; 281 * valid under cpu_list_lock. 282 * @created: Indicates whether the CPU thread has been successfully created. 283 * @interrupt_request: Indicates a pending interrupt request. 284 * @halted: Nonzero if the CPU is in suspended state. 285 * @stop: Indicates a pending stop request. 286 * @stopped: Indicates the CPU has been artificially stopped. 287 * @unplug: Indicates a pending CPU unplug request. 288 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU 289 * @singlestep_enabled: Flags for single-stepping. 290 * @icount_extra: Instructions until next timer event. 291 * @icount_decr: Low 16 bits: number of cycles left, only used in icount mode. 292 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for this 293 * CPU and return to its top level loop (even in non-icount mode). 294 * This allows a single read-compare-cbranch-write sequence to test 295 * for both decrementer underflow and exceptions. 296 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution 297 * requires that IO only be performed on the last instruction of a TB 298 * so that interrupts take effect immediately. 299 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the 300 * AddressSpaces this CPU has) 301 * @num_ases: number of CPUAddressSpaces in @cpu_ases 302 * @as: Pointer to the first AddressSpace, for the convenience of targets which 303 * only have a single AddressSpace 304 * @env_ptr: Pointer to subclass-specific CPUArchState field. 305 * @gdb_regs: Additional GDB registers. 306 * @gdb_num_regs: Number of total registers accessible to GDB. 307 * @gdb_num_g_regs: Number of registers in GDB 'g' packets. 308 * @next_cpu: Next CPU sharing TB cache. 309 * @opaque: User data. 310 * @mem_io_pc: Host Program Counter at which the memory was accessed. 311 * @mem_io_vaddr: Target virtual address at which the memory was accessed. 312 * @kvm_fd: vCPU file descriptor for KVM. 313 * @work_mutex: Lock to prevent multiple access to queued_work_*. 314 * @queued_work_first: First asynchronous work pending. 315 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes 316 * to @trace_dstate). 317 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). 318 * @ignore_memory_transaction_failures: Cached copy of the MachineState 319 * flag of the same name: allows the board to suppress calling of the 320 * CPU do_transaction_failed hook function. 321 * 322 * State of one CPU core or thread. 323 */ 324struct CPUState { 325 /*< private >*/ 326 DeviceState parent_obj; 327 /*< public >*/ 328 329 int nr_cores; 330 int nr_threads; 331 332 struct QemuThread *thread; 333#ifdef _WIN32 334 HANDLE hThread; 335#endif 336 int thread_id; 337 bool running, has_waiter; 338 struct QemuCond *halt_cond; 339 bool thread_kicked; 340 bool created; 341 bool stop; 342 bool stopped; 343 bool unplug; 344 bool crash_occurred; 345 bool exit_request; 346 uint32_t cflags_next_tb; 347 /* updates protected by BQL */ 348 uint32_t interrupt_request; 349 int singlestep_enabled; 350 int64_t icount_budget; 351 int64_t icount_extra; 352 sigjmp_buf jmp_env; 353 354 QemuMutex work_mutex; 355 struct qemu_work_item *queued_work_first, *queued_work_last; 356 357 CPUAddressSpace *cpu_ases; 358 int num_ases; 359 AddressSpace *as; 360 MemoryRegion *memory; 361 362 void *env_ptr; /* CPUArchState */ 363 364 /* Accessed in parallel; all accesses must be atomic */ 365 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; 366 367 struct GDBRegisterState *gdb_regs; 368 int gdb_num_regs; 369 int gdb_num_g_regs; 370 QTAILQ_ENTRY(CPUState) node; 371 372 /* ice debug support */ 373 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; 374 375 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; 376 CPUWatchpoint *watchpoint_hit; 377 378 void *opaque; 379 380 /* In order to avoid passing too many arguments to the MMIO helpers, 381 * we store some rarely used information in the CPU context. 382 */ 383 uintptr_t mem_io_pc; 384 vaddr mem_io_vaddr; 385 386 int kvm_fd; 387 struct KVMState *kvm_state; 388 struct kvm_run *kvm_run; 389 390 /* Used for events with 'vcpu' and *without* the 'disabled' properties */ 391 DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); 392 DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); 393 394 /* TODO Move common fields from CPUArchState here. */ 395 int cpu_index; 396 uint32_t halted; 397 uint32_t can_do_io; 398 int32_t exception_index; 399 400 /* shared by kvm, hax and hvf */ 401 bool vcpu_dirty; 402 403 /* Used to keep track of an outstanding cpu throttle thread for migration 404 * autoconverge 405 */ 406 bool throttle_thread_scheduled; 407 408 bool ignore_memory_transaction_failures; 409 410 /* Note that this is accessed at the start of every TB via a negative 411 offset from AREG0. Leave this field at the end so as to make the 412 (absolute value) offset as small as possible. This reduces code 413 size, especially for hosts without large memory offsets. */ 414 union { 415 uint32_t u32; 416 icount_decr_u16 u16; 417 } icount_decr; 418 419 struct hax_vcpu_state *hax_vcpu; 420 421 /* The pending_tlb_flush flag is set and cleared atomically to 422 * avoid potential races. The aim of the flag is to avoid 423 * unnecessary flushes. 424 */ 425 uint16_t pending_tlb_flush; 426}; 427 428QTAILQ_HEAD(CPUTailQ, CPUState); 429extern struct CPUTailQ cpus; 430#define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) 431#define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) 432#define CPU_FOREACH_SAFE(cpu, next_cpu) \ 433 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) 434#define CPU_FOREACH_REVERSE(cpu) \ 435 QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node) 436#define first_cpu QTAILQ_FIRST(&cpus) 437 438extern __thread CPUState *current_cpu; 439 440static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) 441{ 442 unsigned int i; 443 444 for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { 445 atomic_set(&cpu->tb_jmp_cache[i], NULL); 446 } 447} 448 449/** 450 * qemu_tcg_mttcg_enabled: 451 * Check whether we are running MultiThread TCG or not. 452 * 453 * Returns: %true if we are in MTTCG mode %false otherwise. 454 */ 455extern bool mttcg_enabled; 456#define qemu_tcg_mttcg_enabled() (mttcg_enabled) 457 458/** 459 * cpu_paging_enabled: 460 * @cpu: The CPU whose state is to be inspected. 461 * 462 * Returns: %true if paging is enabled, %false otherwise. 463 */ 464bool cpu_paging_enabled(const CPUState *cpu); 465 466/** 467 * cpu_get_memory_mapping: 468 * @cpu: The CPU whose memory mappings are to be obtained. 469 * @list: Where to write the memory mappings to. 470 * @errp: Pointer for reporting an #Error. 471 */ 472void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 473 Error **errp); 474 475/** 476 * cpu_write_elf64_note: 477 * @f: pointer to a function that writes memory to a file 478 * @cpu: The CPU whose memory is to be dumped 479 * @cpuid: ID number of the CPU 480 * @opaque: pointer to the CPUState struct 481 */ 482int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 483 int cpuid, void *opaque); 484 485/** 486 * cpu_write_elf64_qemunote: 487 * @f: pointer to a function that writes memory to a file 488 * @cpu: The CPU whose memory is to be dumped 489 * @cpuid: ID number of the CPU 490 * @opaque: pointer to the CPUState struct 491 */ 492int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 493 void *opaque); 494 495/** 496 * cpu_write_elf32_note: 497 * @f: pointer to a function that writes memory to a file 498 * @cpu: The CPU whose memory is to be dumped 499 * @cpuid: ID number of the CPU 500 * @opaque: pointer to the CPUState struct 501 */ 502int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 503 int cpuid, void *opaque); 504 505/** 506 * cpu_write_elf32_qemunote: 507 * @f: pointer to a function that writes memory to a file 508 * @cpu: The CPU whose memory is to be dumped 509 * @cpuid: ID number of the CPU 510 * @opaque: pointer to the CPUState struct 511 */ 512int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 513 void *opaque); 514 515/** 516 * cpu_get_crash_info: 517 * @cpu: The CPU to get crash information for 518 * 519 * Gets the previously saved crash information. 520 * Caller is responsible for freeing the data. 521 */ 522GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); 523 524/** 525 * CPUDumpFlags: 526 * @CPU_DUMP_CODE: 527 * @CPU_DUMP_FPU: dump FPU register state, not just integer 528 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state 529 */ 530enum CPUDumpFlags { 531 CPU_DUMP_CODE = 0x00010000, 532 CPU_DUMP_FPU = 0x00020000, 533 CPU_DUMP_CCOP = 0x00040000, 534}; 535 536/** 537 * cpu_dump_state: 538 * @cpu: The CPU whose state is to be dumped. 539 * @f: File to dump to. 540 * @cpu_fprintf: Function to dump with. 541 * @flags: Flags what to dump. 542 * 543 * Dumps CPU state. 544 */ 545void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 546 int flags); 547 548/** 549 * cpu_dump_statistics: 550 * @cpu: The CPU whose state is to be dumped. 551 * @f: File to dump to. 552 * @cpu_fprintf: Function to dump with. 553 * @flags: Flags what to dump. 554 * 555 * Dumps CPU statistics. 556 */ 557void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 558 int flags); 559 560#ifndef CONFIG_USER_ONLY 561/** 562 * cpu_get_phys_page_attrs_debug: 563 * @cpu: The CPU to obtain the physical page address for. 564 * @addr: The virtual address. 565 * @attrs: Updated on return with the memory transaction attributes to use 566 * for this access. 567 * 568 * Obtains the physical page corresponding to a virtual one, together 569 * with the corresponding memory transaction attributes to use for the access. 570 * Use it only for debugging because no protection checks are done. 571 * 572 * Returns: Corresponding physical page address or -1 if no page found. 573 */ 574static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 575 MemTxAttrs *attrs) 576{ 577 CPUClass *cc = CPU_GET_CLASS(cpu); 578 579 if (cc->get_phys_page_attrs_debug) { 580 return cc->get_phys_page_attrs_debug(cpu, addr, attrs); 581 } 582 /* Fallback for CPUs which don't implement the _attrs_ hook */ 583 *attrs = MEMTXATTRS_UNSPECIFIED; 584 return cc->get_phys_page_debug(cpu, addr); 585} 586 587/** 588 * cpu_get_phys_page_debug: 589 * @cpu: The CPU to obtain the physical page address for. 590 * @addr: The virtual address. 591 * 592 * Obtains the physical page corresponding to a virtual one. 593 * Use it only for debugging because no protection checks are done. 594 * 595 * Returns: Corresponding physical page address or -1 if no page found. 596 */ 597static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) 598{ 599 MemTxAttrs attrs = {}; 600 601 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); 602} 603 604/** cpu_asidx_from_attrs: 605 * @cpu: CPU 606 * @attrs: memory transaction attributes 607 * 608 * Returns the address space index specifying the CPU AddressSpace 609 * to use for a memory access with the given transaction attributes. 610 */ 611static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) 612{ 613 CPUClass *cc = CPU_GET_CLASS(cpu); 614 615 if (cc->asidx_from_attrs) { 616 return cc->asidx_from_attrs(cpu, attrs); 617 } 618 return 0; 619} 620#endif 621 622/** 623 * cpu_list_add: 624 * @cpu: The CPU to be added to the list of CPUs. 625 */ 626void cpu_list_add(CPUState *cpu); 627 628/** 629 * cpu_list_remove: 630 * @cpu: The CPU to be removed from the list of CPUs. 631 */ 632void cpu_list_remove(CPUState *cpu); 633 634/** 635 * cpu_reset: 636 * @cpu: The CPU whose state is to be reset. 637 */ 638void cpu_reset(CPUState *cpu); 639 640/** 641 * cpu_class_by_name: 642 * @typename: The CPU base type. 643 * @cpu_model: The model string without any parameters. 644 * 645 * Looks up a CPU #ObjectClass matching name @cpu_model. 646 * 647 * Returns: A #CPUClass or %NULL if not matching class is found. 648 */ 649ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); 650 651/** 652 * cpu_create: 653 * @typename: The CPU type. 654 * 655 * Instantiates a CPU and realizes the CPU. 656 * 657 * Returns: A #CPUState or %NULL if an error occurred. 658 */ 659CPUState *cpu_create(const char *typename); 660 661/** 662 * cpu_parse_cpu_model: 663 * @typename: The CPU base type or CPU type. 664 * @cpu_model: The model string including optional parameters. 665 * 666 * processes optional parameters and registers them as global properties 667 * 668 * Returns: type of CPU to create or prints error and terminates process 669 * if an error occurred. 670 */ 671const char *cpu_parse_cpu_model(const char *typename, const char *cpu_model); 672 673/** 674 * cpu_generic_init: 675 * @typename: The CPU base type. 676 * @cpu_model: The model string including optional parameters. 677 * 678 * Instantiates a CPU, processes optional parameters and realizes the CPU. 679 * 680 * Returns: A #CPUState or %NULL if an error occurred. 681 */ 682CPUState *cpu_generic_init(const char *typename, const char *cpu_model); 683 684/** 685 * cpu_has_work: 686 * @cpu: The vCPU to check. 687 * 688 * Checks whether the CPU has work to do. 689 * 690 * Returns: %true if the CPU has work, %false otherwise. 691 */ 692static inline bool cpu_has_work(CPUState *cpu) 693{ 694 CPUClass *cc = CPU_GET_CLASS(cpu); 695 696 g_assert(cc->has_work); 697 return cc->has_work(cpu); 698} 699 700/** 701 * qemu_cpu_is_self: 702 * @cpu: The vCPU to check against. 703 * 704 * Checks whether the caller is executing on the vCPU thread. 705 * 706 * Returns: %true if called from @cpu's thread, %false otherwise. 707 */ 708bool qemu_cpu_is_self(CPUState *cpu); 709 710/** 711 * qemu_cpu_kick: 712 * @cpu: The vCPU to kick. 713 * 714 * Kicks @cpu's thread. 715 */ 716void qemu_cpu_kick(CPUState *cpu); 717 718/** 719 * cpu_is_stopped: 720 * @cpu: The CPU to check. 721 * 722 * Checks whether the CPU is stopped. 723 * 724 * Returns: %true if run state is not running or if artificially stopped; 725 * %false otherwise. 726 */ 727bool cpu_is_stopped(CPUState *cpu); 728 729/** 730 * do_run_on_cpu: 731 * @cpu: The vCPU to run on. 732 * @func: The function to be executed. 733 * @data: Data to pass to the function. 734 * @mutex: Mutex to release while waiting for @func to run. 735 * 736 * Used internally in the implementation of run_on_cpu. 737 */ 738void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, 739 QemuMutex *mutex); 740 741/** 742 * run_on_cpu: 743 * @cpu: The vCPU to run on. 744 * @func: The function to be executed. 745 * @data: Data to pass to the function. 746 * 747 * Schedules the function @func for execution on the vCPU @cpu. 748 */ 749void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 750 751/** 752 * async_run_on_cpu: 753 * @cpu: The vCPU to run on. 754 * @func: The function to be executed. 755 * @data: Data to pass to the function. 756 * 757 * Schedules the function @func for execution on the vCPU @cpu asynchronously. 758 */ 759void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 760 761/** 762 * async_safe_run_on_cpu: 763 * @cpu: The vCPU to run on. 764 * @func: The function to be executed. 765 * @data: Data to pass to the function. 766 * 767 * Schedules the function @func for execution on the vCPU @cpu asynchronously, 768 * while all other vCPUs are sleeping. 769 * 770 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the 771 * BQL. 772 */ 773void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 774 775/** 776 * qemu_get_cpu: 777 * @index: The CPUState@cpu_index value of the CPU to obtain. 778 * 779 * Gets a CPU matching @index. 780 * 781 * Returns: The CPU or %NULL if there is no matching CPU. 782 */ 783CPUState *qemu_get_cpu(int index); 784 785/** 786 * cpu_exists: 787 * @id: Guest-exposed CPU ID to lookup. 788 * 789 * Search for CPU with specified ID. 790 * 791 * Returns: %true - CPU is found, %false - CPU isn't found. 792 */ 793bool cpu_exists(int64_t id); 794 795/** 796 * cpu_by_arch_id: 797 * @id: Guest-exposed CPU ID of the CPU to obtain. 798 * 799 * Get a CPU with matching @id. 800 * 801 * Returns: The CPU or %NULL if there is no matching CPU. 802 */ 803CPUState *cpu_by_arch_id(int64_t id); 804 805/** 806 * cpu_throttle_set: 807 * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99. 808 * 809 * Throttles all vcpus by forcing them to sleep for the given percentage of 810 * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly. 811 * (example: 10ms sleep for every 30ms awake). 812 * 813 * cpu_throttle_set can be called as needed to adjust new_throttle_pct. 814 * Once the throttling starts, it will remain in effect until cpu_throttle_stop 815 * is called. 816 */ 817void cpu_throttle_set(int new_throttle_pct); 818 819/** 820 * cpu_throttle_stop: 821 * 822 * Stops the vcpu throttling started by cpu_throttle_set. 823 */ 824void cpu_throttle_stop(void); 825 826/** 827 * cpu_throttle_active: 828 * 829 * Returns: %true if the vcpus are currently being throttled, %false otherwise. 830 */ 831bool cpu_throttle_active(void); 832 833/** 834 * cpu_throttle_get_percentage: 835 * 836 * Returns the vcpu throttle percentage. See cpu_throttle_set for details. 837 * 838 * Returns: The throttle percentage in range 1 to 99. 839 */ 840int cpu_throttle_get_percentage(void); 841 842#ifndef CONFIG_USER_ONLY 843 844typedef void (*CPUInterruptHandler)(CPUState *, int); 845 846extern CPUInterruptHandler cpu_interrupt_handler; 847 848/** 849 * cpu_interrupt: 850 * @cpu: The CPU to set an interrupt on. 851 * @mask: The interupts to set. 852 * 853 * Invokes the interrupt handler. 854 */ 855static inline void cpu_interrupt(CPUState *cpu, int mask) 856{ 857 cpu_interrupt_handler(cpu, mask); 858} 859 860#else /* USER_ONLY */ 861 862void cpu_interrupt(CPUState *cpu, int mask); 863 864#endif /* USER_ONLY */ 865 866#ifdef NEED_CPU_H 867 868#ifdef CONFIG_SOFTMMU 869static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, 870 bool is_write, bool is_exec, 871 int opaque, unsigned size) 872{ 873 CPUClass *cc = CPU_GET_CLASS(cpu); 874 875 if (cc->do_unassigned_access) { 876 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); 877 } 878} 879 880static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, 881 MMUAccessType access_type, 882 int mmu_idx, uintptr_t retaddr) 883{ 884 CPUClass *cc = CPU_GET_CLASS(cpu); 885 886 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); 887} 888 889static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, 890 vaddr addr, unsigned size, 891 MMUAccessType access_type, 892 int mmu_idx, MemTxAttrs attrs, 893 MemTxResult response, 894 uintptr_t retaddr) 895{ 896 CPUClass *cc = CPU_GET_CLASS(cpu); 897 898 if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { 899 cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, 900 mmu_idx, attrs, response, retaddr); 901 } 902} 903#endif 904 905#endif /* NEED_CPU_H */ 906 907/** 908 * cpu_set_pc: 909 * @cpu: The CPU to set the program counter for. 910 * @addr: Program counter value. 911 * 912 * Sets the program counter for a CPU. 913 */ 914static inline void cpu_set_pc(CPUState *cpu, vaddr addr) 915{ 916 CPUClass *cc = CPU_GET_CLASS(cpu); 917 918 cc->set_pc(cpu, addr); 919} 920 921/** 922 * cpu_reset_interrupt: 923 * @cpu: The CPU to clear the interrupt on. 924 * @mask: The interrupt mask to clear. 925 * 926 * Resets interrupts on the vCPU @cpu. 927 */ 928void cpu_reset_interrupt(CPUState *cpu, int mask); 929 930/** 931 * cpu_exit: 932 * @cpu: The CPU to exit. 933 * 934 * Requests the CPU @cpu to exit execution. 935 */ 936void cpu_exit(CPUState *cpu); 937 938/** 939 * cpu_resume: 940 * @cpu: The CPU to resume. 941 * 942 * Resumes CPU, i.e. puts CPU into runnable state. 943 */ 944void cpu_resume(CPUState *cpu); 945 946/** 947 * cpu_remove: 948 * @cpu: The CPU to remove. 949 * 950 * Requests the CPU to be removed. 951 */ 952void cpu_remove(CPUState *cpu); 953 954 /** 955 * cpu_remove_sync: 956 * @cpu: The CPU to remove. 957 * 958 * Requests the CPU to be removed and waits till it is removed. 959 */ 960void cpu_remove_sync(CPUState *cpu); 961 962/** 963 * process_queued_cpu_work() - process all items on CPU work queue 964 * @cpu: The CPU which work queue to process. 965 */ 966void process_queued_cpu_work(CPUState *cpu); 967 968/** 969 * cpu_exec_start: 970 * @cpu: The CPU for the current thread. 971 * 972 * Record that a CPU has started execution and can be interrupted with 973 * cpu_exit. 974 */ 975void cpu_exec_start(CPUState *cpu); 976 977/** 978 * cpu_exec_end: 979 * @cpu: The CPU for the current thread. 980 * 981 * Record that a CPU has stopped execution and exclusive sections 982 * can be executed without interrupting it. 983 */ 984void cpu_exec_end(CPUState *cpu); 985 986/** 987 * start_exclusive: 988 * 989 * Wait for a concurrent exclusive section to end, and then start 990 * a section of work that is run while other CPUs are not running 991 * between cpu_exec_start and cpu_exec_end. CPUs that are running 992 * cpu_exec are exited immediately. CPUs that call cpu_exec_start 993 * during the exclusive section go to sleep until this CPU calls 994 * end_exclusive. 995 */ 996void start_exclusive(void); 997 998/** 999 * end_exclusive: 1000 *
1001 * Concludes an exclusive execution section started by start_exclusive. 1002 */ 1003void end_exclusive(void); 1004 1005/** 1006 * qemu_init_vcpu: 1007 * @cpu: The vCPU to initialize. 1008 * 1009 * Initializes a vCPU. 1010 */ 1011void qemu_init_vcpu(CPUState *cpu); 1012 1013#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ 1014#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ 1015#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ 1016 1017/** 1018 * cpu_single_step: 1019 * @cpu: CPU to the flags for. 1020 * @enabled: Flags to enable. 1021 * 1022 * Enables or disables single-stepping for @cpu. 1023 */ 1024void cpu_single_step(CPUState *cpu, int enabled); 1025 1026/* Breakpoint/watchpoint flags */ 1027#define BP_MEM_READ 0x01 1028#define BP_MEM_WRITE 0x02 1029#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) 1030#define BP_STOP_BEFORE_ACCESS 0x04 1031/* 0x08 currently unused */ 1032#define BP_GDB 0x10 1033#define BP_CPU 0x20 1034#define BP_ANY (BP_GDB | BP_CPU) 1035#define BP_WATCHPOINT_HIT_READ 0x40 1036#define BP_WATCHPOINT_HIT_WRITE 0x80 1037#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) 1038 1039int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, 1040 CPUBreakpoint **breakpoint); 1041int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); 1042void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); 1043void cpu_breakpoint_remove_all(CPUState *cpu, int mask); 1044 1045/* Return true if PC matches an installed breakpoint. */ 1046static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) 1047{ 1048 CPUBreakpoint *bp; 1049 1050 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { 1051 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 1052 if (bp->pc == pc && (bp->flags & mask)) { 1053 return true; 1054 } 1055 } 1056 } 1057 return false; 1058} 1059 1060int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 1061 int flags, CPUWatchpoint **watchpoint); 1062int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, 1063 vaddr len, int flags); 1064void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); 1065void cpu_watchpoint_remove_all(CPUState *cpu, int mask); 1066 1067/** 1068 * cpu_get_address_space: 1069 * @cpu: CPU to get address space from 1070 * @asidx: index identifying which address space to get 1071 * 1072 * Return the requested address space of this CPU. @asidx 1073 * specifies which address space to read. 1074 */ 1075AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); 1076 1077void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) 1078 GCC_FMT_ATTR(2, 3); 1079extern Property cpu_common_props[]; 1080void cpu_exec_initfn(CPUState *cpu); 1081void cpu_exec_realizefn(CPUState *cpu, Error **errp); 1082void cpu_exec_unrealizefn(CPUState *cpu); 1083 1084#ifdef NEED_CPU_H 1085 1086#ifdef CONFIG_SOFTMMU 1087extern const struct VMStateDescription vmstate_cpu_common; 1088#else 1089#define vmstate_cpu_common vmstate_dummy 1090#endif 1091 1092#define VMSTATE_CPU() { \ 1093 .name = "parent_obj", \ 1094 .size = sizeof(CPUState), \ 1095 .vmsd = &vmstate_cpu_common, \ 1096 .flags = VMS_STRUCT, \ 1097 .offset = 0, \ 1098} 1099 1100#endif /* NEED_CPU_H */ 1101 1102#define UNASSIGNED_CPU_INDEX -1 1103 1104#endif 1105