1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#ifndef TARGET_ARM_INTERNALS_H
26#define TARGET_ARM_INTERNALS_H
27
28#include "hw/registerfields.h"
29
30
31#define BANK_USRSYS 0
32#define BANK_SVC 1
33#define BANK_ABT 2
34#define BANK_UND 3
35#define BANK_IRQ 4
36#define BANK_FIQ 5
37#define BANK_HYP 6
38#define BANK_MON 7
39
40static inline bool excp_is_internal(int excp)
41{
42
43
44
45 return excp == EXCP_INTERRUPT
46 || excp == EXCP_HLT
47 || excp == EXCP_DEBUG
48 || excp == EXCP_HALTED
49 || excp == EXCP_EXCEPTION_EXIT
50 || excp == EXCP_KERNEL_TRAP
51 || excp == EXCP_SEMIHOST;
52}
53
54
55
56
57#define GTIMER_SCALE 16
58
59
60FIELD(V7M_CONTROL, NPRIV, 0, 1)
61FIELD(V7M_CONTROL, SPSEL, 1, 1)
62FIELD(V7M_CONTROL, FPCA, 2, 1)
63FIELD(V7M_CONTROL, SFPA, 3, 1)
64
65
66FIELD(V7M_EXCRET, ES, 0, 1)
67FIELD(V7M_EXCRET, RES0, 1, 1)
68FIELD(V7M_EXCRET, SPSEL, 2, 1)
69FIELD(V7M_EXCRET, MODE, 3, 1)
70FIELD(V7M_EXCRET, FTYPE, 4, 1)
71FIELD(V7M_EXCRET, DCRS, 5, 1)
72FIELD(V7M_EXCRET, S, 6, 1)
73FIELD(V7M_EXCRET, RES1, 7, 25)
74
75
76#define EXC_RETURN_MIN_MAGIC 0xff000000
77
78
79
80#define FNC_RETURN_MIN_MAGIC 0xfefffffe
81
82
83
84
85
86
87
88
89
90
91
92
93
94#define M_FAKE_FSR_NSC_EXEC 0xf
95#define M_FAKE_FSR_SFAULT 0xe
96
97
98
99
100
101
102
103static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
104{
105 static const unsigned int map[4] = {
106 [1] = BANK_SVC,
107 [2] = BANK_HYP,
108 [3] = BANK_MON,
109 };
110 assert(el >= 1 && el <= 3);
111 return map[el];
112}
113
114
115static inline int bank_number(int mode)
116{
117 switch (mode) {
118 case ARM_CPU_MODE_USR:
119 case ARM_CPU_MODE_SYS:
120 return BANK_USRSYS;
121 case ARM_CPU_MODE_SVC:
122 return BANK_SVC;
123 case ARM_CPU_MODE_ABT:
124 return BANK_ABT;
125 case ARM_CPU_MODE_UND:
126 return BANK_UND;
127 case ARM_CPU_MODE_IRQ:
128 return BANK_IRQ;
129 case ARM_CPU_MODE_FIQ:
130 return BANK_FIQ;
131 case ARM_CPU_MODE_HYP:
132 return BANK_HYP;
133 case ARM_CPU_MODE_MON:
134 return BANK_MON;
135 }
136 g_assert_not_reached();
137}
138
139void switch_mode(CPUARMState *, int);
140void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
141void arm_translate_init(void);
142
143enum arm_fprounding {
144 FPROUNDING_TIEEVEN,
145 FPROUNDING_POSINF,
146 FPROUNDING_NEGINF,
147 FPROUNDING_ZERO,
148 FPROUNDING_TIEAWAY,
149 FPROUNDING_ODD
150};
151
152int arm_rmode_to_sf(int rmode);
153
154static inline void aarch64_save_sp(CPUARMState *env, int el)
155{
156 if (env->pstate & PSTATE_SP) {
157 env->sp_el[el] = env->xregs[31];
158 } else {
159 env->sp_el[0] = env->xregs[31];
160 }
161}
162
163static inline void aarch64_restore_sp(CPUARMState *env, int el)
164{
165 if (env->pstate & PSTATE_SP) {
166 env->xregs[31] = env->sp_el[el];
167 } else {
168 env->xregs[31] = env->sp_el[0];
169 }
170}
171
172static inline void update_spsel(CPUARMState *env, uint32_t imm)
173{
174 unsigned int cur_el = arm_current_el(env);
175
176
177
178 if (!((imm ^ env->pstate) & PSTATE_SP)) {
179 return;
180 }
181 aarch64_save_sp(env, cur_el);
182 env->pstate = deposit32(env->pstate, 0, 1, imm);
183
184
185
186
187 assert(cur_el >= 1 && cur_el <= 3);
188 aarch64_restore_sp(env, cur_el);
189}
190
191
192
193
194
195
196
197
198static inline unsigned int arm_pamax(ARMCPU *cpu)
199{
200 static const unsigned int pamax_map[] = {
201 [0] = 32,
202 [1] = 36,
203 [2] = 40,
204 [3] = 42,
205 [4] = 44,
206 [5] = 48,
207 };
208 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
209
210
211
212 assert(parange < ARRAY_SIZE(pamax_map));
213 return pamax_map[parange];
214}
215
216
217
218
219
220static inline bool extended_addresses_enabled(CPUARMState *env)
221{
222 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
223 return arm_el_is_aa64(env, 1) ||
224 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
225}
226
227
228enum arm_exception_class {
229 EC_UNCATEGORIZED = 0x00,
230 EC_WFX_TRAP = 0x01,
231 EC_CP15RTTRAP = 0x03,
232 EC_CP15RRTTRAP = 0x04,
233 EC_CP14RTTRAP = 0x05,
234 EC_CP14DTTRAP = 0x06,
235 EC_ADVSIMDFPACCESSTRAP = 0x07,
236 EC_FPIDTRAP = 0x08,
237 EC_CP14RRTTRAP = 0x0c,
238 EC_ILLEGALSTATE = 0x0e,
239 EC_AA32_SVC = 0x11,
240 EC_AA32_HVC = 0x12,
241 EC_AA32_SMC = 0x13,
242 EC_AA64_SVC = 0x15,
243 EC_AA64_HVC = 0x16,
244 EC_AA64_SMC = 0x17,
245 EC_SYSTEMREGISTERTRAP = 0x18,
246 EC_INSNABORT = 0x20,
247 EC_INSNABORT_SAME_EL = 0x21,
248 EC_PCALIGNMENT = 0x22,
249 EC_DATAABORT = 0x24,
250 EC_DATAABORT_SAME_EL = 0x25,
251 EC_SPALIGNMENT = 0x26,
252 EC_AA32_FPTRAP = 0x28,
253 EC_AA64_FPTRAP = 0x2c,
254 EC_SERROR = 0x2f,
255 EC_BREAKPOINT = 0x30,
256 EC_BREAKPOINT_SAME_EL = 0x31,
257 EC_SOFTWARESTEP = 0x32,
258 EC_SOFTWARESTEP_SAME_EL = 0x33,
259 EC_WATCHPOINT = 0x34,
260 EC_WATCHPOINT_SAME_EL = 0x35,
261 EC_AA32_BKPT = 0x38,
262 EC_VECTORCATCH = 0x3a,
263 EC_AA64_BKPT = 0x3c,
264};
265
266#define ARM_EL_EC_SHIFT 26
267#define ARM_EL_IL_SHIFT 25
268#define ARM_EL_ISV_SHIFT 24
269#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
270#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
271
272
273
274
275
276
277
278
279
280
281static inline uint32_t syn_uncategorized(void)
282{
283 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
284}
285
286static inline uint32_t syn_aa64_svc(uint32_t imm16)
287{
288 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
289}
290
291static inline uint32_t syn_aa64_hvc(uint32_t imm16)
292{
293 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
294}
295
296static inline uint32_t syn_aa64_smc(uint32_t imm16)
297{
298 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
299}
300
301static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
302{
303 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
304 | (is_16bit ? 0 : ARM_EL_IL);
305}
306
307static inline uint32_t syn_aa32_hvc(uint32_t imm16)
308{
309 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
310}
311
312static inline uint32_t syn_aa32_smc(void)
313{
314 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
315}
316
317static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
318{
319 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
320}
321
322static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
323{
324 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
325 | (is_16bit ? 0 : ARM_EL_IL);
326}
327
328static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
329 int crn, int crm, int rt,
330 int isread)
331{
332 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
333 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
334 | (crm << 1) | isread;
335}
336
337static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
338 int crn, int crm, int rt, int isread,
339 bool is_16bit)
340{
341 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
342 | (is_16bit ? 0 : ARM_EL_IL)
343 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
344 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
345}
346
347static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
348 int crn, int crm, int rt, int isread,
349 bool is_16bit)
350{
351 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
352 | (is_16bit ? 0 : ARM_EL_IL)
353 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
354 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
355}
356
357static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
358 int rt, int rt2, int isread,
359 bool is_16bit)
360{
361 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
362 | (is_16bit ? 0 : ARM_EL_IL)
363 | (cv << 24) | (cond << 20) | (opc1 << 16)
364 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
365}
366
367static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
368 int rt, int rt2, int isread,
369 bool is_16bit)
370{
371 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
372 | (is_16bit ? 0 : ARM_EL_IL)
373 | (cv << 24) | (cond << 20) | (opc1 << 16)
374 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
375}
376
377static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
378{
379 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
380 | (is_16bit ? 0 : ARM_EL_IL)
381 | (cv << 24) | (cond << 20);
382}
383
384static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
385{
386 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
387 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
388}
389
390static inline uint32_t syn_data_abort_no_iss(int same_el,
391 int ea, int cm, int s1ptw,
392 int wnr, int fsc)
393{
394 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
395 | ARM_EL_IL
396 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
397}
398
399static inline uint32_t syn_data_abort_with_iss(int same_el,
400 int sas, int sse, int srt,
401 int sf, int ar,
402 int ea, int cm, int s1ptw,
403 int wnr, int fsc,
404 bool is_16bit)
405{
406 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
407 | (is_16bit ? 0 : ARM_EL_IL)
408 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
409 | (sf << 15) | (ar << 14)
410 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
411}
412
413static inline uint32_t syn_swstep(int same_el, int isv, int ex)
414{
415 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
416 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
417}
418
419static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
420{
421 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
422 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
423}
424
425static inline uint32_t syn_breakpoint(int same_el)
426{
427 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
428 | ARM_EL_IL | 0x22;
429}
430
431static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
432{
433 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
434 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
435 (cv << 24) | (cond << 20) | ti;
436}
437
438
439
440
441void hw_watchpoint_update(ARMCPU *cpu, int n);
442
443
444
445
446void hw_watchpoint_update_all(ARMCPU *cpu);
447
448
449
450void hw_breakpoint_update(ARMCPU *cpu, int n);
451
452
453
454
455void hw_breakpoint_update_all(ARMCPU *cpu);
456
457
458bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
459
460
461
462
463vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
464
465
466void arm_debug_excp_handler(CPUState *cs);
467
468#ifdef CONFIG_USER_ONLY
469static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
470{
471 return false;
472}
473#else
474
475bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
476
477void arm_handle_psci_call(ARMCPU *cpu);
478#endif
479
480
481
482
483
484
485static inline void arm_clear_exclusive(CPUARMState *env)
486{
487 env->exclusive_addr = -1;
488}
489
490
491
492
493
494
495
496
497typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
498struct ARMMMUFaultInfo {
499 target_ulong s2addr;
500 bool stage2;
501 bool s1ptw;
502 bool ea;
503};
504
505
506bool arm_tlb_fill(CPUState *cpu, vaddr address,
507 MMUAccessType access_type, int mmu_idx,
508 uint32_t *fsr, ARMMMUFaultInfo *fi);
509
510
511
512bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
513
514
515void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
516 MMUAccessType access_type,
517 int mmu_idx, uintptr_t retaddr);
518
519
520
521
522
523void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
524 vaddr addr, unsigned size,
525 MMUAccessType access_type,
526 int mmu_idx, MemTxAttrs attrs,
527 MemTxResult response, uintptr_t retaddr);
528
529
530static inline void arm_call_el_change_hook(ARMCPU *cpu)
531{
532 if (cpu->el_change_hook) {
533 cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
534 }
535}
536
537
538static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
539{
540 switch (mmu_idx) {
541 case ARMMMUIdx_S12NSE0:
542 case ARMMMUIdx_S12NSE1:
543 case ARMMMUIdx_S1NSE0:
544 case ARMMMUIdx_S1NSE1:
545 case ARMMMUIdx_S1E2:
546 case ARMMMUIdx_S2NS:
547 case ARMMMUIdx_MPriv:
548 case ARMMMUIdx_MNegPri:
549 case ARMMMUIdx_MUser:
550 return false;
551 case ARMMMUIdx_S1E3:
552 case ARMMMUIdx_S1SE0:
553 case ARMMMUIdx_S1SE1:
554 case ARMMMUIdx_MSPriv:
555 case ARMMMUIdx_MSNegPri:
556 case ARMMMUIdx_MSUser:
557 return true;
558 default:
559 g_assert_not_reached();
560 }
561}
562
563#endif
564