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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "qemu-common.h"
25#include "exec/exec-all.h"
26
27
28static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
29{
30 LM32CPU *cpu = LM32_CPU(cs);
31
32 cpu->env.pc = value;
33}
34
35
36static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
37{
38 ObjectClass *class_a = (ObjectClass *)a;
39 ObjectClass *class_b = (ObjectClass *)b;
40 const char *name_a, *name_b;
41
42 name_a = object_class_get_name(class_a);
43 name_b = object_class_get_name(class_b);
44 return strcmp(name_a, name_b);
45}
46
47static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
48{
49 ObjectClass *oc = data;
50 CPUListState *s = user_data;
51 const char *typename = object_class_get_name(oc);
52 char *name;
53
54 name = g_strndup(typename, strlen(typename) - strlen(LM32_CPU_TYPE_SUFFIX));
55 (*s->cpu_fprintf)(s->file, " %s\n", name);
56 g_free(name);
57}
58
59
60void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
61{
62 CPUListState s = {
63 .file = f,
64 .cpu_fprintf = cpu_fprintf,
65 };
66 GSList *list;
67
68 list = object_class_get_list(TYPE_LM32_CPU, false);
69 list = g_slist_sort(list, lm32_cpu_list_compare);
70 (*cpu_fprintf)(f, "Available CPUs:\n");
71 g_slist_foreach(list, lm32_cpu_list_entry, &s);
72 g_slist_free(list);
73}
74
75static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
76{
77 CPULM32State *env = &cpu->env;
78 uint32_t cfg = 0;
79
80 if (cpu->features & LM32_FEATURE_MULTIPLY) {
81 cfg |= CFG_M;
82 }
83
84 if (cpu->features & LM32_FEATURE_DIVIDE) {
85 cfg |= CFG_D;
86 }
87
88 if (cpu->features & LM32_FEATURE_SHIFT) {
89 cfg |= CFG_S;
90 }
91
92 if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
93 cfg |= CFG_X;
94 }
95
96 if (cpu->features & LM32_FEATURE_I_CACHE) {
97 cfg |= CFG_IC;
98 }
99
100 if (cpu->features & LM32_FEATURE_D_CACHE) {
101 cfg |= CFG_DC;
102 }
103
104 if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
105 cfg |= CFG_CC;
106 }
107
108 cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
109 cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
110 cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
111 cfg |= (cpu->revision << CFG_REV_SHIFT);
112
113 env->cfg = cfg;
114}
115
116static bool lm32_cpu_has_work(CPUState *cs)
117{
118 return cs->interrupt_request & CPU_INTERRUPT_HARD;
119}
120
121
122static void lm32_cpu_reset(CPUState *s)
123{
124 LM32CPU *cpu = LM32_CPU(s);
125 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
126 CPULM32State *env = &cpu->env;
127
128 lcc->parent_reset(s);
129
130
131 memset(env, 0, offsetof(CPULM32State, end_reset_fields));
132
133 lm32_cpu_init_cfg_reg(cpu);
134}
135
136static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
137{
138 info->mach = bfd_mach_lm32;
139 info->print_insn = print_insn_lm32;
140}
141
142static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
143{
144 CPUState *cs = CPU(dev);
145 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
146 Error *local_err = NULL;
147
148 cpu_exec_realizefn(cs, &local_err);
149 if (local_err != NULL) {
150 error_propagate(errp, local_err);
151 return;
152 }
153
154 cpu_reset(cs);
155
156 qemu_init_vcpu(cs);
157
158 lcc->parent_realize(dev, errp);
159}
160
161static void lm32_cpu_initfn(Object *obj)
162{
163 CPUState *cs = CPU(obj);
164 LM32CPU *cpu = LM32_CPU(obj);
165 CPULM32State *env = &cpu->env;
166
167 cs->env_ptr = env;
168
169 env->flags = 0;
170}
171
172static void lm32_basic_cpu_initfn(Object *obj)
173{
174 LM32CPU *cpu = LM32_CPU(obj);
175
176 cpu->revision = 3;
177 cpu->num_interrupts = 32;
178 cpu->num_breakpoints = 4;
179 cpu->num_watchpoints = 4;
180 cpu->features = LM32_FEATURE_SHIFT
181 | LM32_FEATURE_SIGN_EXTEND
182 | LM32_FEATURE_CYCLE_COUNT;
183}
184
185static void lm32_standard_cpu_initfn(Object *obj)
186{
187 LM32CPU *cpu = LM32_CPU(obj);
188
189 cpu->revision = 3;
190 cpu->num_interrupts = 32;
191 cpu->num_breakpoints = 4;
192 cpu->num_watchpoints = 4;
193 cpu->features = LM32_FEATURE_MULTIPLY
194 | LM32_FEATURE_DIVIDE
195 | LM32_FEATURE_SHIFT
196 | LM32_FEATURE_SIGN_EXTEND
197 | LM32_FEATURE_I_CACHE
198 | LM32_FEATURE_CYCLE_COUNT;
199}
200
201static void lm32_full_cpu_initfn(Object *obj)
202{
203 LM32CPU *cpu = LM32_CPU(obj);
204
205 cpu->revision = 3;
206 cpu->num_interrupts = 32;
207 cpu->num_breakpoints = 4;
208 cpu->num_watchpoints = 4;
209 cpu->features = LM32_FEATURE_MULTIPLY
210 | LM32_FEATURE_DIVIDE
211 | LM32_FEATURE_SHIFT
212 | LM32_FEATURE_SIGN_EXTEND
213 | LM32_FEATURE_I_CACHE
214 | LM32_FEATURE_D_CACHE
215 | LM32_FEATURE_CYCLE_COUNT;
216}
217
218static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
219{
220 ObjectClass *oc;
221 char *typename;
222
223 typename = g_strdup_printf(LM32_CPU_TYPE_NAME("%s"), cpu_model);
224 oc = object_class_by_name(typename);
225 g_free(typename);
226 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
227 object_class_is_abstract(oc))) {
228 oc = NULL;
229 }
230 return oc;
231}
232
233static void lm32_cpu_class_init(ObjectClass *oc, void *data)
234{
235 LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
236 CPUClass *cc = CPU_CLASS(oc);
237 DeviceClass *dc = DEVICE_CLASS(oc);
238
239 lcc->parent_realize = dc->realize;
240 dc->realize = lm32_cpu_realizefn;
241
242 lcc->parent_reset = cc->reset;
243 cc->reset = lm32_cpu_reset;
244
245 cc->class_by_name = lm32_cpu_class_by_name;
246 cc->has_work = lm32_cpu_has_work;
247 cc->do_interrupt = lm32_cpu_do_interrupt;
248 cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
249 cc->dump_state = lm32_cpu_dump_state;
250 cc->set_pc = lm32_cpu_set_pc;
251 cc->gdb_read_register = lm32_cpu_gdb_read_register;
252 cc->gdb_write_register = lm32_cpu_gdb_write_register;
253#ifdef CONFIG_USER_ONLY
254 cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
255#else
256 cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
257 cc->vmsd = &vmstate_lm32_cpu;
258#endif
259 cc->gdb_num_core_regs = 32 + 7;
260 cc->gdb_stop_before_watchpoint = true;
261 cc->debug_excp_handler = lm32_debug_excp_handler;
262 cc->disas_set_info = lm32_cpu_disas_set_info;
263 cc->tcg_initialize = lm32_translate_init;
264}
265
266#define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
267 { \
268 .parent = TYPE_LM32_CPU, \
269 .name = LM32_CPU_TYPE_NAME(cpu_model), \
270 .instance_init = initfn, \
271 }
272
273static const TypeInfo lm32_cpus_type_infos[] = {
274 {
275 .name = TYPE_LM32_CPU,
276 .parent = TYPE_CPU,
277 .instance_size = sizeof(LM32CPU),
278 .instance_init = lm32_cpu_initfn,
279 .abstract = true,
280 .class_size = sizeof(LM32CPUClass),
281 .class_init = lm32_cpu_class_init,
282 },
283 DEFINE_LM32_CPU_TYPE("lm32-basic", lm32_basic_cpu_initfn),
284 DEFINE_LM32_CPU_TYPE("lm32-standard", lm32_standard_cpu_initfn),
285 DEFINE_LM32_CPU_TYPE("lm32-full", lm32_full_cpu_initfn),
286};
287
288DEFINE_TYPES(lm32_cpus_type_infos)
289
