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23#ifndef S390X_CPU_H
24#define S390X_CPU_H
25
26#include "qemu-common.h"
27#include "cpu-qom.h"
28#include "cpu_models.h"
29
30#define TARGET_LONG_BITS 64
31
32#define ELF_MACHINE_UNAME "S390X"
33
34#define CPUArchState struct CPUS390XState
35
36#include "exec/cpu-defs.h"
37#define TARGET_PAGE_BITS 12
38
39#define TARGET_PHYS_ADDR_SPACE_BITS 64
40#define TARGET_VIRT_ADDR_SPACE_BITS 64
41
42#include "exec/cpu-all.h"
43
44#include "fpu/softfloat.h"
45
46#define NB_MMU_MODES 4
47#define TARGET_INSN_START_EXTRA_WORDS 1
48
49#define MMU_MODE0_SUFFIX _primary
50#define MMU_MODE1_SUFFIX _secondary
51#define MMU_MODE2_SUFFIX _home
52#define MMU_MODE3_SUFFIX _real
53
54#define MMU_USER_IDX 0
55
56#define MAX_IO_QUEUE 16
57#define MAX_MCHK_QUEUE 16
58
59#define PSW_MCHK_MASK 0x0004000000000000
60#define PSW_IO_MASK 0x0200000000000000
61
62#define S390_MAX_CPUS 248
63
64typedef struct PSW {
65 uint64_t mask;
66 uint64_t addr;
67} PSW;
68
69typedef struct IOIntQueue {
70 uint16_t id;
71 uint16_t nr;
72 uint32_t parm;
73 uint32_t word;
74} IOIntQueue;
75
76typedef struct MchkQueue {
77 uint16_t type;
78} MchkQueue;
79
80struct CPUS390XState {
81 uint64_t regs[16];
82
83
84
85
86 CPU_DoubleU vregs[32][2];
87 uint32_t aregs[16];
88 uint8_t riccb[64];
89 uint64_t gscb[4];
90
91
92 struct {} start_initial_reset_fields;
93
94 uint32_t fpc;
95 uint32_t cc_op;
96 bool bpbc;
97
98 float_status fpu_status;
99
100
101 uint64_t retxl;
102
103 PSW psw;
104
105 uint64_t cc_src;
106 uint64_t cc_dst;
107 uint64_t cc_vr;
108
109 uint64_t ex_value;
110
111 uint64_t __excp_addr;
112 uint64_t psa;
113
114 uint32_t int_pgm_code;
115 uint32_t int_pgm_ilen;
116
117 uint32_t int_svc_code;
118 uint32_t int_svc_ilen;
119
120 uint64_t per_address;
121 uint16_t per_perc_atmid;
122
123 uint64_t cregs[16];
124
125 IOIntQueue io_queue[MAX_IO_QUEUE][8];
126 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
127
128 int pending_int;
129 uint32_t service_param;
130 uint16_t external_call_addr;
131 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
132 int io_index[8];
133 int mchk_index;
134
135 uint64_t ckc;
136 uint64_t cputm;
137 uint32_t todpr;
138
139 uint64_t pfault_token;
140 uint64_t pfault_compare;
141 uint64_t pfault_select;
142
143 uint64_t gbea;
144 uint64_t pp;
145
146
147 struct {} end_reset_fields;
148
149 CPU_COMMON
150
151#if !defined(CONFIG_USER_ONLY)
152 uint32_t core_id;
153 uint64_t cpuid;
154#endif
155
156 uint64_t tod_offset;
157 uint64_t tod_basetime;
158 QEMUTimer *tod_timer;
159
160 QEMUTimer *cpu_timer;
161
162
163
164
165
166
167
168#define CPU_STATE_UNINITIALIZED 0x00
169#define CPU_STATE_STOPPED 0x01
170#define CPU_STATE_CHECK_STOP 0x02
171#define CPU_STATE_OPERATING 0x03
172#define CPU_STATE_LOAD 0x04
173 uint8_t cpu_state;
174
175
176 uint8_t sigp_order;
177
178};
179
180static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
181{
182 return &cs->vregs[nr][0];
183}
184
185
186
187
188
189
190
191struct S390CPU {
192
193 CPUState parent_obj;
194
195
196 CPUS390XState env;
197 S390CPUModel *model;
198
199 void *irqstate;
200 uint32_t irqstate_saved_size;
201};
202
203static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
204{
205 return container_of(env, S390CPU, env);
206}
207
208#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
209
210#define ENV_OFFSET offsetof(S390CPU, env)
211
212#ifndef CONFIG_USER_ONLY
213extern const struct VMStateDescription vmstate_s390_cpu;
214#endif
215
216
217#define HIGH_ORDER_BIT 0x80000000
218
219
220
221#define PGM_OPERATION 0x0001
222#define PGM_PRIVILEGED 0x0002
223#define PGM_EXECUTE 0x0003
224#define PGM_PROTECTION 0x0004
225#define PGM_ADDRESSING 0x0005
226#define PGM_SPECIFICATION 0x0006
227#define PGM_DATA 0x0007
228#define PGM_FIXPT_OVERFLOW 0x0008
229#define PGM_FIXPT_DIVIDE 0x0009
230#define PGM_DEC_OVERFLOW 0x000a
231#define PGM_DEC_DIVIDE 0x000b
232#define PGM_HFP_EXP_OVERFLOW 0x000c
233#define PGM_HFP_EXP_UNDERFLOW 0x000d
234#define PGM_HFP_SIGNIFICANCE 0x000e
235#define PGM_HFP_DIVIDE 0x000f
236#define PGM_SEGMENT_TRANS 0x0010
237#define PGM_PAGE_TRANS 0x0011
238#define PGM_TRANS_SPEC 0x0012
239#define PGM_SPECIAL_OP 0x0013
240#define PGM_OPERAND 0x0015
241#define PGM_TRACE_TABLE 0x0016
242#define PGM_SPACE_SWITCH 0x001c
243#define PGM_HFP_SQRT 0x001d
244#define PGM_PC_TRANS_SPEC 0x001f
245#define PGM_AFX_TRANS 0x0020
246#define PGM_ASX_TRANS 0x0021
247#define PGM_LX_TRANS 0x0022
248#define PGM_EX_TRANS 0x0023
249#define PGM_PRIM_AUTH 0x0024
250#define PGM_SEC_AUTH 0x0025
251#define PGM_ALET_SPEC 0x0028
252#define PGM_ALEN_SPEC 0x0029
253#define PGM_ALE_SEQ 0x002a
254#define PGM_ASTE_VALID 0x002b
255#define PGM_ASTE_SEQ 0x002c
256#define PGM_EXT_AUTH 0x002d
257#define PGM_STACK_FULL 0x0030
258#define PGM_STACK_EMPTY 0x0031
259#define PGM_STACK_SPEC 0x0032
260#define PGM_STACK_TYPE 0x0033
261#define PGM_STACK_OP 0x0034
262#define PGM_ASCE_TYPE 0x0038
263#define PGM_REG_FIRST_TRANS 0x0039
264#define PGM_REG_SEC_TRANS 0x003a
265#define PGM_REG_THIRD_TRANS 0x003b
266#define PGM_MONITOR 0x0040
267#define PGM_PER 0x0080
268#define PGM_CRYPTO 0x0119
269
270
271#define EXT_INTERRUPT_KEY 0x0040
272#define EXT_CLOCK_COMP 0x1004
273#define EXT_CPU_TIMER 0x1005
274#define EXT_MALFUNCTION 0x1200
275#define EXT_EMERGENCY 0x1201
276#define EXT_EXTERNAL_CALL 0x1202
277#define EXT_ETR 0x1406
278#define EXT_SERVICE 0x2401
279#define EXT_VIRTIO 0x2603
280
281
282#undef PSW_MASK_PER
283#undef PSW_MASK_DAT
284#undef PSW_MASK_IO
285#undef PSW_MASK_EXT
286#undef PSW_MASK_KEY
287#undef PSW_SHIFT_KEY
288#undef PSW_MASK_MCHECK
289#undef PSW_MASK_WAIT
290#undef PSW_MASK_PSTATE
291#undef PSW_MASK_ASC
292#undef PSW_SHIFT_ASC
293#undef PSW_MASK_CC
294#undef PSW_MASK_PM
295#undef PSW_SHIFT_MASK_PM
296#undef PSW_MASK_64
297#undef PSW_MASK_32
298#undef PSW_MASK_ESA_ADDR
299
300#define PSW_MASK_PER 0x4000000000000000ULL
301#define PSW_MASK_DAT 0x0400000000000000ULL
302#define PSW_MASK_IO 0x0200000000000000ULL
303#define PSW_MASK_EXT 0x0100000000000000ULL
304#define PSW_MASK_KEY 0x00F0000000000000ULL
305#define PSW_SHIFT_KEY 52
306#define PSW_MASK_MCHECK 0x0004000000000000ULL
307#define PSW_MASK_WAIT 0x0002000000000000ULL
308#define PSW_MASK_PSTATE 0x0001000000000000ULL
309#define PSW_MASK_ASC 0x0000C00000000000ULL
310#define PSW_SHIFT_ASC 46
311#define PSW_MASK_CC 0x0000300000000000ULL
312#define PSW_MASK_PM 0x00000F0000000000ULL
313#define PSW_SHIFT_MASK_PM 40
314#define PSW_MASK_64 0x0000000100000000ULL
315#define PSW_MASK_32 0x0000000080000000ULL
316#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
317
318#undef PSW_ASC_PRIMARY
319#undef PSW_ASC_ACCREG
320#undef PSW_ASC_SECONDARY
321#undef PSW_ASC_HOME
322
323#define PSW_ASC_PRIMARY 0x0000000000000000ULL
324#define PSW_ASC_ACCREG 0x0000400000000000ULL
325#define PSW_ASC_SECONDARY 0x0000800000000000ULL
326#define PSW_ASC_HOME 0x0000C00000000000ULL
327
328
329#define AS_PRIMARY 0
330#define AS_ACCREG 1
331#define AS_SECONDARY 2
332#define AS_HOME 3
333
334
335
336#define FLAG_MASK_PSW_SHIFT 31
337#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
338#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
339#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
340#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
341#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
342#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
343 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
344
345
346#define CR0_LOWPROT 0x0000000010000000ULL
347#define CR0_SECONDARY 0x0000000004000000ULL
348#define CR0_EDAT 0x0000000000800000ULL
349#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
350#define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
351#define CR0_CKC_SC 0x0000000000000800ULL
352#define CR0_CPU_TIMER_SC 0x0000000000000400ULL
353#define CR0_SERVICE_SC 0x0000000000000200ULL
354
355
356#define MMU_PRIMARY_IDX 0
357#define MMU_SECONDARY_IDX 1
358#define MMU_HOME_IDX 2
359#define MMU_REAL_IDX 3
360
361static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
362{
363 switch (env->psw.mask & PSW_MASK_ASC) {
364 case PSW_ASC_PRIMARY:
365 return MMU_PRIMARY_IDX;
366 case PSW_ASC_SECONDARY:
367 return MMU_SECONDARY_IDX;
368 case PSW_ASC_HOME:
369 return MMU_HOME_IDX;
370 case PSW_ASC_ACCREG:
371
372 default:
373 abort();
374 }
375}
376
377static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
378 target_ulong *cs_base, uint32_t *flags)
379{
380 *pc = env->psw.addr;
381 *cs_base = env->ex_value;
382 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
383}
384
385
386#define PER_CR9_EVENT_BRANCH 0x80000000
387#define PER_CR9_EVENT_IFETCH 0x40000000
388#define PER_CR9_EVENT_STORE 0x20000000
389#define PER_CR9_EVENT_STORE_REAL 0x08000000
390#define PER_CR9_EVENT_NULLIFICATION 0x01000000
391#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
392#define PER_CR9_CONTROL_ALTERATION 0x00200000
393
394
395#define PER_CODE_EVENT_BRANCH 0x8000
396#define PER_CODE_EVENT_IFETCH 0x4000
397#define PER_CODE_EVENT_STORE 0x2000
398#define PER_CODE_EVENT_STORE_REAL 0x0800
399#define PER_CODE_EVENT_NULLIFICATION 0x0100
400
401#define EXCP_EXT 1
402#define EXCP_SVC 2
403#define EXCP_PGM 3
404#define EXCP_RESTART 4
405#define EXCP_STOP 5
406#define EXCP_IO 7
407#define EXCP_MCHK 8
408
409#define INTERRUPT_IO (1 << 0)
410#define INTERRUPT_MCHK (1 << 1)
411#define INTERRUPT_EXT_SERVICE (1 << 2)
412#define INTERRUPT_EXT_CPU_TIMER (1 << 3)
413#define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
414#define INTERRUPT_EXTERNAL_CALL (1 << 5)
415#define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
416#define INTERRUPT_RESTART (1 << 7)
417#define INTERRUPT_STOP (1 << 8)
418
419
420#define S390_PSWM_REGNUM 0
421#define S390_PSWA_REGNUM 1
422
423#define S390_R0_REGNUM 2
424#define S390_R1_REGNUM 3
425#define S390_R2_REGNUM 4
426#define S390_R3_REGNUM 5
427#define S390_R4_REGNUM 6
428#define S390_R5_REGNUM 7
429#define S390_R6_REGNUM 8
430#define S390_R7_REGNUM 9
431#define S390_R8_REGNUM 10
432#define S390_R9_REGNUM 11
433#define S390_R10_REGNUM 12
434#define S390_R11_REGNUM 13
435#define S390_R12_REGNUM 14
436#define S390_R13_REGNUM 15
437#define S390_R14_REGNUM 16
438#define S390_R15_REGNUM 17
439
440#define S390_NUM_CORE_REGS 18
441
442static inline void setcc(S390CPU *cpu, uint64_t cc)
443{
444 CPUS390XState *env = &cpu->env;
445
446 env->psw.mask &= ~(3ull << 44);
447 env->psw.mask |= (cc & 3) << 44;
448 env->cc_op = cc;
449}
450
451
452#define STSI_LEVEL_MASK 0x00000000f0000000ULL
453#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
454#define STSI_LEVEL_1 0x0000000010000000ULL
455#define STSI_LEVEL_2 0x0000000020000000ULL
456#define STSI_LEVEL_3 0x0000000030000000ULL
457#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
458#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
459#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
460#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
461
462
463struct sysib_111 {
464 uint32_t res1[8];
465 uint8_t manuf[16];
466 uint8_t type[4];
467 uint8_t res2[12];
468 uint8_t model[16];
469 uint8_t sequence[16];
470 uint8_t plant[4];
471 uint8_t res3[156];
472};
473
474
475struct sysib_121 {
476 uint32_t res1[80];
477 uint8_t sequence[16];
478 uint8_t plant[4];
479 uint8_t res2[2];
480 uint16_t cpu_addr;
481 uint8_t res3[152];
482};
483
484
485struct sysib_122 {
486 uint8_t res1[32];
487 uint32_t capability;
488 uint16_t total_cpus;
489 uint16_t active_cpus;
490 uint16_t standby_cpus;
491 uint16_t reserved_cpus;
492 uint16_t adjustments[2026];
493};
494
495
496struct sysib_221 {
497 uint32_t res1[80];
498 uint8_t sequence[16];
499 uint8_t plant[4];
500 uint16_t cpu_id;
501 uint16_t cpu_addr;
502 uint8_t res3[152];
503};
504
505
506struct sysib_222 {
507 uint32_t res1[32];
508 uint16_t lpar_num;
509 uint8_t res2;
510 uint8_t lcpuc;
511 uint16_t total_cpus;
512 uint16_t conf_cpus;
513 uint16_t standby_cpus;
514 uint16_t reserved_cpus;
515 uint8_t name[8];
516 uint32_t caf;
517 uint8_t res3[16];
518 uint16_t dedicated_cpus;
519 uint16_t shared_cpus;
520 uint8_t res4[180];
521};
522
523
524struct sysib_322 {
525 uint8_t res1[31];
526 uint8_t count;
527 struct {
528 uint8_t res2[4];
529 uint16_t total_cpus;
530 uint16_t conf_cpus;
531 uint16_t standby_cpus;
532 uint16_t reserved_cpus;
533 uint8_t name[8];
534 uint32_t caf;
535 uint8_t cpi[16];
536 uint8_t res5[3];
537 uint8_t ext_name_encoding;
538 uint32_t res3;
539 uint8_t uuid[16];
540 } vm[8];
541 uint8_t res4[1504];
542 uint8_t ext_names[8][256];
543};
544
545
546#define _ASCE_ORIGIN ~0xfffULL
547#define _ASCE_SUBSPACE 0x200
548#define _ASCE_PRIVATE_SPACE 0x100
549#define _ASCE_ALT_EVENT 0x80
550#define _ASCE_SPACE_SWITCH 0x40
551#define _ASCE_REAL_SPACE 0x20
552#define _ASCE_TYPE_MASK 0x0c
553#define _ASCE_TYPE_REGION1 0x0c
554#define _ASCE_TYPE_REGION2 0x08
555#define _ASCE_TYPE_REGION3 0x04
556#define _ASCE_TYPE_SEGMENT 0x00
557#define _ASCE_TABLE_LENGTH 0x03
558
559#define _REGION_ENTRY_ORIGIN ~0xfffULL
560#define _REGION_ENTRY_RO 0x200
561#define _REGION_ENTRY_TF 0xc0
562#define _REGION_ENTRY_INV 0x20
563#define _REGION_ENTRY_TYPE_MASK 0x0c
564#define _REGION_ENTRY_TYPE_R1 0x0c
565#define _REGION_ENTRY_TYPE_R2 0x08
566#define _REGION_ENTRY_TYPE_R3 0x04
567#define _REGION_ENTRY_LENGTH 0x03
568
569#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL
570#define _SEGMENT_ENTRY_FC 0x400
571#define _SEGMENT_ENTRY_RO 0x200
572#define _SEGMENT_ENTRY_INV 0x20
573
574#define VADDR_PX 0xff000
575
576#define _PAGE_RO 0x200
577#define _PAGE_INVALID 0x400
578#define _PAGE_RES0 0x800
579
580#define SK_C (0x1 << 1)
581#define SK_R (0x1 << 2)
582#define SK_F (0x1 << 3)
583#define SK_ACC_MASK (0xf << 4)
584
585
586#define SIGP_SENSE 0x01
587#define SIGP_EXTERNAL_CALL 0x02
588#define SIGP_EMERGENCY 0x03
589#define SIGP_START 0x04
590#define SIGP_STOP 0x05
591#define SIGP_RESTART 0x06
592#define SIGP_STOP_STORE_STATUS 0x09
593#define SIGP_INITIAL_CPU_RESET 0x0b
594#define SIGP_CPU_RESET 0x0c
595#define SIGP_SET_PREFIX 0x0d
596#define SIGP_STORE_STATUS_ADDR 0x0e
597#define SIGP_SET_ARCH 0x12
598#define SIGP_COND_EMERGENCY 0x13
599#define SIGP_SENSE_RUNNING 0x15
600#define SIGP_STORE_ADTL_STATUS 0x17
601
602
603#define SIGP_CC_ORDER_CODE_ACCEPTED 0
604#define SIGP_CC_STATUS_STORED 1
605#define SIGP_CC_BUSY 2
606#define SIGP_CC_NOT_OPERATIONAL 3
607
608
609#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
610#define SIGP_STAT_NOT_RUNNING 0x00000400UL
611#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
612#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
613#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
614#define SIGP_STAT_STOPPED 0x00000040UL
615#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
616#define SIGP_STAT_CHECK_STOP 0x00000010UL
617#define SIGP_STAT_INOPERATIVE 0x00000004UL
618#define SIGP_STAT_INVALID_ORDER 0x00000002UL
619#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
620
621
622#define SIGP_MODE_ESA_S390 0
623#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
624#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
625
626
627#define SIGP_ORDER_MASK 0x000000ff
628
629
630#define MEM_SECTION_SIZE 0x10000000UL
631#define MAX_AVAIL_SLOTS 32
632
633
634
635
636#define MCIC_SC_SD 0x8000000000000000ULL
637#define MCIC_SC_PD 0x4000000000000000ULL
638#define MCIC_SC_SR 0x2000000000000000ULL
639#define MCIC_SC_CD 0x0800000000000000ULL
640#define MCIC_SC_ED 0x0400000000000000ULL
641#define MCIC_SC_DG 0x0100000000000000ULL
642#define MCIC_SC_W 0x0080000000000000ULL
643#define MCIC_SC_CP 0x0040000000000000ULL
644#define MCIC_SC_SP 0x0020000000000000ULL
645#define MCIC_SC_CK 0x0010000000000000ULL
646
647
648#define MCIC_SCM_B 0x0002000000000000ULL
649#define MCIC_SCM_DA 0x0000000020000000ULL
650#define MCIC_SCM_AP 0x0000000000080000ULL
651
652
653#define MCIC_SE_SE 0x0000800000000000ULL
654#define MCIC_SE_SC 0x0000400000000000ULL
655#define MCIC_SE_KE 0x0000200000000000ULL
656#define MCIC_SE_DS 0x0000100000000000ULL
657#define MCIC_SE_IE 0x0000000080000000ULL
658
659
660#define MCIC_VB_WP 0x0000080000000000ULL
661#define MCIC_VB_MS 0x0000040000000000ULL
662#define MCIC_VB_PM 0x0000020000000000ULL
663#define MCIC_VB_IA 0x0000010000000000ULL
664#define MCIC_VB_FA 0x0000008000000000ULL
665#define MCIC_VB_VR 0x0000004000000000ULL
666#define MCIC_VB_EC 0x0000002000000000ULL
667#define MCIC_VB_FP 0x0000001000000000ULL
668#define MCIC_VB_GR 0x0000000800000000ULL
669#define MCIC_VB_CR 0x0000000400000000ULL
670#define MCIC_VB_ST 0x0000000100000000ULL
671#define MCIC_VB_AR 0x0000000040000000ULL
672#define MCIC_VB_GS 0x0000000008000000ULL
673#define MCIC_VB_PR 0x0000000000200000ULL
674#define MCIC_VB_FC 0x0000000000100000ULL
675#define MCIC_VB_CT 0x0000000000020000ULL
676#define MCIC_VB_CC 0x0000000000010000ULL
677
678
679
680int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low);
681int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low);
682void s390_crypto_reset(void);
683bool s390_get_squash_mcss(void);
684int s390_get_memslot_count(void);
685int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
686void s390_cmma_reset(void);
687void s390_enable_css_support(S390CPU *cpu);
688int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
689 int vq, bool assign);
690#ifndef CONFIG_USER_ONLY
691unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
692#else
693static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
694{
695 return 0;
696}
697#endif
698
699
700
701void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
702#define cpu_list s390_cpu_list
703
704
705#define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)
706
707#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
708#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
709
710
711
712
713int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
714#define cpu_signal_handler cpu_s390x_signal_handler
715
716
717
718void s390_crw_mchk(void);
719void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
720 uint32_t io_int_parm, uint32_t io_int_word);
721
722#define ILEN_AUTO 0xff
723void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
724
725void s390_sclp_extint(uint32_t parm);
726
727
728
729int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
730 int len, bool is_write);
731#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
732 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
733#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
734 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
735#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
736 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
737
738
739
740int s390_cpu_restart(S390CPU *cpu);
741void s390_init_sigp(void);
742
743
744
745S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
746
747#endif
748