qemu/target/unicore32/helper.c
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   1/*
   2 * Copyright (C) 2010-2012 Guan Xuetao
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 *
   8 * Contributions from 2012-04-01 on are considered under GPL version 2,
   9 * or (at your option) any later version.
  10 */
  11
  12#include "qemu/osdep.h"
  13#include "cpu.h"
  14#include "exec/exec-all.h"
  15#include "exec/gdbstub.h"
  16#include "exec/helper-proto.h"
  17#include "qemu/host-utils.h"
  18#ifndef CONFIG_USER_ONLY
  19#include "ui/console.h"
  20#endif
  21
  22#undef DEBUG_UC32
  23
  24#ifdef DEBUG_UC32
  25#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
  26#else
  27#define DPRINTF(fmt, ...) do {} while (0)
  28#endif
  29
  30#ifndef CONFIG_USER_ONLY
  31void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
  32        uint32_t cop)
  33{
  34    UniCore32CPU *cpu = uc32_env_get_cpu(env);
  35
  36    /*
  37     * movc pp.nn, rn, #imm9
  38     *      rn: UCOP_REG_D
  39     *      nn: UCOP_REG_N
  40     *          1: sys control reg.
  41     *          2: page table base reg.
  42     *          3: data fault status reg.
  43     *          4: insn fault status reg.
  44     *          5: cache op. reg.
  45     *          6: tlb op. reg.
  46     *      imm9: split UCOP_IMM10 with bit5 is 0
  47     */
  48    switch (creg) {
  49    case 1:
  50        if (cop != 0) {
  51            goto unrecognized;
  52        }
  53        env->cp0.c1_sys = val;
  54        break;
  55    case 2:
  56        if (cop != 0) {
  57            goto unrecognized;
  58        }
  59        env->cp0.c2_base = val;
  60        break;
  61    case 3:
  62        if (cop != 0) {
  63            goto unrecognized;
  64        }
  65        env->cp0.c3_faultstatus = val;
  66        break;
  67    case 4:
  68        if (cop != 0) {
  69            goto unrecognized;
  70        }
  71        env->cp0.c4_faultaddr = val;
  72        break;
  73    case 5:
  74        switch (cop) {
  75        case 28:
  76            DPRINTF("Invalidate Entire I&D cache\n");
  77            return;
  78        case 20:
  79            DPRINTF("Invalidate Entire Icache\n");
  80            return;
  81        case 12:
  82            DPRINTF("Invalidate Entire Dcache\n");
  83            return;
  84        case 10:
  85            DPRINTF("Clean Entire Dcache\n");
  86            return;
  87        case 14:
  88            DPRINTF("Flush Entire Dcache\n");
  89            return;
  90        case 13:
  91            DPRINTF("Invalidate Dcache line\n");
  92            return;
  93        case 11:
  94            DPRINTF("Clean Dcache line\n");
  95            return;
  96        case 15:
  97            DPRINTF("Flush Dcache line\n");
  98            return;
  99        }
 100        break;
 101    case 6:
 102        if ((cop <= 6) && (cop >= 2)) {
 103            /* invalid all tlb */
 104            tlb_flush(CPU(cpu));
 105            return;
 106        }
 107        break;
 108    default:
 109        goto unrecognized;
 110    }
 111    return;
 112unrecognized:
 113    DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
 114            creg, cop);
 115}
 116
 117uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
 118{
 119    /*
 120     * movc rd, pp.nn, #imm9
 121     *      rd: UCOP_REG_D
 122     *      nn: UCOP_REG_N
 123     *          0: cpuid and cachetype
 124     *          1: sys control reg.
 125     *          2: page table base reg.
 126     *          3: data fault status reg.
 127     *          4: insn fault status reg.
 128     *      imm9: split UCOP_IMM10 with bit5 is 0
 129     */
 130    switch (creg) {
 131    case 0:
 132        switch (cop) {
 133        case 0:
 134            return env->cp0.c0_cpuid;
 135        case 1:
 136            return env->cp0.c0_cachetype;
 137        }
 138        break;
 139    case 1:
 140        if (cop == 0) {
 141            return env->cp0.c1_sys;
 142        }
 143        break;
 144    case 2:
 145        if (cop == 0) {
 146            return env->cp0.c2_base;
 147        }
 148        break;
 149    case 3:
 150        if (cop == 0) {
 151            return env->cp0.c3_faultstatus;
 152        }
 153        break;
 154    case 4:
 155        if (cop == 0) {
 156            return env->cp0.c4_faultaddr;
 157        }
 158        break;
 159    }
 160    DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
 161            creg, cop);
 162    return 0;
 163}
 164
 165#ifdef CONFIG_CURSES
 166
 167/* KEY_EVENT is defined in wincon.h and in curses.h. Avoid redefinition. */
 168#undef KEY_EVENT
 169#include <curses.h>
 170#undef KEY_EVENT
 171
 172/*
 173 * FIXME:
 174 *     1. curses windows will be blank when switching back
 175 *     2. backspace is not handled yet
 176 */
 177static void putc_on_screen(unsigned char ch)
 178{
 179    static WINDOW *localwin;
 180    static int init;
 181
 182    if (!init) {
 183        /* Assume 80 * 30 screen to minimize the implementation */
 184        localwin = newwin(30, 80, 0, 0);
 185        scrollok(localwin, TRUE);
 186        init = TRUE;
 187    }
 188
 189    if (isprint(ch)) {
 190        wprintw(localwin, "%c", ch);
 191    } else {
 192        switch (ch) {
 193        case '\n':
 194            wprintw(localwin, "%c", ch);
 195            break;
 196        case '\r':
 197            /* If '\r' is put before '\n', the curses window will destroy the
 198             * last print line. And meanwhile, '\n' implifies '\r' inside. */
 199            break;
 200        default: /* Not handled, so just print it hex code */
 201            wprintw(localwin, "-- 0x%x --", ch);
 202        }
 203    }
 204
 205    wrefresh(localwin);
 206}
 207#else
 208#define putc_on_screen(c)               do { } while (0)
 209#endif
 210
 211void helper_cp1_putc(target_ulong x)
 212{
 213    putc_on_screen((unsigned char)x);   /* Output to screen */
 214    DPRINTF("%c", x);                   /* Output to stdout */
 215}
 216#endif
 217
 218#ifdef CONFIG_USER_ONLY
 219void switch_mode(CPUUniCore32State *env, int mode)
 220{
 221    UniCore32CPU *cpu = uc32_env_get_cpu(env);
 222
 223    if (mode != ASR_MODE_USER) {
 224        cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
 225    }
 226}
 227
 228void uc32_cpu_do_interrupt(CPUState *cs)
 229{
 230    cpu_abort(cs, "NO interrupt in user mode\n");
 231}
 232
 233int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
 234                              int access_type, int mmu_idx)
 235{
 236    cpu_abort(cs, "NO mmu fault in user mode\n");
 237    return 1;
 238}
 239#endif
 240
 241bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 242{
 243    if (interrupt_request & CPU_INTERRUPT_HARD) {
 244        UniCore32CPU *cpu = UNICORE32_CPU(cs);
 245        CPUUniCore32State *env = &cpu->env;
 246
 247        if (!(env->uncached_asr & ASR_I)) {
 248            cs->exception_index = UC32_EXCP_INTR;
 249            uc32_cpu_do_interrupt(cs);
 250            return true;
 251        }
 252    }
 253    return false;
 254}
 255