LXR qemu/hw/arm/stm32f205

   1/*
   2 * STM32F205 SoC
   3 *
   4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qapi/error.h"
  27#include "qemu-common.h"
  28#include "hw/arm/arm.h"
  29#include "exec/address-spaces.h"
  30#include "hw/arm/stm32f205_soc.h"
  31
  32/* At the moment only Timer 2 to 5 are modelled */
  33static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
  34    0x40000800, 0x40000C00 };
  35static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
  36    0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
  37static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
  38    0x40012200 };
  39static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
  40    0x40003C00 };
  41
  42static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
  43static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
  44#define ADC_IRQ 18
  45static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
  46
  47static void stm32f205_soc_initfn(Object *obj)
  48{
  49    STM32F205State *s = STM32F205_SOC(obj);
  50    int i;
  51
  52    object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
  53    qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
  54
  55    object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
  56    qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
  57
  58    for (i = 0; i < STM_NUM_USARTS; i++) {
  59        object_initialize(&s->usart[i], sizeof(s->usart[i]),
  60                          TYPE_STM32F2XX_USART);
  61        qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
  62    }
  63
  64    for (i = 0; i < STM_NUM_TIMERS; i++) {
  65        object_initialize(&s->timer[i], sizeof(s->timer[i]),
  66                          TYPE_STM32F2XX_TIMER);
  67        qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
  68    }
  69
  70    s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
  71
  72    for (i = 0; i < STM_NUM_ADCS; i++) {
  73        object_initialize(&s->adc[i], sizeof(s->adc[i]),
  74                          TYPE_STM32F2XX_ADC);
  75        qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
  76    }
  77
  78    for (i = 0; i < STM_NUM_SPIS; i++) {
  79        object_initialize(&s->spi[i], sizeof(s->spi[i]),
  80                          TYPE_STM32F2XX_SPI);
  81        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
  82    }
  83}
  84
  85static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
  86{
  87    STM32F205State *s = STM32F205_SOC(dev_soc);
  88    DeviceState *dev, *armv7m;
  89    SysBusDevice *busdev;
  90    Error *err = NULL;
  91    int i;
  92
  93    MemoryRegion *system_memory = get_system_memory();
  94    MemoryRegion *sram = g_new(MemoryRegion, 1);
  95    MemoryRegion *flash = g_new(MemoryRegion, 1);
  96    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  97
  98    memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
  99                           &error_fatal);
 100    memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
 101                             flash, 0, FLASH_SIZE);
 102
 103    memory_region_set_readonly(flash, true);
 104    memory_region_set_readonly(flash_alias, true);
 105
 106    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
 107    memory_region_add_subregion(system_memory, 0, flash_alias);
 108
 109    memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
 110                           &error_fatal);
 111    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 112
 113    armv7m = DEVICE(&s->armv7m);
 114    qdev_prop_set_uint32(armv7m, "num-irq", 96);
 115    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 116    object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
 117                                     "memory", &error_abort);
 118    object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
 119    if (err != NULL) {
 120        error_propagate(errp, err);
 121        return;
 122    }
 123
 124    /* System configuration controller */
 125    dev = DEVICE(&s->syscfg);
 126    object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
 127    if (err != NULL) {
 128        error_propagate(errp, err);
 129        return;
 130    }
 131    busdev = SYS_BUS_DEVICE(dev);
 132    sysbus_mmio_map(busdev, 0, 0x40013800);
 133    sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
 134
 135    /* Attach UART (uses USART registers) and USART controllers */
 136    for (i = 0; i < STM_NUM_USARTS; i++) {
 137        dev = DEVICE(&(s->usart[i]));
 138        qdev_prop_set_chr(dev, "chardev",
 139                          i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
 140        object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
 141        if (err != NULL) {
 142            error_propagate(errp, err);
 143            return;
 144        }
 145        busdev = SYS_BUS_DEVICE(dev);
 146        sysbus_mmio_map(busdev, 0, usart_addr[i]);
 147        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
 148    }
 149
 150    /* Timer 2 to 5 */
 151    for (i = 0; i < STM_NUM_TIMERS; i++) {
 152        dev = DEVICE(&(s->timer[i]));
 153        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
 154        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 155        if (err != NULL) {
 156            error_propagate(errp, err);
 157            return;
 158        }
 159        busdev = SYS_BUS_DEVICE(dev);
 160        sysbus_mmio_map(busdev, 0, timer_addr[i]);
 161        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
 162    }
 163
 164    /* ADC 1 to 3 */
 165    object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
 166                            "num-lines", &err);
 167    object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
 168    if (err != NULL) {
 169        error_propagate(errp, err);
 170        return;
 171    }
 172    qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
 173                          qdev_get_gpio_in(armv7m, ADC_IRQ));
 174
 175    for (i = 0; i < STM_NUM_ADCS; i++) {
 176        dev = DEVICE(&(s->adc[i]));
 177        object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
 178        if (err != NULL) {
 179            error_propagate(errp, err);
 180            return;
 181        }
 182        busdev = SYS_BUS_DEVICE(dev);
 183        sysbus_mmio_map(busdev, 0, adc_addr[i]);
 184        sysbus_connect_irq(busdev, 0,
 185                           qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
 186    }
 187
 188    /* SPI 1 and 2 */
 189    for (i = 0; i < STM_NUM_SPIS; i++) {
 190        dev = DEVICE(&(s->spi[i]));
 191        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 192        if (err != NULL) {
 193            error_propagate(errp, err);
 194            return;
 195        }
 196        busdev = SYS_BUS_DEVICE(dev);
 197        sysbus_mmio_map(busdev, 0, spi_addr[i]);
 198        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
 199    }
 200}
 201
 202static Property stm32f205_soc_properties[] = {
 203    DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
 204    DEFINE_PROP_END_OF_LIST(),
 205};
 206
 207static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 208{
 209    DeviceClass *dc = DEVICE_CLASS(klass);
 210
 211    dc->realize = stm32f205_soc_realize;
 212    dc->props = stm32f205_soc_properties;
 213}
 214
 215static const TypeInfo stm32f205_soc_info = {
 216    .name          = TYPE_STM32F205_SOC,
 217    .parent        = TYPE_SYS_BUS_DEVICE,
 218    .instance_size = sizeof(STM32F205State),
 219    .instance_init = stm32f205_soc_initfn,
 220    .class_init    = stm32f205_soc_class_init,
 221};
 222
 223static void stm32f205_soc_types(void)
 224{
 225    type_register_static(&stm32f205_soc_info);
 226}
 227
 228type_init(stm32f205_soc_types)
 229