qemu/hw/char/serial.c
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   1/*
   2 * QEMU 16550A UART emulation
   3 *
   4 * Copyright (c) 2003-2004 Fabrice Bellard
   5 * Copyright (c) 2008 Citrix Systems, Inc.
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25
  26#include "qemu/osdep.h"
  27#include "hw/char/serial.h"
  28#include "chardev/char-serial.h"
  29#include "qapi/error.h"
  30#include "qemu/timer.h"
  31#include "exec/address-spaces.h"
  32#include "qemu/error-report.h"
  33
  34//#define DEBUG_SERIAL
  35
  36#define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  37
  38#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  39#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  40#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  41#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  42
  43#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  44#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  45
  46#define UART_IIR_MSI    0x00    /* Modem status interrupt */
  47#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  48#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  49#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  50#define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  51
  52#define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  53#define UART_IIR_FE     0xC0    /* Fifo enabled */
  54
  55/*
  56 * These are the definitions for the Modem Control Register
  57 */
  58#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  59#define UART_MCR_OUT2   0x08    /* Out2 complement */
  60#define UART_MCR_OUT1   0x04    /* Out1 complement */
  61#define UART_MCR_RTS    0x02    /* RTS complement */
  62#define UART_MCR_DTR    0x01    /* DTR complement */
  63
  64/*
  65 * These are the definitions for the Modem Status Register
  66 */
  67#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  68#define UART_MSR_RI     0x40    /* Ring Indicator */
  69#define UART_MSR_DSR    0x20    /* Data Set Ready */
  70#define UART_MSR_CTS    0x10    /* Clear to Send */
  71#define UART_MSR_DDCD   0x08    /* Delta DCD */
  72#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  73#define UART_MSR_DDSR   0x02    /* Delta DSR */
  74#define UART_MSR_DCTS   0x01    /* Delta CTS */
  75#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  76
  77#define UART_LSR_TEMT   0x40    /* Transmitter empty */
  78#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  79#define UART_LSR_BI     0x10    /* Break interrupt indicator */
  80#define UART_LSR_FE     0x08    /* Frame error indicator */
  81#define UART_LSR_PE     0x04    /* Parity error indicator */
  82#define UART_LSR_OE     0x02    /* Overrun error indicator */
  83#define UART_LSR_DR     0x01    /* Receiver data ready */
  84#define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  85
  86/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  87
  88#define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  89#define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  90#define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  91#define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  92
  93#define UART_FCR_DMS        0x08    /* DMA Mode Select */
  94#define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  95#define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  96#define UART_FCR_FE         0x01    /* FIFO Enable */
  97
  98#define MAX_XMIT_RETRY      4
  99
 100#ifdef DEBUG_SERIAL
 101#define DPRINTF(fmt, ...) \
 102do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 103#else
 104#define DPRINTF(fmt, ...) \
 105do {} while (0)
 106#endif
 107
 108static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 109static void serial_xmit(SerialState *s);
 110
 111static inline void recv_fifo_put(SerialState *s, uint8_t chr)
 112{
 113    /* Receive overruns do not overwrite FIFO contents. */
 114    if (!fifo8_is_full(&s->recv_fifo)) {
 115        fifo8_push(&s->recv_fifo, chr);
 116    } else {
 117        s->lsr |= UART_LSR_OE;
 118    }
 119}
 120
 121static void serial_update_irq(SerialState *s)
 122{
 123    uint8_t tmp_iir = UART_IIR_NO_INT;
 124
 125    if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 126        tmp_iir = UART_IIR_RLSI;
 127    } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 128        /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 129         * this is not in the specification but is observed on existing
 130         * hardware.  */
 131        tmp_iir = UART_IIR_CTI;
 132    } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 133               (!(s->fcr & UART_FCR_FE) ||
 134                s->recv_fifo.num >= s->recv_fifo_itl)) {
 135        tmp_iir = UART_IIR_RDI;
 136    } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 137        tmp_iir = UART_IIR_THRI;
 138    } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 139        tmp_iir = UART_IIR_MSI;
 140    }
 141
 142    s->iir = tmp_iir | (s->iir & 0xF0);
 143
 144    if (tmp_iir != UART_IIR_NO_INT) {
 145        qemu_irq_raise(s->irq);
 146    } else {
 147        qemu_irq_lower(s->irq);
 148    }
 149}
 150
 151static void serial_update_parameters(SerialState *s)
 152{
 153    int speed, parity, data_bits, stop_bits, frame_size;
 154    QEMUSerialSetParams ssp;
 155
 156    if (s->divider == 0 || s->divider > s->baudbase) {
 157        return;
 158    }
 159
 160    /* Start bit. */
 161    frame_size = 1;
 162    if (s->lcr & 0x08) {
 163        /* Parity bit. */
 164        frame_size++;
 165        if (s->lcr & 0x10)
 166            parity = 'E';
 167        else
 168            parity = 'O';
 169    } else {
 170            parity = 'N';
 171    }
 172    if (s->lcr & 0x04)
 173        stop_bits = 2;
 174    else
 175        stop_bits = 1;
 176
 177    data_bits = (s->lcr & 0x03) + 5;
 178    frame_size += data_bits + stop_bits;
 179    speed = s->baudbase / s->divider;
 180    ssp.speed = speed;
 181    ssp.parity = parity;
 182    ssp.data_bits = data_bits;
 183    ssp.stop_bits = stop_bits;
 184    s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
 185    qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 186
 187    DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
 188           speed, parity, data_bits, stop_bits);
 189}
 190
 191static void serial_update_msl(SerialState *s)
 192{
 193    uint8_t omsr;
 194    int flags;
 195
 196    timer_del(s->modem_status_poll);
 197
 198    if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM,
 199                          &flags) == -ENOTSUP) {
 200        s->poll_msl = -1;
 201        return;
 202    }
 203
 204    omsr = s->msr;
 205
 206    s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 207    s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 208    s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 209    s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 210
 211    if (s->msr != omsr) {
 212         /* Set delta bits */
 213         s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 214         /* UART_MSR_TERI only if change was from 1 -> 0 */
 215         if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 216             s->msr &= ~UART_MSR_TERI;
 217         serial_update_irq(s);
 218    }
 219
 220    /* The real 16550A apparently has a 250ns response latency to line status changes.
 221       We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 222
 223    if (s->poll_msl) {
 224        timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 225                  NANOSECONDS_PER_SECOND / 100);
 226    }
 227}
 228
 229static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond,
 230                                void *opaque)
 231{
 232    SerialState *s = opaque;
 233    s->watch_tag = 0;
 234    serial_xmit(s);
 235    return FALSE;
 236}
 237
 238static void serial_xmit(SerialState *s)
 239{
 240    do {
 241        assert(!(s->lsr & UART_LSR_TEMT));
 242        if (s->tsr_retry == 0) {
 243            assert(!(s->lsr & UART_LSR_THRE));
 244
 245            if (s->fcr & UART_FCR_FE) {
 246                assert(!fifo8_is_empty(&s->xmit_fifo));
 247                s->tsr = fifo8_pop(&s->xmit_fifo);
 248                if (!s->xmit_fifo.num) {
 249                    s->lsr |= UART_LSR_THRE;
 250                }
 251            } else {
 252                s->tsr = s->thr;
 253                s->lsr |= UART_LSR_THRE;
 254            }
 255            if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) {
 256                s->thr_ipending = 1;
 257                serial_update_irq(s);
 258            }
 259        }
 260
 261        if (s->mcr & UART_MCR_LOOP) {
 262            /* in loopback mode, say that we just received a char */
 263            serial_receive1(s, &s->tsr, 1);
 264        } else if (qemu_chr_fe_write(&s->chr, &s->tsr, 1) != 1 &&
 265                   s->tsr_retry < MAX_XMIT_RETRY) {
 266            assert(s->watch_tag == 0);
 267            s->watch_tag =
 268                qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 269                                      serial_watch_cb, s);
 270            if (s->watch_tag > 0) {
 271                s->tsr_retry++;
 272                return;
 273            }
 274        }
 275        s->tsr_retry = 0;
 276
 277        /* Transmit another byte if it is already available. It is only
 278           possible when FIFO is enabled and not empty. */
 279    } while (!(s->lsr & UART_LSR_THRE));
 280
 281    s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 282    s->lsr |= UART_LSR_TEMT;
 283}
 284
 285/* Setter for FCR.
 286   is_load flag means, that value is set while loading VM state
 287   and interrupt should not be invoked */
 288static void serial_write_fcr(SerialState *s, uint8_t val)
 289{
 290    /* Set fcr - val only has the bits that are supposed to "stick" */
 291    s->fcr = val;
 292
 293    if (val & UART_FCR_FE) {
 294        s->iir |= UART_IIR_FE;
 295        /* Set recv_fifo trigger Level */
 296        switch (val & 0xC0) {
 297        case UART_FCR_ITL_1:
 298            s->recv_fifo_itl = 1;
 299            break;
 300        case UART_FCR_ITL_2:
 301            s->recv_fifo_itl = 4;
 302            break;
 303        case UART_FCR_ITL_3:
 304            s->recv_fifo_itl = 8;
 305            break;
 306        case UART_FCR_ITL_4:
 307            s->recv_fifo_itl = 14;
 308            break;
 309        }
 310    } else {
 311        s->iir &= ~UART_IIR_FE;
 312    }
 313}
 314
 315static void serial_update_tiocm(SerialState *s)
 316{
 317    int flags;
 318
 319    qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 320
 321    flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 322
 323    if (s->mcr & UART_MCR_RTS) {
 324        flags |= CHR_TIOCM_RTS;
 325    }
 326    if (s->mcr & UART_MCR_DTR) {
 327        flags |= CHR_TIOCM_DTR;
 328    }
 329
 330    qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 331}
 332
 333static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 334                                unsigned size)
 335{
 336    SerialState *s = opaque;
 337
 338    addr &= 7;
 339    DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val);
 340    switch(addr) {
 341    default:
 342    case 0:
 343        if (s->lcr & UART_LCR_DLAB) {
 344            s->divider = (s->divider & 0xff00) | val;
 345            serial_update_parameters(s);
 346        } else {
 347            s->thr = (uint8_t) val;
 348            if(s->fcr & UART_FCR_FE) {
 349                /* xmit overruns overwrite data, so make space if needed */
 350                if (fifo8_is_full(&s->xmit_fifo)) {
 351                    fifo8_pop(&s->xmit_fifo);
 352                }
 353                fifo8_push(&s->xmit_fifo, s->thr);
 354            }
 355            s->thr_ipending = 0;
 356            s->lsr &= ~UART_LSR_THRE;
 357            s->lsr &= ~UART_LSR_TEMT;
 358            serial_update_irq(s);
 359            if (s->tsr_retry == 0) {
 360                serial_xmit(s);
 361            }
 362        }
 363        break;
 364    case 1:
 365        if (s->lcr & UART_LCR_DLAB) {
 366            s->divider = (s->divider & 0x00ff) | (val << 8);
 367            serial_update_parameters(s);
 368        } else {
 369            uint8_t changed = (s->ier ^ val) & 0x0f;
 370            s->ier = val & 0x0f;
 371            /* If the backend device is a real serial port, turn polling of the modem
 372             * status lines on physical port on or off depending on UART_IER_MSI state.
 373             */
 374            if ((changed & UART_IER_MSI) && s->poll_msl >= 0) {
 375                if (s->ier & UART_IER_MSI) {
 376                     s->poll_msl = 1;
 377                     serial_update_msl(s);
 378                } else {
 379                     timer_del(s->modem_status_poll);
 380                     s->poll_msl = 0;
 381                }
 382            }
 383
 384            /* Turning on the THRE interrupt on IER can trigger the interrupt
 385             * if LSR.THRE=1, even if it had been masked before by reading IIR.
 386             * This is not in the datasheet, but Windows relies on it.  It is
 387             * unclear if THRE has to be resampled every time THRI becomes
 388             * 1, or only on the rising edge.  Bochs does the latter, and Windows
 389             * always toggles IER to all zeroes and back to all ones, so do the
 390             * same.
 391             *
 392             * If IER.THRI is zero, thr_ipending is not used.  Set it to zero
 393             * so that the thr_ipending subsection is not migrated.
 394             */
 395            if (changed & UART_IER_THRI) {
 396                if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) {
 397                    s->thr_ipending = 1;
 398                } else {
 399                    s->thr_ipending = 0;
 400                }
 401            }
 402
 403            if (changed) {
 404                serial_update_irq(s);
 405            }
 406        }
 407        break;
 408    case 2:
 409        /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 410        if ((val ^ s->fcr) & UART_FCR_FE) {
 411            val |= UART_FCR_XFR | UART_FCR_RFR;
 412        }
 413
 414        /* FIFO clear */
 415
 416        if (val & UART_FCR_RFR) {
 417            s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 418            timer_del(s->fifo_timeout_timer);
 419            s->timeout_ipending = 0;
 420            fifo8_reset(&s->recv_fifo);
 421        }
 422
 423        if (val & UART_FCR_XFR) {
 424            s->lsr |= UART_LSR_THRE;
 425            s->thr_ipending = 1;
 426            fifo8_reset(&s->xmit_fifo);
 427        }
 428
 429        serial_write_fcr(s, val & 0xC9);
 430        serial_update_irq(s);
 431        break;
 432    case 3:
 433        {
 434            int break_enable;
 435            s->lcr = val;
 436            serial_update_parameters(s);
 437            break_enable = (val >> 6) & 1;
 438            if (break_enable != s->last_break_enable) {
 439                s->last_break_enable = break_enable;
 440                qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 441                                  &break_enable);
 442            }
 443        }
 444        break;
 445    case 4:
 446        {
 447            int old_mcr = s->mcr;
 448            s->mcr = val & 0x1f;
 449            if (val & UART_MCR_LOOP)
 450                break;
 451
 452            if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 453                serial_update_tiocm(s);
 454                /* Update the modem status after a one-character-send wait-time, since there may be a response
 455                   from the device/computer at the other end of the serial line */
 456                timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time);
 457            }
 458        }
 459        break;
 460    case 5:
 461        break;
 462    case 6:
 463        break;
 464    case 7:
 465        s->scr = val;
 466        break;
 467    }
 468}
 469
 470static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
 471{
 472    SerialState *s = opaque;
 473    uint32_t ret;
 474
 475    addr &= 7;
 476    switch(addr) {
 477    default:
 478    case 0:
 479        if (s->lcr & UART_LCR_DLAB) {
 480            ret = s->divider & 0xff;
 481        } else {
 482            if(s->fcr & UART_FCR_FE) {
 483                ret = fifo8_is_empty(&s->recv_fifo) ?
 484                            0 : fifo8_pop(&s->recv_fifo);
 485                if (s->recv_fifo.num == 0) {
 486                    s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 487                } else {
 488                    timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 489                }
 490                s->timeout_ipending = 0;
 491            } else {
 492                ret = s->rbr;
 493                s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 494            }
 495            serial_update_irq(s);
 496            if (!(s->mcr & UART_MCR_LOOP)) {
 497                /* in loopback mode, don't receive any data */
 498                qemu_chr_fe_accept_input(&s->chr);
 499            }
 500        }
 501        break;
 502    case 1:
 503        if (s->lcr & UART_LCR_DLAB) {
 504            ret = (s->divider >> 8) & 0xff;
 505        } else {
 506            ret = s->ier;
 507        }
 508        break;
 509    case 2:
 510        ret = s->iir;
 511        if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 512            s->thr_ipending = 0;
 513            serial_update_irq(s);
 514        }
 515        break;
 516    case 3:
 517        ret = s->lcr;
 518        break;
 519    case 4:
 520        ret = s->mcr;
 521        break;
 522    case 5:
 523        ret = s->lsr;
 524        /* Clear break and overrun interrupts */
 525        if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 526            s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 527            serial_update_irq(s);
 528        }
 529        break;
 530    case 6:
 531        if (s->mcr & UART_MCR_LOOP) {
 532            /* in loopback, the modem output pins are connected to the
 533               inputs */
 534            ret = (s->mcr & 0x0c) << 4;
 535            ret |= (s->mcr & 0x02) << 3;
 536            ret |= (s->mcr & 0x01) << 5;
 537        } else {
 538            if (s->poll_msl >= 0)
 539                serial_update_msl(s);
 540            ret = s->msr;
 541            /* Clear delta bits & msr int after read, if they were set */
 542            if (s->msr & UART_MSR_ANY_DELTA) {
 543                s->msr &= 0xF0;
 544                serial_update_irq(s);
 545            }
 546        }
 547        break;
 548    case 7:
 549        ret = s->scr;
 550        break;
 551    }
 552    DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret);
 553    return ret;
 554}
 555
 556static int serial_can_receive(SerialState *s)
 557{
 558    if(s->fcr & UART_FCR_FE) {
 559        if (s->recv_fifo.num < UART_FIFO_LENGTH) {
 560            /*
 561             * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
 562             * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
 563             * effect will be to almost always fill the fifo completely before
 564             * the guest has a chance to respond, effectively overriding the ITL
 565             * that the guest has set.
 566             */
 567            return (s->recv_fifo.num <= s->recv_fifo_itl) ?
 568                        s->recv_fifo_itl - s->recv_fifo.num : 1;
 569        } else {
 570            return 0;
 571        }
 572    } else {
 573        return !(s->lsr & UART_LSR_DR);
 574    }
 575}
 576
 577static void serial_receive_break(SerialState *s)
 578{
 579    s->rbr = 0;
 580    /* When the LSR_DR is set a null byte is pushed into the fifo */
 581    recv_fifo_put(s, '\0');
 582    s->lsr |= UART_LSR_BI | UART_LSR_DR;
 583    serial_update_irq(s);
 584}
 585
 586/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 587static void fifo_timeout_int (void *opaque) {
 588    SerialState *s = opaque;
 589    if (s->recv_fifo.num) {
 590        s->timeout_ipending = 1;
 591        serial_update_irq(s);
 592    }
 593}
 594
 595static int serial_can_receive1(void *opaque)
 596{
 597    SerialState *s = opaque;
 598    return serial_can_receive(s);
 599}
 600
 601static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 602{
 603    SerialState *s = opaque;
 604
 605    if (s->wakeup) {
 606        qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
 607    }
 608    if(s->fcr & UART_FCR_FE) {
 609        int i;
 610        for (i = 0; i < size; i++) {
 611            recv_fifo_put(s, buf[i]);
 612        }
 613        s->lsr |= UART_LSR_DR;
 614        /* call the timeout receive callback in 4 char transmit time */
 615        timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4);
 616    } else {
 617        if (s->lsr & UART_LSR_DR)
 618            s->lsr |= UART_LSR_OE;
 619        s->rbr = buf[0];
 620        s->lsr |= UART_LSR_DR;
 621    }
 622    serial_update_irq(s);
 623}
 624
 625static void serial_event(void *opaque, int event)
 626{
 627    SerialState *s = opaque;
 628    DPRINTF("event %x\n", event);
 629    if (event == CHR_EVENT_BREAK)
 630        serial_receive_break(s);
 631}
 632
 633static int serial_pre_save(void *opaque)
 634{
 635    SerialState *s = opaque;
 636    s->fcr_vmstate = s->fcr;
 637
 638    return 0;
 639}
 640
 641static int serial_pre_load(void *opaque)
 642{
 643    SerialState *s = opaque;
 644    s->thr_ipending = -1;
 645    s->poll_msl = -1;
 646    return 0;
 647}
 648
 649static int serial_post_load(void *opaque, int version_id)
 650{
 651    SerialState *s = opaque;
 652
 653    if (version_id < 3) {
 654        s->fcr_vmstate = 0;
 655    }
 656    if (s->thr_ipending == -1) {
 657        s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 658    }
 659
 660    if (s->tsr_retry > 0) {
 661        /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty).  */
 662        if (s->lsr & UART_LSR_TEMT) {
 663            error_report("inconsistent state in serial device "
 664                         "(tsr empty, tsr_retry=%d", s->tsr_retry);
 665            return -1;
 666        }
 667
 668        if (s->tsr_retry > MAX_XMIT_RETRY) {
 669            s->tsr_retry = MAX_XMIT_RETRY;
 670        }
 671
 672        assert(s->watch_tag == 0);
 673        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 674                                             serial_watch_cb, s);
 675    } else {
 676        /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty).  */
 677        if (!(s->lsr & UART_LSR_TEMT)) {
 678            error_report("inconsistent state in serial device "
 679                         "(tsr not empty, tsr_retry=0");
 680            return -1;
 681        }
 682    }
 683
 684    s->last_break_enable = (s->lcr >> 6) & 1;
 685    /* Initialize fcr via setter to perform essential side-effects */
 686    serial_write_fcr(s, s->fcr_vmstate);
 687    serial_update_parameters(s);
 688    return 0;
 689}
 690
 691static bool serial_thr_ipending_needed(void *opaque)
 692{
 693    SerialState *s = opaque;
 694
 695    if (s->ier & UART_IER_THRI) {
 696        bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI);
 697        return s->thr_ipending != expected_value;
 698    } else {
 699        /* LSR.THRE will be sampled again when the interrupt is
 700         * enabled.  thr_ipending is not used in this case, do
 701         * not migrate it.
 702         */
 703        return false;
 704    }
 705}
 706
 707static const VMStateDescription vmstate_serial_thr_ipending = {
 708    .name = "serial/thr_ipending",
 709    .version_id = 1,
 710    .minimum_version_id = 1,
 711    .needed = serial_thr_ipending_needed,
 712    .fields = (VMStateField[]) {
 713        VMSTATE_INT32(thr_ipending, SerialState),
 714        VMSTATE_END_OF_LIST()
 715    }
 716};
 717
 718static bool serial_tsr_needed(void *opaque)
 719{
 720    SerialState *s = (SerialState *)opaque;
 721    return s->tsr_retry != 0;
 722}
 723
 724static const VMStateDescription vmstate_serial_tsr = {
 725    .name = "serial/tsr",
 726    .version_id = 1,
 727    .minimum_version_id = 1,
 728    .needed = serial_tsr_needed,
 729    .fields = (VMStateField[]) {
 730        VMSTATE_UINT32(tsr_retry, SerialState),
 731        VMSTATE_UINT8(thr, SerialState),
 732        VMSTATE_UINT8(tsr, SerialState),
 733        VMSTATE_END_OF_LIST()
 734    }
 735};
 736
 737static bool serial_recv_fifo_needed(void *opaque)
 738{
 739    SerialState *s = (SerialState *)opaque;
 740    return !fifo8_is_empty(&s->recv_fifo);
 741
 742}
 743
 744static const VMStateDescription vmstate_serial_recv_fifo = {
 745    .name = "serial/recv_fifo",
 746    .version_id = 1,
 747    .minimum_version_id = 1,
 748    .needed = serial_recv_fifo_needed,
 749    .fields = (VMStateField[]) {
 750        VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 751        VMSTATE_END_OF_LIST()
 752    }
 753};
 754
 755static bool serial_xmit_fifo_needed(void *opaque)
 756{
 757    SerialState *s = (SerialState *)opaque;
 758    return !fifo8_is_empty(&s->xmit_fifo);
 759}
 760
 761static const VMStateDescription vmstate_serial_xmit_fifo = {
 762    .name = "serial/xmit_fifo",
 763    .version_id = 1,
 764    .minimum_version_id = 1,
 765    .needed = serial_xmit_fifo_needed,
 766    .fields = (VMStateField[]) {
 767        VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8),
 768        VMSTATE_END_OF_LIST()
 769    }
 770};
 771
 772static bool serial_fifo_timeout_timer_needed(void *opaque)
 773{
 774    SerialState *s = (SerialState *)opaque;
 775    return timer_pending(s->fifo_timeout_timer);
 776}
 777
 778static const VMStateDescription vmstate_serial_fifo_timeout_timer = {
 779    .name = "serial/fifo_timeout_timer",
 780    .version_id = 1,
 781    .minimum_version_id = 1,
 782    .needed = serial_fifo_timeout_timer_needed,
 783    .fields = (VMStateField[]) {
 784        VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState),
 785        VMSTATE_END_OF_LIST()
 786    }
 787};
 788
 789static bool serial_timeout_ipending_needed(void *opaque)
 790{
 791    SerialState *s = (SerialState *)opaque;
 792    return s->timeout_ipending != 0;
 793}
 794
 795static const VMStateDescription vmstate_serial_timeout_ipending = {
 796    .name = "serial/timeout_ipending",
 797    .version_id = 1,
 798    .minimum_version_id = 1,
 799    .needed = serial_timeout_ipending_needed,
 800    .fields = (VMStateField[]) {
 801        VMSTATE_INT32(timeout_ipending, SerialState),
 802        VMSTATE_END_OF_LIST()
 803    }
 804};
 805
 806static bool serial_poll_needed(void *opaque)
 807{
 808    SerialState *s = (SerialState *)opaque;
 809    return s->poll_msl >= 0;
 810}
 811
 812static const VMStateDescription vmstate_serial_poll = {
 813    .name = "serial/poll",
 814    .version_id = 1,
 815    .needed = serial_poll_needed,
 816    .minimum_version_id = 1,
 817    .fields = (VMStateField[]) {
 818        VMSTATE_INT32(poll_msl, SerialState),
 819        VMSTATE_TIMER_PTR(modem_status_poll, SerialState),
 820        VMSTATE_END_OF_LIST()
 821    }
 822};
 823
 824const VMStateDescription vmstate_serial = {
 825    .name = "serial",
 826    .version_id = 3,
 827    .minimum_version_id = 2,
 828    .pre_save = serial_pre_save,
 829    .pre_load = serial_pre_load,
 830    .post_load = serial_post_load,
 831    .fields = (VMStateField[]) {
 832        VMSTATE_UINT16_V(divider, SerialState, 2),
 833        VMSTATE_UINT8(rbr, SerialState),
 834        VMSTATE_UINT8(ier, SerialState),
 835        VMSTATE_UINT8(iir, SerialState),
 836        VMSTATE_UINT8(lcr, SerialState),
 837        VMSTATE_UINT8(mcr, SerialState),
 838        VMSTATE_UINT8(lsr, SerialState),
 839        VMSTATE_UINT8(msr, SerialState),
 840        VMSTATE_UINT8(scr, SerialState),
 841        VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 842        VMSTATE_END_OF_LIST()
 843    },
 844    .subsections = (const VMStateDescription*[]) {
 845        &vmstate_serial_thr_ipending,
 846        &vmstate_serial_tsr,
 847        &vmstate_serial_recv_fifo,
 848        &vmstate_serial_xmit_fifo,
 849        &vmstate_serial_fifo_timeout_timer,
 850        &vmstate_serial_timeout_ipending,
 851        &vmstate_serial_poll,
 852        NULL
 853    }
 854};
 855
 856static void serial_reset(void *opaque)
 857{
 858    SerialState *s = opaque;
 859
 860    if (s->watch_tag > 0) {
 861        g_source_remove(s->watch_tag);
 862        s->watch_tag = 0;
 863    }
 864
 865    s->rbr = 0;
 866    s->ier = 0;
 867    s->iir = UART_IIR_NO_INT;
 868    s->lcr = 0;
 869    s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 870    s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 871    /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 872    s->divider = 0x0C;
 873    s->mcr = UART_MCR_OUT2;
 874    s->scr = 0;
 875    s->tsr_retry = 0;
 876    s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 877    s->poll_msl = 0;
 878
 879    s->timeout_ipending = 0;
 880    timer_del(s->fifo_timeout_timer);
 881    timer_del(s->modem_status_poll);
 882
 883    fifo8_reset(&s->recv_fifo);
 884    fifo8_reset(&s->xmit_fifo);
 885
 886    s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 887
 888    s->thr_ipending = 0;
 889    s->last_break_enable = 0;
 890    qemu_irq_lower(s->irq);
 891
 892    serial_update_msl(s);
 893    s->msr &= ~UART_MSR_ANY_DELTA;
 894}
 895
 896static int serial_be_change(void *opaque)
 897{
 898    SerialState *s = opaque;
 899
 900    qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
 901                             serial_event, serial_be_change, s, NULL, true);
 902
 903    serial_update_parameters(s);
 904
 905    qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 906                      &s->last_break_enable);
 907
 908    s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0;
 909    serial_update_msl(s);
 910
 911    if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) {
 912        serial_update_tiocm(s);
 913    }
 914
 915    if (s->watch_tag > 0) {
 916        g_source_remove(s->watch_tag);
 917        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 918                                             serial_watch_cb, s);
 919    }
 920
 921    return 0;
 922}
 923
 924void serial_realize_core(SerialState *s, Error **errp)
 925{
 926    if (!qemu_chr_fe_backend_connected(&s->chr)) {
 927        error_setg(errp, "Can't create serial device, empty char device");
 928        return;
 929    }
 930
 931    s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
 932
 933    s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
 934    qemu_register_reset(serial_reset, s);
 935
 936    qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
 937                             serial_event, serial_be_change, s, NULL, true);
 938    fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
 939    fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
 940    serial_reset(s);
 941}
 942
 943void serial_exit_core(SerialState *s)
 944{
 945    qemu_chr_fe_deinit(&s->chr, false);
 946
 947    timer_del(s->modem_status_poll);
 948    timer_free(s->modem_status_poll);
 949
 950    timer_del(s->fifo_timeout_timer);
 951    timer_free(s->fifo_timeout_timer);
 952
 953    fifo8_destroy(&s->recv_fifo);
 954    fifo8_destroy(&s->xmit_fifo);
 955
 956    qemu_unregister_reset(serial_reset, s);
 957}
 958
 959/* Change the main reference oscillator frequency. */
 960void serial_set_frequency(SerialState *s, uint32_t frequency)
 961{
 962    s->baudbase = frequency;
 963    serial_update_parameters(s);
 964}
 965
 966const MemoryRegionOps serial_io_ops = {
 967    .read = serial_ioport_read,
 968    .write = serial_ioport_write,
 969    .impl = {
 970        .min_access_size = 1,
 971        .max_access_size = 1,
 972    },
 973    .endianness = DEVICE_LITTLE_ENDIAN,
 974};
 975
 976SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 977                         Chardev *chr, MemoryRegion *system_io)
 978{
 979    SerialState *s;
 980
 981    s = g_malloc0(sizeof(SerialState));
 982
 983    s->irq = irq;
 984    s->baudbase = baudbase;
 985    qemu_chr_fe_init(&s->chr, chr, &error_abort);
 986    serial_realize_core(s, &error_fatal);
 987
 988    vmstate_register(NULL, base, &vmstate_serial, s);
 989
 990    memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
 991    memory_region_add_subregion(system_io, base, &s->io);
 992
 993    return s;
 994}
 995
 996/* Memory mapped interface */
 997static uint64_t serial_mm_read(void *opaque, hwaddr addr,
 998                               unsigned size)
 999{
1000    SerialState *s = opaque;
1001    return serial_ioport_read(s, addr >> s->it_shift, 1);
1002}
1003
1004static void serial_mm_write(void *opaque, hwaddr addr,
1005                            uint64_t value, unsigned size)
1006{
1007    SerialState *s = opaque;
1008    value &= 255;
1009    serial_ioport_write(s, addr >> s->it_shift, value, 1);
1010}
1011
1012static const MemoryRegionOps serial_mm_ops[3] = {
1013    [DEVICE_NATIVE_ENDIAN] = {
1014        .read = serial_mm_read,
1015        .write = serial_mm_write,
1016        .endianness = DEVICE_NATIVE_ENDIAN,
1017        .valid.max_access_size = 8,
1018        .impl.max_access_size = 8,
1019    },
1020    [DEVICE_LITTLE_ENDIAN] = {
1021        .read = serial_mm_read,
1022        .write = serial_mm_write,
1023        .endianness = DEVICE_LITTLE_ENDIAN,
1024        .valid.max_access_size = 8,
1025        .impl.max_access_size = 8,
1026    },
1027    [DEVICE_BIG_ENDIAN] = {
1028        .read = serial_mm_read,
1029        .write = serial_mm_write,
1030        .endianness = DEVICE_BIG_ENDIAN,
1031        .valid.max_access_size = 8,
1032        .impl.max_access_size = 8,
1033    },
1034};
1035
1036SerialState *serial_mm_init(MemoryRegion *address_space,
1037                            hwaddr base, int it_shift,
1038                            qemu_irq irq, int baudbase,
1039                            Chardev *chr, enum device_endian end)
1040{
1041    SerialState *s;
1042
1043    s = g_malloc0(sizeof(SerialState));
1044
1045    s->it_shift = it_shift;
1046    s->irq = irq;
1047    s->baudbase = baudbase;
1048    qemu_chr_fe_init(&s->chr, chr, &error_abort);
1049
1050    serial_realize_core(s, &error_fatal);
1051    vmstate_register(NULL, base, &vmstate_serial, s);
1052
1053    memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
1054                          "serial", 8 << it_shift);
1055    memory_region_add_subregion(address_space, base, &s->io);
1056    return s;
1057}
1058