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26#include "qemu/osdep.h"
27#include "qemu/cutils.h"
28#include "qapi/error.h"
29#include "qemu-common.h"
30#include "cpu.h"
31#include "hw/hw.h"
32#include "hw/char/serial.h"
33#include "ui/console.h"
34#include "hw/devices.h"
35#include "hw/sysbus.h"
36#include "hw/pci/pci.h"
37#include "qemu/range.h"
38#include "ui/pixel_ops.h"
39#include "exec/address-spaces.h"
40
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60
61#ifdef DEBUG_SM501
62#define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
63#else
64#define SM501_DPRINTF(fmt, ...) do {} while (0)
65#endif
66
67#define MMIO_BASE_OFFSET 0x3e00000
68#define MMIO_SIZE 0x200000
69#define DC_PALETTE_ENTRIES (0x400 * 3)
70
71
72
73
74
75#define SM501_SYS_CONFIG (0x000000)
76
77
78#define SM501_SYSTEM_CONTROL (0x000000)
79
80#define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
81#define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
82#define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
83
84#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
85#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
86#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
87#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
88#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
89
90#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
91#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
92#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
93#define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
94
95
96
97#define SM501_MISC_CONTROL (0x000004)
98
99#define SM501_MISC_BUS_SH (0x0)
100#define SM501_MISC_BUS_PCI (0x1)
101#define SM501_MISC_BUS_XSCALE (0x2)
102#define SM501_MISC_BUS_NEC (0x6)
103#define SM501_MISC_BUS_MASK (0x7)
104
105#define SM501_MISC_VR_62MB (1 << 3)
106#define SM501_MISC_CDR_RESET (1 << 7)
107#define SM501_MISC_USB_LB (1 << 8)
108#define SM501_MISC_USB_SLAVE (1 << 9)
109#define SM501_MISC_BL_1 (1 << 10)
110#define SM501_MISC_MC (1 << 11)
111#define SM501_MISC_DAC_POWER (1 << 12)
112#define SM501_MISC_IRQ_INVERT (1 << 16)
113#define SM501_MISC_SH (1 << 17)
114
115#define SM501_MISC_HOLD_EMPTY (0 << 18)
116#define SM501_MISC_HOLD_8 (1 << 18)
117#define SM501_MISC_HOLD_16 (2 << 18)
118#define SM501_MISC_HOLD_24 (3 << 18)
119#define SM501_MISC_HOLD_32 (4 << 18)
120#define SM501_MISC_HOLD_MASK (7 << 18)
121
122#define SM501_MISC_FREQ_12 (1 << 24)
123#define SM501_MISC_PNL_24BIT (1 << 25)
124#define SM501_MISC_8051_LE (1 << 26)
125
126
127
128#define SM501_GPIO31_0_CONTROL (0x000008)
129#define SM501_GPIO63_32_CONTROL (0x00000C)
130#define SM501_DRAM_CONTROL (0x000010)
131
132
133#define SM501_ARBTRTN_CONTROL (0x000014)
134
135
136#define SM501_COMMAND_LIST_STATUS (0x000024)
137
138
139#define SM501_RAW_IRQ_STATUS (0x000028)
140#define SM501_RAW_IRQ_CLEAR (0x000028)
141#define SM501_IRQ_STATUS (0x00002C)
142#define SM501_IRQ_MASK (0x000030)
143#define SM501_DEBUG_CONTROL (0x000034)
144
145
146#define SM501_POWERMODE_P2X_SRC (1 << 29)
147#define SM501_POWERMODE_V2X_SRC (1 << 20)
148#define SM501_POWERMODE_M_SRC (1 << 12)
149#define SM501_POWERMODE_M1_SRC (1 << 4)
150
151#define SM501_CURRENT_GATE (0x000038)
152#define SM501_CURRENT_CLOCK (0x00003C)
153#define SM501_POWER_MODE_0_GATE (0x000040)
154#define SM501_POWER_MODE_0_CLOCK (0x000044)
155#define SM501_POWER_MODE_1_GATE (0x000048)
156#define SM501_POWER_MODE_1_CLOCK (0x00004C)
157#define SM501_SLEEP_MODE_GATE (0x000050)
158#define SM501_POWER_MODE_CONTROL (0x000054)
159
160
161#define SM501_GATE_HOST (0)
162#define SM501_GATE_MEMORY (1)
163#define SM501_GATE_DISPLAY (2)
164#define SM501_GATE_2D_ENGINE (3)
165#define SM501_GATE_CSC (4)
166#define SM501_GATE_ZVPORT (5)
167#define SM501_GATE_GPIO (6)
168#define SM501_GATE_UART0 (7)
169#define SM501_GATE_UART1 (8)
170#define SM501_GATE_SSP (10)
171#define SM501_GATE_USB_HOST (11)
172#define SM501_GATE_USB_GADGET (12)
173#define SM501_GATE_UCONTROLLER (17)
174#define SM501_GATE_AC97 (18)
175
176
177#define SM501_CLOCK_P2XCLK (24)
178
179#define SM501_CLOCK_V2XCLK (16)
180
181#define SM501_CLOCK_MCLK (8)
182
183#define SM501_CLOCK_M1XCLK (0)
184
185
186#define SM501_PCI_MASTER_BASE (0x000058)
187#define SM501_ENDIAN_CONTROL (0x00005C)
188#define SM501_DEVICEID (0x000060)
189
190
191#define SM501_DEVICEID_SM501 (0x05010000)
192#define SM501_DEVICEID_IDMASK (0xffff0000)
193#define SM501_DEVICEID_REVMASK (0x000000ff)
194
195#define SM501_PLLCLOCK_COUNT (0x000064)
196#define SM501_MISC_TIMING (0x000068)
197#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
198
199#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
200
201
202#define SM501_GPIO (0x010000)
203#define SM501_GPIO_DATA_LOW (0x00)
204#define SM501_GPIO_DATA_HIGH (0x04)
205#define SM501_GPIO_DDR_LOW (0x08)
206#define SM501_GPIO_DDR_HIGH (0x0C)
207#define SM501_GPIO_IRQ_SETUP (0x10)
208#define SM501_GPIO_IRQ_STATUS (0x14)
209#define SM501_GPIO_IRQ_RESET (0x14)
210
211
212#define SM501_I2C (0x010040)
213#define SM501_I2C_BYTE_COUNT (0x00)
214#define SM501_I2C_CONTROL (0x01)
215#define SM501_I2C_STATUS (0x02)
216#define SM501_I2C_RESET (0x02)
217#define SM501_I2C_SLAVE_ADDRESS (0x03)
218#define SM501_I2C_DATA (0x04)
219
220
221#define SM501_SSP (0x020000)
222
223
224#define SM501_UART0 (0x030000)
225
226
227#define SM501_UART1 (0x030020)
228
229
230#define SM501_USB_HOST (0x040000)
231
232
233#define SM501_USB_GADGET (0x060000)
234
235
236#define SM501_USB_GADGET_DATA (0x070000)
237
238
239#define SM501_DC (0x080000)
240
241
242#define SM501_ADDR_FLIP (1 << 31)
243#define SM501_ADDR_EXT (1 << 27)
244#define SM501_ADDR_CS1 (1 << 26)
245#define SM501_ADDR_MASK (0x3f << 26)
246
247#define SM501_FIFO_MASK (0x3 << 16)
248#define SM501_FIFO_1 (0x0 << 16)
249#define SM501_FIFO_3 (0x1 << 16)
250#define SM501_FIFO_7 (0x2 << 16)
251#define SM501_FIFO_11 (0x3 << 16)
252
253
254#define SM501_OFF_DC_H_TOT (0x000)
255#define SM501_OFF_DC_V_TOT (0x008)
256#define SM501_OFF_DC_H_SYNC (0x004)
257#define SM501_OFF_DC_V_SYNC (0x00C)
258
259#define SM501_DC_PANEL_CONTROL (0x000)
260
261#define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
262#define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
263#define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
264#define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
265#define SM501_DC_PANEL_CONTROL_DP (1 << 23)
266
267#define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
268#define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
269#define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
270
271#define SM501_DC_PANEL_CONTROL_DE (1 << 20)
272
273#define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
274#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
275#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
276
277#define SM501_DC_PANEL_CONTROL_CP (1 << 14)
278#define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
279#define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
280#define SM501_DC_PANEL_CONTROL_CK (1 << 9)
281#define SM501_DC_PANEL_CONTROL_TE (1 << 8)
282#define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
283#define SM501_DC_PANEL_CONTROL_VP (1 << 6)
284#define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
285#define SM501_DC_PANEL_CONTROL_HP (1 << 4)
286#define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
287#define SM501_DC_PANEL_CONTROL_EN (1 << 2)
288
289#define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
290#define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
291#define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
292
293
294#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
295#define SM501_DC_PANEL_COLOR_KEY (0x008)
296#define SM501_DC_PANEL_FB_ADDR (0x00C)
297#define SM501_DC_PANEL_FB_OFFSET (0x010)
298#define SM501_DC_PANEL_FB_WIDTH (0x014)
299#define SM501_DC_PANEL_FB_HEIGHT (0x018)
300#define SM501_DC_PANEL_TL_LOC (0x01C)
301#define SM501_DC_PANEL_BR_LOC (0x020)
302#define SM501_DC_PANEL_H_TOT (0x024)
303#define SM501_DC_PANEL_H_SYNC (0x028)
304#define SM501_DC_PANEL_V_TOT (0x02C)
305#define SM501_DC_PANEL_V_SYNC (0x030)
306#define SM501_DC_PANEL_CUR_LINE (0x034)
307
308#define SM501_DC_VIDEO_CONTROL (0x040)
309#define SM501_DC_VIDEO_FB0_ADDR (0x044)
310#define SM501_DC_VIDEO_FB_WIDTH (0x048)
311#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
312#define SM501_DC_VIDEO_TL_LOC (0x050)
313#define SM501_DC_VIDEO_BR_LOC (0x054)
314#define SM501_DC_VIDEO_SCALE (0x058)
315#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
316#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
317#define SM501_DC_VIDEO_FB1_ADDR (0x064)
318#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
319
320#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
321#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
322#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
323#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
324#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
325#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
326#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
327#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
328#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
329#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
330
331#define SM501_DC_PANEL_HWC_BASE (0x0F0)
332#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
333#define SM501_DC_PANEL_HWC_LOC (0x0F4)
334#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
335#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
336
337#define SM501_HWC_EN (1 << 31)
338
339#define SM501_OFF_HWC_ADDR (0x00)
340#define SM501_OFF_HWC_LOC (0x04)
341#define SM501_OFF_HWC_COLOR_1_2 (0x08)
342#define SM501_OFF_HWC_COLOR_3 (0x0C)
343
344#define SM501_DC_ALPHA_CONTROL (0x100)
345#define SM501_DC_ALPHA_FB_ADDR (0x104)
346#define SM501_DC_ALPHA_FB_OFFSET (0x108)
347#define SM501_DC_ALPHA_TL_LOC (0x10C)
348#define SM501_DC_ALPHA_BR_LOC (0x110)
349#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
350#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
351
352#define SM501_DC_CRT_CONTROL (0x200)
353
354#define SM501_DC_CRT_CONTROL_TVP (1 << 15)
355#define SM501_DC_CRT_CONTROL_CP (1 << 14)
356#define SM501_DC_CRT_CONTROL_VSP (1 << 13)
357#define SM501_DC_CRT_CONTROL_HSP (1 << 12)
358#define SM501_DC_CRT_CONTROL_VS (1 << 11)
359#define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
360#define SM501_DC_CRT_CONTROL_SEL (1 << 9)
361#define SM501_DC_CRT_CONTROL_TE (1 << 8)
362#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
363#define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
364#define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
365
366#define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
367#define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
368#define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
369
370#define SM501_DC_CRT_FB_ADDR (0x204)
371#define SM501_DC_CRT_FB_OFFSET (0x208)
372#define SM501_DC_CRT_H_TOT (0x20C)
373#define SM501_DC_CRT_H_SYNC (0x210)
374#define SM501_DC_CRT_V_TOT (0x214)
375#define SM501_DC_CRT_V_SYNC (0x218)
376#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
377#define SM501_DC_CRT_CUR_LINE (0x220)
378#define SM501_DC_CRT_MONITOR_DETECT (0x224)
379
380#define SM501_DC_CRT_HWC_BASE (0x230)
381#define SM501_DC_CRT_HWC_ADDR (0x230)
382#define SM501_DC_CRT_HWC_LOC (0x234)
383#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
384#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
385
386#define SM501_DC_PANEL_PALETTE (0x400)
387
388#define SM501_DC_VIDEO_PALETTE (0x800)
389
390#define SM501_DC_CRT_PALETTE (0xC00)
391
392
393#define SM501_ZVPORT (0x090000)
394
395
396#define SM501_AC97 (0x0A0000)
397
398
399#define SM501_UCONTROLLER (0x0B0000)
400
401
402#define SM501_UCONTROLLER_SRAM (0x0C0000)
403
404
405#define SM501_DMA (0x0D0000)
406
407
408#define SM501_2D_ENGINE (0x100000)
409#define SM501_2D_SOURCE (0x00)
410#define SM501_2D_DESTINATION (0x04)
411#define SM501_2D_DIMENSION (0x08)
412#define SM501_2D_CONTROL (0x0C)
413#define SM501_2D_PITCH (0x10)
414#define SM501_2D_FOREGROUND (0x14)
415#define SM501_2D_BACKGROUND (0x18)
416#define SM501_2D_STRETCH (0x1C)
417#define SM501_2D_COLOR_COMPARE (0x20)
418#define SM501_2D_COLOR_COMPARE_MASK (0x24)
419#define SM501_2D_MASK (0x28)
420#define SM501_2D_CLIP_TL (0x2C)
421#define SM501_2D_CLIP_BR (0x30)
422#define SM501_2D_MONO_PATTERN_LOW (0x34)
423#define SM501_2D_MONO_PATTERN_HIGH (0x38)
424#define SM501_2D_WINDOW_WIDTH (0x3C)
425#define SM501_2D_SOURCE_BASE (0x40)
426#define SM501_2D_DESTINATION_BASE (0x44)
427#define SM501_2D_ALPHA (0x48)
428#define SM501_2D_WRAP (0x4C)
429#define SM501_2D_STATUS (0x50)
430
431#define SM501_CSC_Y_SOURCE_BASE (0xC8)
432#define SM501_CSC_CONSTANTS (0xCC)
433#define SM501_CSC_Y_SOURCE_X (0xD0)
434#define SM501_CSC_Y_SOURCE_Y (0xD4)
435#define SM501_CSC_U_SOURCE_BASE (0xD8)
436#define SM501_CSC_V_SOURCE_BASE (0xDC)
437#define SM501_CSC_SOURCE_DIMENSION (0xE0)
438#define SM501_CSC_SOURCE_PITCH (0xE4)
439#define SM501_CSC_DESTINATION (0xE8)
440#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
441#define SM501_CSC_DESTINATION_PITCH (0xF0)
442#define SM501_CSC_SCALE_FACTOR (0xF4)
443#define SM501_CSC_DESTINATION_BASE (0xF8)
444#define SM501_CSC_CONTROL (0xFC)
445
446
447#define SM501_2D_ENGINE_DATA (0x110000)
448
449
450
451#define SM501_HWC_WIDTH (64)
452#define SM501_HWC_HEIGHT (64)
453
454
455static const uint32_t sm501_mem_local_size[] = {
456 [0] = 4 * M_BYTE,
457 [1] = 8 * M_BYTE,
458 [2] = 16 * M_BYTE,
459 [3] = 32 * M_BYTE,
460 [4] = 64 * M_BYTE,
461 [5] = 2 * M_BYTE,
462};
463#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
464
465typedef struct SM501State {
466
467 QemuConsole *con;
468
469
470 uint32_t local_mem_size_index;
471 uint8_t *local_mem;
472 MemoryRegion local_mem_region;
473 MemoryRegion mmio_region;
474 MemoryRegion system_config_region;
475 MemoryRegion disp_ctrl_region;
476 MemoryRegion twoD_engine_region;
477 uint32_t last_width;
478 uint32_t last_height;
479
480
481 uint32_t system_control;
482 uint32_t misc_control;
483 uint32_t gpio_31_0_control;
484 uint32_t gpio_63_32_control;
485 uint32_t dram_control;
486 uint32_t arbitration_control;
487 uint32_t irq_mask;
488 uint32_t misc_timing;
489 uint32_t power_mode_control;
490
491 uint32_t uart0_ier;
492 uint32_t uart0_lcr;
493 uint32_t uart0_mcr;
494 uint32_t uart0_scr;
495
496 uint8_t dc_palette[DC_PALETTE_ENTRIES];
497
498 uint32_t dc_panel_control;
499 uint32_t dc_panel_panning_control;
500 uint32_t dc_panel_fb_addr;
501 uint32_t dc_panel_fb_offset;
502 uint32_t dc_panel_fb_width;
503 uint32_t dc_panel_fb_height;
504 uint32_t dc_panel_tl_location;
505 uint32_t dc_panel_br_location;
506 uint32_t dc_panel_h_total;
507 uint32_t dc_panel_h_sync;
508 uint32_t dc_panel_v_total;
509 uint32_t dc_panel_v_sync;
510
511 uint32_t dc_panel_hwc_addr;
512 uint32_t dc_panel_hwc_location;
513 uint32_t dc_panel_hwc_color_1_2;
514 uint32_t dc_panel_hwc_color_3;
515
516 uint32_t dc_video_control;
517
518 uint32_t dc_crt_control;
519 uint32_t dc_crt_fb_addr;
520 uint32_t dc_crt_fb_offset;
521 uint32_t dc_crt_h_total;
522 uint32_t dc_crt_h_sync;
523 uint32_t dc_crt_v_total;
524 uint32_t dc_crt_v_sync;
525
526 uint32_t dc_crt_hwc_addr;
527 uint32_t dc_crt_hwc_location;
528 uint32_t dc_crt_hwc_color_1_2;
529 uint32_t dc_crt_hwc_color_3;
530
531 uint32_t twoD_source;
532 uint32_t twoD_destination;
533 uint32_t twoD_dimension;
534 uint32_t twoD_control;
535 uint32_t twoD_pitch;
536 uint32_t twoD_foreground;
537 uint32_t twoD_background;
538 uint32_t twoD_stretch;
539 uint32_t twoD_color_compare;
540 uint32_t twoD_color_compare_mask;
541 uint32_t twoD_mask;
542 uint32_t twoD_clip_tl;
543 uint32_t twoD_clip_br;
544 uint32_t twoD_mono_pattern_low;
545 uint32_t twoD_mono_pattern_high;
546 uint32_t twoD_window_width;
547 uint32_t twoD_source_base;
548 uint32_t twoD_destination_base;
549 uint32_t twoD_alpha;
550 uint32_t twoD_wrap;
551} SM501State;
552
553static uint32_t get_local_mem_size_index(uint32_t size)
554{
555 uint32_t norm_size = 0;
556 int i, index = 0;
557
558 for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) {
559 uint32_t new_size = sm501_mem_local_size[i];
560 if (new_size >= size) {
561 if (norm_size == 0 || norm_size > new_size) {
562 norm_size = new_size;
563 index = i;
564 }
565 }
566 }
567
568 return index;
569}
570
571static inline int get_width(SM501State *s, int crt)
572{
573 int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total;
574 return (width & 0x00000FFF) + 1;
575}
576
577static inline int get_height(SM501State *s, int crt)
578{
579 int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total;
580 return (height & 0x00000FFF) + 1;
581}
582
583static inline int get_bpp(SM501State *s, int crt)
584{
585 int bpp = crt ? s->dc_crt_control : s->dc_panel_control;
586 return 1 << (bpp & 3);
587}
588
589
590
591
592
593static inline int is_hwc_enabled(SM501State *state, int crt)
594{
595 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
596 return addr & SM501_HWC_EN;
597}
598
599
600
601
602
603static inline uint8_t *get_hwc_address(SM501State *state, int crt)
604{
605 uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
606 return state->local_mem + (addr & 0x03FFFFF0);
607}
608
609
610
611
612
613static inline uint32_t get_hwc_y(SM501State *state, int crt)
614{
615 uint32_t location = crt ? state->dc_crt_hwc_location
616 : state->dc_panel_hwc_location;
617 return (location & 0x07FF0000) >> 16;
618}
619
620
621
622
623
624static inline uint32_t get_hwc_x(SM501State *state, int crt)
625{
626 uint32_t location = crt ? state->dc_crt_hwc_location
627 : state->dc_panel_hwc_location;
628 return location & 0x000007FF;
629}
630
631
632
633
634
635
636static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette)
637{
638 int i;
639 uint32_t color_reg;
640 uint16_t rgb565;
641
642 for (i = 0; i < 3; i++) {
643 if (i + 1 == 3) {
644 color_reg = crt ? state->dc_crt_hwc_color_3
645 : state->dc_panel_hwc_color_3;
646 } else {
647 color_reg = crt ? state->dc_crt_hwc_color_1_2
648 : state->dc_panel_hwc_color_1_2;
649 }
650
651 if (i + 1 == 2) {
652 rgb565 = (color_reg >> 16) & 0xFFFF;
653 } else {
654 rgb565 = color_reg & 0xFFFF;
655 }
656 palette[i * 3 + 0] = (rgb565 << 3) & 0xf8;
657 palette[i * 3 + 1] = (rgb565 >> 3) & 0xfc;
658 palette[i * 3 + 2] = (rgb565 >> 8) & 0xf8;
659 }
660}
661
662static inline void hwc_invalidate(SM501State *s, int crt)
663{
664 int w = get_width(s, crt);
665 int h = get_height(s, crt);
666 int bpp = get_bpp(s, crt);
667 int start = get_hwc_y(s, crt);
668 int end = MIN(h, start + SM501_HWC_HEIGHT) + 1;
669
670 start *= w * bpp;
671 end *= w * bpp;
672
673 memory_region_set_dirty(&s->local_mem_region, start, end - start);
674}
675
676static void sm501_2d_operation(SM501State *s)
677{
678
679 int operation = (s->twoD_control >> 16) & 0x1f;
680 int rtl = s->twoD_control & 0x8000000;
681 int src_x = (s->twoD_source >> 16) & 0x01FFF;
682 int src_y = s->twoD_source & 0xFFFF;
683 int dst_x = (s->twoD_destination >> 16) & 0x01FFF;
684 int dst_y = s->twoD_destination & 0xFFFF;
685 int operation_width = (s->twoD_dimension >> 16) & 0x1FFF;
686 int operation_height = s->twoD_dimension & 0xFFFF;
687 uint32_t color = s->twoD_foreground;
688 int format_flags = (s->twoD_stretch >> 20) & 0x3;
689 int addressing = (s->twoD_stretch >> 16) & 0xF;
690
691
692 uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
693 uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
694 int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
695 int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
696
697 if (addressing != 0x0) {
698 printf("%s: only XY addressing is supported.\n", __func__);
699 abort();
700 }
701
702 if ((s->twoD_source_base & 0x08000000) ||
703 (s->twoD_destination_base & 0x08000000)) {
704 printf("%s: only local memory is supported.\n", __func__);
705 abort();
706 }
707
708 switch (operation) {
709 case 0x00:
710#define COPY_AREA(_bpp, _pixel_type, rtl) { \
711 int y, x, index_d, index_s; \
712 for (y = 0; y < operation_height; y++) { \
713 for (x = 0; x < operation_width; x++) { \
714 if (rtl) { \
715 index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
716 index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
717 } else { \
718 index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
719 index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
720 } \
721 *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\
722 } \
723 } \
724 }
725 switch (format_flags) {
726 case 0:
727 COPY_AREA(1, uint8_t, rtl);
728 break;
729 case 1:
730 COPY_AREA(2, uint16_t, rtl);
731 break;
732 case 2:
733 COPY_AREA(4, uint32_t, rtl);
734 break;
735 }
736 break;
737
738 case 0x01:
739#define FILL_RECT(_bpp, _pixel_type) { \
740 int y, x; \
741 for (y = 0; y < operation_height; y++) { \
742 for (x = 0; x < operation_width; x++) { \
743 int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
744 *(_pixel_type *)&dst[index] = (_pixel_type)color; \
745 } \
746 } \
747 }
748
749 switch (format_flags) {
750 case 0:
751 FILL_RECT(1, uint8_t);
752 break;
753 case 1:
754 FILL_RECT(2, uint16_t);
755 break;
756 case 2:
757 FILL_RECT(4, uint32_t);
758 break;
759 }
760 break;
761
762 default:
763 printf("non-implemented SM501 2D operation. %d\n", operation);
764 abort();
765 break;
766 }
767}
768
769static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
770 unsigned size)
771{
772 SM501State *s = (SM501State *)opaque;
773 uint32_t ret = 0;
774 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
775
776 switch (addr) {
777 case SM501_SYSTEM_CONTROL:
778 ret = s->system_control;
779 break;
780 case SM501_MISC_CONTROL:
781 ret = s->misc_control;
782 break;
783 case SM501_GPIO31_0_CONTROL:
784 ret = s->gpio_31_0_control;
785 break;
786 case SM501_GPIO63_32_CONTROL:
787 ret = s->gpio_63_32_control;
788 break;
789 case SM501_DEVICEID:
790 ret = 0x050100A0;
791 break;
792 case SM501_DRAM_CONTROL:
793 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
794 break;
795 case SM501_ARBTRTN_CONTROL:
796 ret = s->arbitration_control;
797 break;
798 case SM501_COMMAND_LIST_STATUS:
799 ret = 0x00180002;
800 break;
801 case SM501_IRQ_MASK:
802 ret = s->irq_mask;
803 break;
804 case SM501_MISC_TIMING:
805
806 ret = s->misc_timing;
807 break;
808 case SM501_CURRENT_GATE:
809
810 ret = 0x00021807;
811 break;
812 case SM501_CURRENT_CLOCK:
813 ret = 0x2A1A0A09;
814 break;
815 case SM501_POWER_MODE_CONTROL:
816 ret = s->power_mode_control;
817 break;
818 case SM501_ENDIAN_CONTROL:
819 ret = 0;
820 break;
821
822 default:
823 printf("sm501 system config : not implemented register read."
824 " addr=%x\n", (int)addr);
825 abort();
826 }
827
828 return ret;
829}
830
831static void sm501_system_config_write(void *opaque, hwaddr addr,
832 uint64_t value, unsigned size)
833{
834 SM501State *s = (SM501State *)opaque;
835 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
836 (uint32_t)addr, (uint32_t)value);
837
838 switch (addr) {
839 case SM501_SYSTEM_CONTROL:
840 s->system_control = value & 0xE300B8F7;
841 break;
842 case SM501_MISC_CONTROL:
843 s->misc_control = value & 0xFF7FFF20;
844 break;
845 case SM501_GPIO31_0_CONTROL:
846 s->gpio_31_0_control = value;
847 break;
848 case SM501_GPIO63_32_CONTROL:
849 s->gpio_63_32_control = value;
850 break;
851 case SM501_DRAM_CONTROL:
852 s->local_mem_size_index = (value >> 13) & 0x7;
853
854 s->dram_control |= value & 0x7FFFFFC3;
855 break;
856 case SM501_ARBTRTN_CONTROL:
857 s->arbitration_control = value & 0x37777777;
858 break;
859 case SM501_IRQ_MASK:
860 s->irq_mask = value;
861 break;
862 case SM501_MISC_TIMING:
863 s->misc_timing = value & 0xF31F1FFF;
864 break;
865 case SM501_POWER_MODE_0_GATE:
866 case SM501_POWER_MODE_1_GATE:
867 case SM501_POWER_MODE_0_CLOCK:
868 case SM501_POWER_MODE_1_CLOCK:
869
870 break;
871 case SM501_POWER_MODE_CONTROL:
872 s->power_mode_control = value & 0x00000003;
873 break;
874 case SM501_ENDIAN_CONTROL:
875 if (value & 0x00000001) {
876 printf("sm501 system config : big endian mode not implemented.\n");
877 abort();
878 }
879 break;
880
881 default:
882 printf("sm501 system config : not implemented register write."
883 " addr=%x, val=%x\n", (int)addr, (uint32_t)value);
884 abort();
885 }
886}
887
888static const MemoryRegionOps sm501_system_config_ops = {
889 .read = sm501_system_config_read,
890 .write = sm501_system_config_write,
891 .valid = {
892 .min_access_size = 4,
893 .max_access_size = 4,
894 },
895 .endianness = DEVICE_LITTLE_ENDIAN,
896};
897
898static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
899{
900 SM501State *s = (SM501State *)opaque;
901 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
902
903
904
905
906 assert(range_covers_byte(0, 0x400 * 3, addr));
907 return *(uint32_t *)&s->dc_palette[addr];
908}
909
910static void sm501_palette_write(void *opaque, hwaddr addr,
911 uint32_t value)
912{
913 SM501State *s = (SM501State *)opaque;
914 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
915 (int)addr, value);
916
917
918
919
920 assert(range_covers_byte(0, 0x400 * 3, addr));
921 *(uint32_t *)&s->dc_palette[addr] = value;
922}
923
924static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
925 unsigned size)
926{
927 SM501State *s = (SM501State *)opaque;
928 uint32_t ret = 0;
929 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
930
931 switch (addr) {
932
933 case SM501_DC_PANEL_CONTROL:
934 ret = s->dc_panel_control;
935 break;
936 case SM501_DC_PANEL_PANNING_CONTROL:
937 ret = s->dc_panel_panning_control;
938 break;
939 case SM501_DC_PANEL_COLOR_KEY:
940
941 break;
942 case SM501_DC_PANEL_FB_ADDR:
943 ret = s->dc_panel_fb_addr;
944 break;
945 case SM501_DC_PANEL_FB_OFFSET:
946 ret = s->dc_panel_fb_offset;
947 break;
948 case SM501_DC_PANEL_FB_WIDTH:
949 ret = s->dc_panel_fb_width;
950 break;
951 case SM501_DC_PANEL_FB_HEIGHT:
952 ret = s->dc_panel_fb_height;
953 break;
954 case SM501_DC_PANEL_TL_LOC:
955 ret = s->dc_panel_tl_location;
956 break;
957 case SM501_DC_PANEL_BR_LOC:
958 ret = s->dc_panel_br_location;
959 break;
960
961 case SM501_DC_PANEL_H_TOT:
962 ret = s->dc_panel_h_total;
963 break;
964 case SM501_DC_PANEL_H_SYNC:
965 ret = s->dc_panel_h_sync;
966 break;
967 case SM501_DC_PANEL_V_TOT:
968 ret = s->dc_panel_v_total;
969 break;
970 case SM501_DC_PANEL_V_SYNC:
971 ret = s->dc_panel_v_sync;
972 break;
973
974 case SM501_DC_PANEL_HWC_ADDR:
975 ret = s->dc_panel_hwc_addr;
976 break;
977 case SM501_DC_PANEL_HWC_LOC:
978 ret = s->dc_panel_hwc_location;
979 break;
980 case SM501_DC_PANEL_HWC_COLOR_1_2:
981 ret = s->dc_panel_hwc_color_1_2;
982 break;
983 case SM501_DC_PANEL_HWC_COLOR_3:
984 ret = s->dc_panel_hwc_color_3;
985 break;
986
987 case SM501_DC_VIDEO_CONTROL:
988 ret = s->dc_video_control;
989 break;
990
991 case SM501_DC_CRT_CONTROL:
992 ret = s->dc_crt_control;
993 break;
994 case SM501_DC_CRT_FB_ADDR:
995 ret = s->dc_crt_fb_addr;
996 break;
997 case SM501_DC_CRT_FB_OFFSET:
998 ret = s->dc_crt_fb_offset;
999 break;
1000 case SM501_DC_CRT_H_TOT:
1001 ret = s->dc_crt_h_total;
1002 break;
1003 case SM501_DC_CRT_H_SYNC:
1004 ret = s->dc_crt_h_sync;
1005 break;
1006 case SM501_DC_CRT_V_TOT:
1007 ret = s->dc_crt_v_total;
1008 break;
1009 case SM501_DC_CRT_V_SYNC:
1010 ret = s->dc_crt_v_sync;
1011 break;
1012
1013 case SM501_DC_CRT_HWC_ADDR:
1014 ret = s->dc_crt_hwc_addr;
1015 break;
1016 case SM501_DC_CRT_HWC_LOC:
1017 ret = s->dc_crt_hwc_location;
1018 break;
1019 case SM501_DC_CRT_HWC_COLOR_1_2:
1020 ret = s->dc_crt_hwc_color_1_2;
1021 break;
1022 case SM501_DC_CRT_HWC_COLOR_3:
1023 ret = s->dc_crt_hwc_color_3;
1024 break;
1025
1026 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1027 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
1028 break;
1029
1030 default:
1031 printf("sm501 disp ctrl : not implemented register read."
1032 " addr=%x\n", (int)addr);
1033 abort();
1034 }
1035
1036 return ret;
1037}
1038
1039static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
1040 uint64_t value, unsigned size)
1041{
1042 SM501State *s = (SM501State *)opaque;
1043 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
1044 (unsigned)addr, (unsigned)value);
1045
1046 switch (addr) {
1047 case SM501_DC_PANEL_CONTROL:
1048 s->dc_panel_control = value & 0x0FFF73FF;
1049 break;
1050 case SM501_DC_PANEL_PANNING_CONTROL:
1051 s->dc_panel_panning_control = value & 0xFF3FFF3F;
1052 break;
1053 case SM501_DC_PANEL_COLOR_KEY:
1054
1055 break;
1056 case SM501_DC_PANEL_FB_ADDR:
1057 s->dc_panel_fb_addr = value & 0x8FFFFFF0;
1058 break;
1059 case SM501_DC_PANEL_FB_OFFSET:
1060 s->dc_panel_fb_offset = value & 0x3FF03FF0;
1061 break;
1062 case SM501_DC_PANEL_FB_WIDTH:
1063 s->dc_panel_fb_width = value & 0x0FFF0FFF;
1064 break;
1065 case SM501_DC_PANEL_FB_HEIGHT:
1066 s->dc_panel_fb_height = value & 0x0FFF0FFF;
1067 break;
1068 case SM501_DC_PANEL_TL_LOC:
1069 s->dc_panel_tl_location = value & 0x07FF07FF;
1070 break;
1071 case SM501_DC_PANEL_BR_LOC:
1072 s->dc_panel_br_location = value & 0x07FF07FF;
1073 break;
1074
1075 case SM501_DC_PANEL_H_TOT:
1076 s->dc_panel_h_total = value & 0x0FFF0FFF;
1077 break;
1078 case SM501_DC_PANEL_H_SYNC:
1079 s->dc_panel_h_sync = value & 0x00FF0FFF;
1080 break;
1081 case SM501_DC_PANEL_V_TOT:
1082 s->dc_panel_v_total = value & 0x0FFF0FFF;
1083 break;
1084 case SM501_DC_PANEL_V_SYNC:
1085 s->dc_panel_v_sync = value & 0x003F0FFF;
1086 break;
1087
1088 case SM501_DC_PANEL_HWC_ADDR:
1089 value &= 0x8FFFFFF0;
1090 if (value != s->dc_panel_hwc_addr) {
1091 hwc_invalidate(s, 0);
1092 s->dc_panel_hwc_addr = value;
1093 }
1094 break;
1095 case SM501_DC_PANEL_HWC_LOC:
1096 value &= 0x0FFF0FFF;
1097 if (value != s->dc_panel_hwc_location) {
1098 hwc_invalidate(s, 0);
1099 s->dc_panel_hwc_location = value;
1100 }
1101 break;
1102 case SM501_DC_PANEL_HWC_COLOR_1_2:
1103 s->dc_panel_hwc_color_1_2 = value;
1104 break;
1105 case SM501_DC_PANEL_HWC_COLOR_3:
1106 s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
1107 break;
1108
1109 case SM501_DC_VIDEO_CONTROL:
1110 s->dc_video_control = value & 0x00037FFF;
1111 break;
1112
1113 case SM501_DC_CRT_CONTROL:
1114 s->dc_crt_control = value & 0x0003FFFF;
1115 break;
1116 case SM501_DC_CRT_FB_ADDR:
1117 s->dc_crt_fb_addr = value & 0x8FFFFFF0;
1118 break;
1119 case SM501_DC_CRT_FB_OFFSET:
1120 s->dc_crt_fb_offset = value & 0x3FF03FF0;
1121 break;
1122 case SM501_DC_CRT_H_TOT:
1123 s->dc_crt_h_total = value & 0x0FFF0FFF;
1124 break;
1125 case SM501_DC_CRT_H_SYNC:
1126 s->dc_crt_h_sync = value & 0x00FF0FFF;
1127 break;
1128 case SM501_DC_CRT_V_TOT:
1129 s->dc_crt_v_total = value & 0x0FFF0FFF;
1130 break;
1131 case SM501_DC_CRT_V_SYNC:
1132 s->dc_crt_v_sync = value & 0x003F0FFF;
1133 break;
1134
1135 case SM501_DC_CRT_HWC_ADDR:
1136 value &= 0x8FFFFFF0;
1137 if (value != s->dc_crt_hwc_addr) {
1138 hwc_invalidate(s, 1);
1139 s->dc_crt_hwc_addr = value;
1140 }
1141 break;
1142 case SM501_DC_CRT_HWC_LOC:
1143 value &= 0x0FFF0FFF;
1144 if (value != s->dc_crt_hwc_location) {
1145 hwc_invalidate(s, 1);
1146 s->dc_crt_hwc_location = value;
1147 }
1148 break;
1149 case SM501_DC_CRT_HWC_COLOR_1_2:
1150 s->dc_crt_hwc_color_1_2 = value;
1151 break;
1152 case SM501_DC_CRT_HWC_COLOR_3:
1153 s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
1154 break;
1155
1156 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
1157 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
1158 break;
1159
1160 default:
1161 printf("sm501 disp ctrl : not implemented register write."
1162 " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1163 abort();
1164 }
1165}
1166
1167static const MemoryRegionOps sm501_disp_ctrl_ops = {
1168 .read = sm501_disp_ctrl_read,
1169 .write = sm501_disp_ctrl_write,
1170 .valid = {
1171 .min_access_size = 4,
1172 .max_access_size = 4,
1173 },
1174 .endianness = DEVICE_LITTLE_ENDIAN,
1175};
1176
1177static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
1178 unsigned size)
1179{
1180 SM501State *s = (SM501State *)opaque;
1181 uint32_t ret = 0;
1182 SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr);
1183
1184 switch (addr) {
1185 case SM501_2D_SOURCE:
1186 ret = s->twoD_source;
1187 break;
1188 case SM501_2D_DESTINATION:
1189 ret = s->twoD_destination;
1190 break;
1191 case SM501_2D_DIMENSION:
1192 ret = s->twoD_dimension;
1193 break;
1194 case SM501_2D_CONTROL:
1195 ret = s->twoD_control;
1196 break;
1197 case SM501_2D_PITCH:
1198 ret = s->twoD_pitch;
1199 break;
1200 case SM501_2D_FOREGROUND:
1201 ret = s->twoD_foreground;
1202 break;
1203 case SM501_2D_BACKGROUND:
1204 ret = s->twoD_background;
1205 break;
1206 case SM501_2D_STRETCH:
1207 ret = s->twoD_stretch;
1208 break;
1209 case SM501_2D_COLOR_COMPARE:
1210 ret = s->twoD_color_compare;
1211 break;
1212 case SM501_2D_COLOR_COMPARE_MASK:
1213 ret = s->twoD_color_compare_mask;
1214 break;
1215 case SM501_2D_MASK:
1216 ret = s->twoD_mask;
1217 break;
1218 case SM501_2D_CLIP_TL:
1219 ret = s->twoD_clip_tl;
1220 break;
1221 case SM501_2D_CLIP_BR:
1222 ret = s->twoD_clip_br;
1223 break;
1224 case SM501_2D_MONO_PATTERN_LOW:
1225 ret = s->twoD_mono_pattern_low;
1226 break;
1227 case SM501_2D_MONO_PATTERN_HIGH:
1228 ret = s->twoD_mono_pattern_high;
1229 break;
1230 case SM501_2D_WINDOW_WIDTH:
1231 ret = s->twoD_window_width;
1232 break;
1233 case SM501_2D_SOURCE_BASE:
1234 ret = s->twoD_source_base;
1235 break;
1236 case SM501_2D_DESTINATION_BASE:
1237 ret = s->twoD_destination_base;
1238 break;
1239 case SM501_2D_ALPHA:
1240 ret = s->twoD_alpha;
1241 break;
1242 case SM501_2D_WRAP:
1243 ret = s->twoD_wrap;
1244 break;
1245 case SM501_2D_STATUS:
1246 ret = 0;
1247 break;
1248 default:
1249 printf("sm501 disp ctrl : not implemented register read."
1250 " addr=%x\n", (int)addr);
1251 abort();
1252 }
1253
1254 return ret;
1255}
1256
1257static void sm501_2d_engine_write(void *opaque, hwaddr addr,
1258 uint64_t value, unsigned size)
1259{
1260 SM501State *s = (SM501State *)opaque;
1261 SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
1262 (unsigned)addr, (unsigned)value);
1263
1264 switch (addr) {
1265 case SM501_2D_SOURCE:
1266 s->twoD_source = value;
1267 break;
1268 case SM501_2D_DESTINATION:
1269 s->twoD_destination = value;
1270 break;
1271 case SM501_2D_DIMENSION:
1272 s->twoD_dimension = value;
1273 break;
1274 case SM501_2D_CONTROL:
1275 s->twoD_control = value;
1276
1277
1278 if (value & 0x80000000) {
1279 sm501_2d_operation(s);
1280 s->twoD_control &= ~0x80000000;
1281 }
1282
1283 break;
1284 case SM501_2D_PITCH:
1285 s->twoD_pitch = value;
1286 break;
1287 case SM501_2D_FOREGROUND:
1288 s->twoD_foreground = value;
1289 break;
1290 case SM501_2D_BACKGROUND:
1291 s->twoD_background = value;
1292 break;
1293 case SM501_2D_STRETCH:
1294 s->twoD_stretch = value;
1295 break;
1296 case SM501_2D_COLOR_COMPARE:
1297 s->twoD_color_compare = value;
1298 break;
1299 case SM501_2D_COLOR_COMPARE_MASK:
1300 s->twoD_color_compare_mask = value;
1301 break;
1302 case SM501_2D_MASK:
1303 s->twoD_mask = value;
1304 break;
1305 case SM501_2D_CLIP_TL:
1306 s->twoD_clip_tl = value;
1307 break;
1308 case SM501_2D_CLIP_BR:
1309 s->twoD_clip_br = value;
1310 break;
1311 case SM501_2D_MONO_PATTERN_LOW:
1312 s->twoD_mono_pattern_low = value;
1313 break;
1314 case SM501_2D_MONO_PATTERN_HIGH:
1315 s->twoD_mono_pattern_high = value;
1316 break;
1317 case SM501_2D_WINDOW_WIDTH:
1318 s->twoD_window_width = value;
1319 break;
1320 case SM501_2D_SOURCE_BASE:
1321 s->twoD_source_base = value;
1322 break;
1323 case SM501_2D_DESTINATION_BASE:
1324 s->twoD_destination_base = value;
1325 break;
1326 case SM501_2D_ALPHA:
1327 s->twoD_alpha = value;
1328 break;
1329 case SM501_2D_WRAP:
1330 s->twoD_wrap = value;
1331 break;
1332 case SM501_2D_STATUS:
1333
1334 break;
1335 default:
1336 printf("sm501 2d engine : not implemented register write."
1337 " addr=%x, val=%x\n", (int)addr, (unsigned)value);
1338 abort();
1339 }
1340}
1341
1342static const MemoryRegionOps sm501_2d_engine_ops = {
1343 .read = sm501_2d_engine_read,
1344 .write = sm501_2d_engine_write,
1345 .valid = {
1346 .min_access_size = 4,
1347 .max_access_size = 4,
1348 },
1349 .endianness = DEVICE_LITTLE_ENDIAN,
1350};
1351
1352
1353
1354typedef void draw_line_func(uint8_t *d, const uint8_t *s,
1355 int width, const uint32_t *pal);
1356
1357typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s,
1358 int width, const uint8_t *palette,
1359 int c_x, int c_y);
1360
1361#define DEPTH 8
1362#include "sm501_template.h"
1363
1364#define DEPTH 15
1365#include "sm501_template.h"
1366
1367#define BGR_FORMAT
1368#define DEPTH 15
1369#include "sm501_template.h"
1370
1371#define DEPTH 16
1372#include "sm501_template.h"
1373
1374#define BGR_FORMAT
1375#define DEPTH 16
1376#include "sm501_template.h"
1377
1378#define DEPTH 32
1379#include "sm501_template.h"
1380
1381#define BGR_FORMAT
1382#define DEPTH 32
1383#include "sm501_template.h"
1384
1385static draw_line_func *draw_line8_funcs[] = {
1386 draw_line8_8,
1387 draw_line8_15,
1388 draw_line8_16,
1389 draw_line8_32,
1390 draw_line8_32bgr,
1391 draw_line8_15bgr,
1392 draw_line8_16bgr,
1393};
1394
1395static draw_line_func *draw_line16_funcs[] = {
1396 draw_line16_8,
1397 draw_line16_15,
1398 draw_line16_16,
1399 draw_line16_32,
1400 draw_line16_32bgr,
1401 draw_line16_15bgr,
1402 draw_line16_16bgr,
1403};
1404
1405static draw_line_func *draw_line32_funcs[] = {
1406 draw_line32_8,
1407 draw_line32_15,
1408 draw_line32_16,
1409 draw_line32_32,
1410 draw_line32_32bgr,
1411 draw_line32_15bgr,
1412 draw_line32_16bgr,
1413};
1414
1415static draw_hwc_line_func *draw_hwc_line_funcs[] = {
1416 draw_hwc_line_8,
1417 draw_hwc_line_15,
1418 draw_hwc_line_16,
1419 draw_hwc_line_32,
1420 draw_hwc_line_32bgr,
1421 draw_hwc_line_15bgr,
1422 draw_hwc_line_16bgr,
1423};
1424
1425static inline int get_depth_index(DisplaySurface *surface)
1426{
1427 switch (surface_bits_per_pixel(surface)) {
1428 default:
1429 case 8:
1430 return 0;
1431 case 15:
1432 return 1;
1433 case 16:
1434 return 2;
1435 case 32:
1436 if (is_surface_bgr(surface)) {
1437 return 4;
1438 } else {
1439 return 3;
1440 }
1441 }
1442}
1443
1444static void sm501_update_display(void *opaque)
1445{
1446 SM501State *s = (SM501State *)opaque;
1447 DisplaySurface *surface = qemu_console_surface(s->con);
1448 DirtyBitmapSnapshot *snap;
1449 int y, c_x = 0, c_y = 0;
1450 int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
1451 int width = get_width(s, crt);
1452 int height = get_height(s, crt);
1453 int src_bpp = get_bpp(s, crt);
1454 int dst_bpp = surface_bytes_per_pixel(surface);
1455 int dst_depth_index = get_depth_index(surface);
1456 draw_line_func *draw_line = NULL;
1457 draw_hwc_line_func *draw_hwc_line = NULL;
1458 int full_update = 0;
1459 int y_start = -1;
1460 ram_addr_t offset = 0;
1461 uint32_t *palette;
1462 uint8_t hwc_palette[3 * 3];
1463 uint8_t *hwc_src = NULL;
1464
1465 if (!((crt ? s->dc_crt_control : s->dc_panel_control)
1466 & SM501_DC_CRT_CONTROL_ENABLE)) {
1467 return;
1468 }
1469
1470 palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE -
1471 SM501_DC_PANEL_PALETTE]
1472 : &s->dc_palette[0]);
1473
1474
1475 switch (src_bpp) {
1476 case 1:
1477 draw_line = draw_line8_funcs[dst_depth_index];
1478 break;
1479 case 2:
1480 draw_line = draw_line16_funcs[dst_depth_index];
1481 break;
1482 case 4:
1483 draw_line = draw_line32_funcs[dst_depth_index];
1484 break;
1485 default:
1486 printf("sm501 update display : invalid control register value.\n");
1487 abort();
1488 break;
1489 }
1490
1491
1492 if (is_hwc_enabled(s, crt)) {
1493
1494 draw_hwc_line = draw_hwc_line_funcs[dst_depth_index];
1495 hwc_src = get_hwc_address(s, crt);
1496 c_x = get_hwc_x(s, crt);
1497 c_y = get_hwc_y(s, crt);
1498 get_hwc_palette(s, crt, hwc_palette);
1499 }
1500
1501
1502 if (s->last_width != width || s->last_height != height) {
1503 qemu_console_resize(s->con, width, height);
1504 surface = qemu_console_surface(s->con);
1505 s->last_width = width;
1506 s->last_height = height;
1507 full_update = 1;
1508 }
1509
1510
1511 snap = memory_region_snapshot_and_clear_dirty(&s->local_mem_region,
1512 offset, width * height * src_bpp, DIRTY_MEMORY_VGA);
1513 for (y = 0, offset = 0; y < height; y++, offset += width * src_bpp) {
1514 int update, update_hwc;
1515
1516
1517 update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT;
1518 update = full_update || update_hwc;
1519
1520 update |= memory_region_snapshot_get_dirty(&s->local_mem_region, snap,
1521 offset, width * src_bpp);
1522
1523
1524 if (update) {
1525 uint8_t *d = surface_data(surface);
1526 d += y * width * dst_bpp;
1527
1528
1529 draw_line(d, s->local_mem + offset, width, palette);
1530
1531
1532 if (update_hwc) {
1533 draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y);
1534 }
1535
1536 if (y_start < 0) {
1537 y_start = y;
1538 }
1539 } else {
1540 if (y_start >= 0) {
1541
1542 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1543 y_start = -1;
1544 }
1545 }
1546 }
1547 g_free(snap);
1548
1549
1550 if (y_start >= 0) {
1551 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
1552 }
1553}
1554
1555static const GraphicHwOps sm501_ops = {
1556 .gfx_update = sm501_update_display,
1557};
1558
1559static void sm501_reset(SM501State *s)
1560{
1561 s->system_control = 0x00100000;
1562
1563
1564
1565
1566
1567
1568
1569
1570 s->misc_control = SM501_MISC_DAC_POWER;
1571 s->gpio_31_0_control = 0;
1572 s->gpio_63_32_control = 0;
1573 s->dram_control = 0;
1574 s->arbitration_control = 0x05146732;
1575 s->irq_mask = 0;
1576 s->misc_timing = 0;
1577 s->power_mode_control = 0;
1578 s->dc_panel_control = 0x00010000;
1579 s->dc_video_control = 0;
1580 s->dc_crt_control = 0x00010000;
1581 s->twoD_source = 0;
1582 s->twoD_destination = 0;
1583 s->twoD_dimension = 0;
1584 s->twoD_control = 0;
1585 s->twoD_pitch = 0;
1586 s->twoD_foreground = 0;
1587 s->twoD_background = 0;
1588 s->twoD_stretch = 0;
1589 s->twoD_color_compare = 0;
1590 s->twoD_color_compare_mask = 0;
1591 s->twoD_mask = 0;
1592 s->twoD_clip_tl = 0;
1593 s->twoD_clip_br = 0;
1594 s->twoD_mono_pattern_low = 0;
1595 s->twoD_mono_pattern_high = 0;
1596 s->twoD_window_width = 0;
1597 s->twoD_source_base = 0;
1598 s->twoD_destination_base = 0;
1599 s->twoD_alpha = 0;
1600 s->twoD_wrap = 0;
1601}
1602
1603static void sm501_init(SM501State *s, DeviceState *dev,
1604 uint32_t local_mem_bytes)
1605{
1606 s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
1607 SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s),
1608 s->local_mem_size_index);
1609
1610
1611 memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local",
1612 get_local_mem_size(s), &error_fatal);
1613 memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
1614 s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
1615
1616
1617 memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
1618 memory_region_init_io(&s->system_config_region, OBJECT(dev),
1619 &sm501_system_config_ops, s,
1620 "sm501-system-config", 0x6c);
1621 memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG,
1622 &s->system_config_region);
1623 memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev),
1624 &sm501_disp_ctrl_ops, s,
1625 "sm501-disp-ctrl", 0x1000);
1626 memory_region_add_subregion(&s->mmio_region, SM501_DC,
1627 &s->disp_ctrl_region);
1628 memory_region_init_io(&s->twoD_engine_region, OBJECT(dev),
1629 &sm501_2d_engine_ops, s,
1630 "sm501-2d-engine", 0x54);
1631 memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE,
1632 &s->twoD_engine_region);
1633
1634
1635 s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
1636}
1637
1638static const VMStateDescription vmstate_sm501_state = {
1639 .name = "sm501-state",
1640 .version_id = 1,
1641 .minimum_version_id = 1,
1642 .fields = (VMStateField[]) {
1643 VMSTATE_UINT32(local_mem_size_index, SM501State),
1644 VMSTATE_UINT32(system_control, SM501State),
1645 VMSTATE_UINT32(misc_control, SM501State),
1646 VMSTATE_UINT32(gpio_31_0_control, SM501State),
1647 VMSTATE_UINT32(gpio_63_32_control, SM501State),
1648 VMSTATE_UINT32(dram_control, SM501State),
1649 VMSTATE_UINT32(arbitration_control, SM501State),
1650 VMSTATE_UINT32(irq_mask, SM501State),
1651 VMSTATE_UINT32(misc_timing, SM501State),
1652 VMSTATE_UINT32(power_mode_control, SM501State),
1653 VMSTATE_UINT32(uart0_ier, SM501State),
1654 VMSTATE_UINT32(uart0_lcr, SM501State),
1655 VMSTATE_UINT32(uart0_mcr, SM501State),
1656 VMSTATE_UINT32(uart0_scr, SM501State),
1657 VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES),
1658 VMSTATE_UINT32(dc_panel_control, SM501State),
1659 VMSTATE_UINT32(dc_panel_panning_control, SM501State),
1660 VMSTATE_UINT32(dc_panel_fb_addr, SM501State),
1661 VMSTATE_UINT32(dc_panel_fb_offset, SM501State),
1662 VMSTATE_UINT32(dc_panel_fb_width, SM501State),
1663 VMSTATE_UINT32(dc_panel_fb_height, SM501State),
1664 VMSTATE_UINT32(dc_panel_tl_location, SM501State),
1665 VMSTATE_UINT32(dc_panel_br_location, SM501State),
1666 VMSTATE_UINT32(dc_panel_h_total, SM501State),
1667 VMSTATE_UINT32(dc_panel_h_sync, SM501State),
1668 VMSTATE_UINT32(dc_panel_v_total, SM501State),
1669 VMSTATE_UINT32(dc_panel_v_sync, SM501State),
1670 VMSTATE_UINT32(dc_panel_hwc_addr, SM501State),
1671 VMSTATE_UINT32(dc_panel_hwc_location, SM501State),
1672 VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State),
1673 VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State),
1674 VMSTATE_UINT32(dc_video_control, SM501State),
1675 VMSTATE_UINT32(dc_crt_control, SM501State),
1676 VMSTATE_UINT32(dc_crt_fb_addr, SM501State),
1677 VMSTATE_UINT32(dc_crt_fb_offset, SM501State),
1678 VMSTATE_UINT32(dc_crt_h_total, SM501State),
1679 VMSTATE_UINT32(dc_crt_h_sync, SM501State),
1680 VMSTATE_UINT32(dc_crt_v_total, SM501State),
1681 VMSTATE_UINT32(dc_crt_v_sync, SM501State),
1682 VMSTATE_UINT32(dc_crt_hwc_addr, SM501State),
1683 VMSTATE_UINT32(dc_crt_hwc_location, SM501State),
1684 VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State),
1685 VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State),
1686 VMSTATE_UINT32(twoD_source, SM501State),
1687 VMSTATE_UINT32(twoD_destination, SM501State),
1688 VMSTATE_UINT32(twoD_dimension, SM501State),
1689 VMSTATE_UINT32(twoD_control, SM501State),
1690 VMSTATE_UINT32(twoD_pitch, SM501State),
1691 VMSTATE_UINT32(twoD_foreground, SM501State),
1692 VMSTATE_UINT32(twoD_background, SM501State),
1693 VMSTATE_UINT32(twoD_stretch, SM501State),
1694 VMSTATE_UINT32(twoD_color_compare, SM501State),
1695 VMSTATE_UINT32(twoD_color_compare_mask, SM501State),
1696 VMSTATE_UINT32(twoD_mask, SM501State),
1697 VMSTATE_UINT32(twoD_clip_tl, SM501State),
1698 VMSTATE_UINT32(twoD_clip_br, SM501State),
1699 VMSTATE_UINT32(twoD_mono_pattern_low, SM501State),
1700 VMSTATE_UINT32(twoD_mono_pattern_high, SM501State),
1701 VMSTATE_UINT32(twoD_window_width, SM501State),
1702 VMSTATE_UINT32(twoD_source_base, SM501State),
1703 VMSTATE_UINT32(twoD_destination_base, SM501State),
1704 VMSTATE_UINT32(twoD_alpha, SM501State),
1705 VMSTATE_UINT32(twoD_wrap, SM501State),
1706 VMSTATE_END_OF_LIST()
1707 }
1708};
1709
1710#define TYPE_SYSBUS_SM501 "sysbus-sm501"
1711#define SYSBUS_SM501(obj) \
1712 OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
1713
1714typedef struct {
1715
1716 SysBusDevice parent_obj;
1717
1718 SM501State state;
1719 uint32_t vram_size;
1720 uint32_t base;
1721 void *chr_state;
1722} SM501SysBusState;
1723
1724static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
1725{
1726 SM501SysBusState *s = SYSBUS_SM501(dev);
1727 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1728 DeviceState *usb_dev;
1729
1730 sm501_init(&s->state, dev, s->vram_size);
1731 if (get_local_mem_size(&s->state) != s->vram_size) {
1732 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
1733 get_local_mem_size(&s->state));
1734 return;
1735 }
1736 sysbus_init_mmio(sbd, &s->state.local_mem_region);
1737 sysbus_init_mmio(sbd, &s->state.mmio_region);
1738
1739
1740 usb_dev = qdev_create(NULL, "sysbus-ohci");
1741 qdev_prop_set_uint32(usb_dev, "num-ports", 2);
1742 qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
1743 qdev_init_nofail(usb_dev);
1744 memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
1745 sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
1746 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
1747
1748
1749 if (s->chr_state) {
1750 serial_mm_init(&s->state.mmio_region, SM501_UART0, 2,
1751 NULL,
1752 115200, s->chr_state, DEVICE_LITTLE_ENDIAN);
1753 }
1754}
1755
1756static Property sm501_sysbus_properties[] = {
1757 DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
1758 DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
1759 DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state),
1760 DEFINE_PROP_END_OF_LIST(),
1761};
1762
1763static void sm501_reset_sysbus(DeviceState *dev)
1764{
1765 SM501SysBusState *s = SYSBUS_SM501(dev);
1766 sm501_reset(&s->state);
1767}
1768
1769static const VMStateDescription vmstate_sm501_sysbus = {
1770 .name = TYPE_SYSBUS_SM501,
1771 .version_id = 1,
1772 .minimum_version_id = 1,
1773 .fields = (VMStateField[]) {
1774 VMSTATE_STRUCT(state, SM501SysBusState, 1,
1775 vmstate_sm501_state, SM501State),
1776 VMSTATE_END_OF_LIST()
1777 }
1778};
1779
1780static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
1781{
1782 DeviceClass *dc = DEVICE_CLASS(klass);
1783
1784 dc->realize = sm501_realize_sysbus;
1785 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1786 dc->desc = "SM501 Multimedia Companion";
1787 dc->props = sm501_sysbus_properties;
1788 dc->reset = sm501_reset_sysbus;
1789 dc->vmsd = &vmstate_sm501_sysbus;
1790
1791
1792
1793}
1794
1795static const TypeInfo sm501_sysbus_info = {
1796 .name = TYPE_SYSBUS_SM501,
1797 .parent = TYPE_SYS_BUS_DEVICE,
1798 .instance_size = sizeof(SM501SysBusState),
1799 .class_init = sm501_sysbus_class_init,
1800};
1801
1802#define TYPE_PCI_SM501 "sm501"
1803#define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501)
1804
1805typedef struct {
1806
1807 PCIDevice parent_obj;
1808
1809 SM501State state;
1810 uint32_t vram_size;
1811} SM501PCIState;
1812
1813static void sm501_realize_pci(PCIDevice *dev, Error **errp)
1814{
1815 SM501PCIState *s = PCI_SM501(dev);
1816
1817 sm501_init(&s->state, DEVICE(dev), s->vram_size);
1818 if (get_local_mem_size(&s->state) != s->vram_size) {
1819 error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
1820 get_local_mem_size(&s->state));
1821 return;
1822 }
1823 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
1824 &s->state.local_mem_region);
1825 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
1826 &s->state.mmio_region);
1827}
1828
1829static Property sm501_pci_properties[] = {
1830 DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE),
1831 DEFINE_PROP_END_OF_LIST(),
1832};
1833
1834static void sm501_reset_pci(DeviceState *dev)
1835{
1836 SM501PCIState *s = PCI_SM501(dev);
1837 sm501_reset(&s->state);
1838
1839 s->state.misc_control |= 1;
1840}
1841
1842static const VMStateDescription vmstate_sm501_pci = {
1843 .name = TYPE_PCI_SM501,
1844 .version_id = 1,
1845 .minimum_version_id = 1,
1846 .fields = (VMStateField[]) {
1847 VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState),
1848 VMSTATE_STRUCT(state, SM501PCIState, 1,
1849 vmstate_sm501_state, SM501State),
1850 VMSTATE_END_OF_LIST()
1851 }
1852};
1853
1854static void sm501_pci_class_init(ObjectClass *klass, void *data)
1855{
1856 DeviceClass *dc = DEVICE_CLASS(klass);
1857 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1858
1859 k->realize = sm501_realize_pci;
1860 k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION;
1861 k->device_id = PCI_DEVICE_ID_SM501;
1862 k->class_id = PCI_CLASS_DISPLAY_OTHER;
1863 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1864 dc->desc = "SM501 Display Controller";
1865 dc->props = sm501_pci_properties;
1866 dc->reset = sm501_reset_pci;
1867 dc->hotpluggable = false;
1868 dc->vmsd = &vmstate_sm501_pci;
1869}
1870
1871static const TypeInfo sm501_pci_info = {
1872 .name = TYPE_PCI_SM501,
1873 .parent = TYPE_PCI_DEVICE,
1874 .instance_size = sizeof(SM501PCIState),
1875 .class_init = sm501_pci_class_init,
1876 .interfaces = (InterfaceInfo[]) {
1877 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1878 { },
1879 },
1880};
1881
1882static void sm501_register_types(void)
1883{
1884 type_register_static(&sm501_sysbus_info);
1885 type_register_static(&sm501_pci_info);
1886}
1887
1888type_init(sm501_register_types)
1889