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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/pci/pci.h"
28#include "hw/isa/isa.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/dma.h"
31
32#include "hw/ide/pci.h"
33#include "trace.h"
34
35
36#define CFR 0x50
37#define CFR_INTR_CH0 0x04
38#define CNTRL 0x51
39#define CNTRL_EN_CH0 0x04
40#define CNTRL_EN_CH1 0x08
41#define ARTTIM23 0x57
42#define ARTTIM23_INTR_CH1 0x10
43#define MRDMODE 0x71
44#define MRDMODE_INTR_CH0 0x04
45#define MRDMODE_INTR_CH1 0x08
46#define MRDMODE_BLK_CH0 0x10
47#define MRDMODE_BLK_CH1 0x20
48#define UDIDETCR0 0x73
49#define UDIDETCR1 0x7B
50
51static void cmd646_update_irq(PCIDevice *pd);
52
53static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
54 unsigned size)
55{
56 CMD646BAR *cmd646bar = opaque;
57
58 if (addr != 2 || size != 1) {
59 return ((uint64_t)1 << (size * 8)) - 1;
60 }
61 return ide_status_read(cmd646bar->bus, addr + 2);
62}
63
64static void cmd646_cmd_write(void *opaque, hwaddr addr,
65 uint64_t data, unsigned size)
66{
67 CMD646BAR *cmd646bar = opaque;
68
69 if (addr != 2 || size != 1) {
70 return;
71 }
72 ide_cmd_write(cmd646bar->bus, addr + 2, data);
73}
74
75static const MemoryRegionOps cmd646_cmd_ops = {
76 .read = cmd646_cmd_read,
77 .write = cmd646_cmd_write,
78 .endianness = DEVICE_LITTLE_ENDIAN,
79};
80
81static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
82 unsigned size)
83{
84 CMD646BAR *cmd646bar = opaque;
85
86 if (size == 1) {
87 return ide_ioport_read(cmd646bar->bus, addr);
88 } else if (addr == 0) {
89 if (size == 2) {
90 return ide_data_readw(cmd646bar->bus, addr);
91 } else {
92 return ide_data_readl(cmd646bar->bus, addr);
93 }
94 }
95 return ((uint64_t)1 << (size * 8)) - 1;
96}
97
98static void cmd646_data_write(void *opaque, hwaddr addr,
99 uint64_t data, unsigned size)
100{
101 CMD646BAR *cmd646bar = opaque;
102
103 if (size == 1) {
104 ide_ioport_write(cmd646bar->bus, addr, data);
105 } else if (addr == 0) {
106 if (size == 2) {
107 ide_data_writew(cmd646bar->bus, addr, data);
108 } else {
109 ide_data_writel(cmd646bar->bus, addr, data);
110 }
111 }
112}
113
114static const MemoryRegionOps cmd646_data_ops = {
115 .read = cmd646_data_read,
116 .write = cmd646_data_write,
117 .endianness = DEVICE_LITTLE_ENDIAN,
118};
119
120static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
121{
122 IDEBus *bus = &d->bus[bus_num];
123 CMD646BAR *bar = &d->cmd646_bar[bus_num];
124
125 bar->bus = bus;
126 bar->pci_dev = d;
127 memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
128 "cmd646-cmd", 4);
129 memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
130 "cmd646-data", 8);
131}
132
133static void cmd646_update_dma_interrupts(PCIDevice *pd)
134{
135
136 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
137 pd->config[CFR] |= CFR_INTR_CH0;
138 } else {
139 pd->config[CFR] &= ~CFR_INTR_CH0;
140 }
141
142 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
143 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
144 } else {
145 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
146 }
147}
148
149static void cmd646_update_udma_interrupts(PCIDevice *pd)
150{
151
152 if (pd->config[CFR] & CFR_INTR_CH0) {
153 pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
154 } else {
155 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
156 }
157
158 if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
159 pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
160 } else {
161 pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
162 }
163}
164
165static uint64_t bmdma_read(void *opaque, hwaddr addr,
166 unsigned size)
167{
168 BMDMAState *bm = opaque;
169 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
170 uint32_t val;
171
172 if (size != 1) {
173 return ((uint64_t)1 << (size * 8)) - 1;
174 }
175
176 switch(addr & 3) {
177 case 0:
178 val = bm->cmd;
179 break;
180 case 1:
181 val = pci_dev->config[MRDMODE];
182 break;
183 case 2:
184 val = bm->status;
185 break;
186 case 3:
187 if (bm == &bm->pci_dev->bmdma[0]) {
188 val = pci_dev->config[UDIDETCR0];
189 } else {
190 val = pci_dev->config[UDIDETCR1];
191 }
192 break;
193 default:
194 val = 0xff;
195 break;
196 }
197
198 trace_bmdma_read_cmd646(addr, val);
199 return val;
200}
201
202static void bmdma_write(void *opaque, hwaddr addr,
203 uint64_t val, unsigned size)
204{
205 BMDMAState *bm = opaque;
206 PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
207
208 if (size != 1) {
209 return;
210 }
211
212 trace_bmdma_write_cmd646(addr, val);
213 switch(addr & 3) {
214 case 0:
215 bmdma_cmd_writeb(bm, val);
216 break;
217 case 1:
218 pci_dev->config[MRDMODE] =
219 (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
220 cmd646_update_dma_interrupts(pci_dev);
221 cmd646_update_irq(pci_dev);
222 break;
223 case 2:
224 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
225 break;
226 case 3:
227 if (bm == &bm->pci_dev->bmdma[0]) {
228 pci_dev->config[UDIDETCR0] = val;
229 } else {
230 pci_dev->config[UDIDETCR1] = val;
231 }
232 break;
233 }
234}
235
236static const MemoryRegionOps cmd646_bmdma_ops = {
237 .read = bmdma_read,
238 .write = bmdma_write,
239};
240
241static void bmdma_setup_bar(PCIIDEState *d)
242{
243 BMDMAState *bm;
244 int i;
245
246 memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
247 for(i = 0;i < 2; i++) {
248 bm = &d->bmdma[i];
249 memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
250 "cmd646-bmdma-bus", 4);
251 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
252 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
253 &bmdma_addr_ioport_ops, bm,
254 "cmd646-bmdma-ioport", 4);
255 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
256 }
257}
258
259static void cmd646_update_irq(PCIDevice *pd)
260{
261 int pci_level;
262
263 pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
264 !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
265 ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
266 !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
267 pci_set_irq(pd, pci_level);
268}
269
270
271static void cmd646_set_irq(void *opaque, int channel, int level)
272{
273 PCIIDEState *d = opaque;
274 PCIDevice *pd = PCI_DEVICE(d);
275 int irq_mask;
276
277 irq_mask = MRDMODE_INTR_CH0 << channel;
278 if (level) {
279 pd->config[MRDMODE] |= irq_mask;
280 } else {
281 pd->config[MRDMODE] &= ~irq_mask;
282 }
283 cmd646_update_dma_interrupts(pd);
284 cmd646_update_irq(pd);
285}
286
287static void cmd646_reset(void *opaque)
288{
289 PCIIDEState *d = opaque;
290 unsigned int i;
291
292 for (i = 0; i < 2; i++) {
293 ide_bus_reset(&d->bus[i]);
294 }
295}
296
297static uint32_t cmd646_pci_config_read(PCIDevice *d,
298 uint32_t address, int len)
299{
300 return pci_default_read_config(d, address, len);
301}
302
303static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
304 int l)
305{
306 uint32_t i;
307
308 pci_default_write_config(d, addr, val, l);
309
310 for (i = addr; i < addr + l; i++) {
311 switch (i) {
312 case CFR:
313 case ARTTIM23:
314 cmd646_update_udma_interrupts(d);
315 break;
316 case MRDMODE:
317 cmd646_update_dma_interrupts(d);
318 break;
319 }
320 }
321
322 cmd646_update_irq(d);
323}
324
325
326static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
327{
328 PCIIDEState *d = PCI_IDE(dev);
329 uint8_t *pci_conf = dev->config;
330 qemu_irq *irq;
331 int i;
332
333 pci_conf[PCI_CLASS_PROG] = 0x8f;
334
335 pci_conf[CNTRL] = CNTRL_EN_CH0;
336 if (d->secondary) {
337
338 pci_conf[CNTRL] |= CNTRL_EN_CH1;
339 }
340
341
342 dev->wmask[CFR] = 0x0;
343 dev->w1cmask[CFR] = CFR_INTR_CH0;
344 dev->wmask[ARTTIM23] = 0x0;
345 dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
346 dev->wmask[MRDMODE] = 0x0;
347 dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
348
349 setup_cmd646_bar(d, 0);
350 setup_cmd646_bar(d, 1);
351 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
352 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
353 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
354 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
355 bmdma_setup_bar(d);
356 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
357
358
359 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
360
361 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
362 for (i = 0; i < 2; i++) {
363 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
364 ide_init2(&d->bus[i], irq[i]);
365
366 bmdma_init(&d->bus[i], &d->bmdma[i], d);
367 d->bmdma[i].bus = &d->bus[i];
368 ide_register_restart_cb(&d->bus[i]);
369 }
370
371 vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
372 qemu_register_reset(cmd646_reset, d);
373}
374
375static void pci_cmd646_ide_exitfn(PCIDevice *dev)
376{
377 PCIIDEState *d = PCI_IDE(dev);
378 unsigned i;
379
380 for (i = 0; i < 2; ++i) {
381 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
382 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
383 }
384}
385
386void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
387 int secondary_ide_enabled)
388{
389 PCIDevice *dev;
390
391 dev = pci_create(bus, -1, "cmd646-ide");
392 qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
393 qdev_init_nofail(&dev->qdev);
394
395 pci_ide_create_devs(dev, hd_table);
396}
397
398static Property cmd646_ide_properties[] = {
399 DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
400 DEFINE_PROP_END_OF_LIST(),
401};
402
403static void cmd646_ide_class_init(ObjectClass *klass, void *data)
404{
405 DeviceClass *dc = DEVICE_CLASS(klass);
406 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
407
408 k->realize = pci_cmd646_ide_realize;
409 k->exit = pci_cmd646_ide_exitfn;
410 k->vendor_id = PCI_VENDOR_ID_CMD;
411 k->device_id = PCI_DEVICE_ID_CMD_646;
412 k->revision = 0x07;
413 k->class_id = PCI_CLASS_STORAGE_IDE;
414 k->config_read = cmd646_pci_config_read;
415 k->config_write = cmd646_pci_config_write;
416 dc->props = cmd646_ide_properties;
417 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
418}
419
420static const TypeInfo cmd646_ide_info = {
421 .name = "cmd646-ide",
422 .parent = TYPE_PCI_IDE,
423 .class_init = cmd646_ide_class_init,
424};
425
426static void cmd646_ide_register_types(void)
427{
428 type_register_static(&cmd646_ide_info);
429}
430
431type_init(cmd646_ide_register_types)
432
