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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "gic_internal.h"
24#include "hw/arm/linux-boot-if.h"
25
26static int gic_pre_save(void *opaque)
27{
28 GICState *s = (GICState *)opaque;
29 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
30
31 if (c->pre_save) {
32 c->pre_save(s);
33 }
34
35 return 0;
36}
37
38static int gic_post_load(void *opaque, int version_id)
39{
40 GICState *s = (GICState *)opaque;
41 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
42
43 if (c->post_load) {
44 c->post_load(s);
45 }
46 return 0;
47}
48
49static const VMStateDescription vmstate_gic_irq_state = {
50 .name = "arm_gic_irq_state",
51 .version_id = 1,
52 .minimum_version_id = 1,
53 .fields = (VMStateField[]) {
54 VMSTATE_UINT8(enabled, gic_irq_state),
55 VMSTATE_UINT8(pending, gic_irq_state),
56 VMSTATE_UINT8(active, gic_irq_state),
57 VMSTATE_UINT8(level, gic_irq_state),
58 VMSTATE_BOOL(model, gic_irq_state),
59 VMSTATE_BOOL(edge_trigger, gic_irq_state),
60 VMSTATE_UINT8(group, gic_irq_state),
61 VMSTATE_END_OF_LIST()
62 }
63};
64
65static const VMStateDescription vmstate_gic = {
66 .name = "arm_gic",
67 .version_id = 12,
68 .minimum_version_id = 12,
69 .pre_save = gic_pre_save,
70 .post_load = gic_post_load,
71 .fields = (VMStateField[]) {
72 VMSTATE_UINT32(ctlr, GICState),
73 VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
74 VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
75 vmstate_gic_irq_state, gic_irq_state),
76 VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
77 VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
78 VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
79 VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
80 VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
81 VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
82 VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
83 VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
84 VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
85 VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
86 VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
87 VMSTATE_END_OF_LIST()
88 }
89};
90
91void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
92 const MemoryRegionOps *ops)
93{
94 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
95 int i = s->num_irq - GIC_INTERNAL;
96
97
98
99
100
101
102
103
104 i += (GIC_INTERNAL * s->num_cpu);
105 qdev_init_gpio_in(DEVICE(s), handler, i);
106
107 for (i = 0; i < s->num_cpu; i++) {
108 sysbus_init_irq(sbd, &s->parent_irq[i]);
109 }
110 for (i = 0; i < s->num_cpu; i++) {
111 sysbus_init_irq(sbd, &s->parent_fiq[i]);
112 }
113 for (i = 0; i < s->num_cpu; i++) {
114 sysbus_init_irq(sbd, &s->parent_virq[i]);
115 }
116 for (i = 0; i < s->num_cpu; i++) {
117 sysbus_init_irq(sbd, &s->parent_vfiq[i]);
118 }
119
120
121 memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
122 sysbus_init_mmio(sbd, &s->iomem);
123
124
125
126
127 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
128 s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
129 sysbus_init_mmio(sbd, &s->cpuiomem[0]);
130}
131
132static void arm_gic_common_realize(DeviceState *dev, Error **errp)
133{
134 GICState *s = ARM_GIC_COMMON(dev);
135 int num_irq = s->num_irq;
136
137 if (s->num_cpu > GIC_NCPU) {
138 error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
139 s->num_cpu, GIC_NCPU);
140 return;
141 }
142 s->num_irq += GIC_BASE_IRQ;
143 if (s->num_irq > GIC_MAXIRQ) {
144 error_setg(errp,
145 "requested %u interrupt lines exceeds GIC maximum %d",
146 num_irq, GIC_MAXIRQ);
147 return;
148 }
149
150
151
152
153 if (s->num_irq < 32 || (s->num_irq % 32)) {
154 error_setg(errp,
155 "%d interrupt lines unsupported: not divisible by 32",
156 num_irq);
157 return;
158 }
159
160 if (s->security_extn &&
161 (s->revision == REV_11MPCORE)) {
162 error_setg(errp, "this GIC revision does not implement "
163 "the security extensions");
164 return;
165 }
166}
167
168static void arm_gic_common_reset(DeviceState *dev)
169{
170 GICState *s = ARM_GIC_COMMON(dev);
171 int i, j;
172 int resetprio;
173
174
175
176
177
178
179
180
181 if (s->security_extn && s->irq_reset_nonsecure) {
182 resetprio = 0x80;
183 } else {
184 resetprio = 0;
185 }
186
187 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
188 for (i = 0 ; i < s->num_cpu; i++) {
189 if (s->revision == REV_11MPCORE) {
190 s->priority_mask[i] = 0xf0;
191 } else {
192 s->priority_mask[i] = resetprio;
193 }
194 s->current_pending[i] = 1023;
195 s->running_priority[i] = 0x100;
196 s->cpu_ctlr[i] = 0;
197 s->bpr[i] = GIC_MIN_BPR;
198 s->abpr[i] = GIC_MIN_ABPR;
199 for (j = 0; j < GIC_INTERNAL; j++) {
200 s->priority1[j][i] = resetprio;
201 }
202 for (j = 0; j < GIC_NR_SGIS; j++) {
203 s->sgi_pending[j][i] = 0;
204 }
205 }
206 for (i = 0; i < GIC_NR_SGIS; i++) {
207 GIC_SET_ENABLED(i, ALL_CPU_MASK);
208 GIC_SET_EDGE_TRIGGER(i);
209 }
210
211 for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
212 s->priority2[i] = resetprio;
213 }
214
215 for (i = 0; i < GIC_MAXIRQ; i++) {
216
217 if (s->num_cpu == 1) {
218 s->irq_target[i] = 1;
219 } else {
220 s->irq_target[i] = 0;
221 }
222 }
223 if (s->security_extn && s->irq_reset_nonsecure) {
224 for (i = 0; i < GIC_MAXIRQ; i++) {
225 GIC_SET_GROUP(i, ALL_CPU_MASK);
226 }
227 }
228
229 s->ctlr = 0;
230}
231
232static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
233 bool secure_boot)
234{
235 GICState *s = ARM_GIC_COMMON(obj);
236
237 if (s->security_extn && !secure_boot) {
238
239
240
241
242
243
244
245 s->irq_reset_nonsecure = true;
246 }
247}
248
249static Property arm_gic_common_properties[] = {
250 DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
251 DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
252
253
254
255 DEFINE_PROP_UINT32("revision", GICState, revision, 1),
256
257 DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
258 DEFINE_PROP_END_OF_LIST(),
259};
260
261static void arm_gic_common_class_init(ObjectClass *klass, void *data)
262{
263 DeviceClass *dc = DEVICE_CLASS(klass);
264 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
265
266 dc->reset = arm_gic_common_reset;
267 dc->realize = arm_gic_common_realize;
268 dc->props = arm_gic_common_properties;
269 dc->vmsd = &vmstate_gic;
270 albifc->arm_linux_init = arm_gic_common_linux_init;
271}
272
273static const TypeInfo arm_gic_common_type = {
274 .name = TYPE_ARM_GIC_COMMON,
275 .parent = TYPE_SYS_BUS_DEVICE,
276 .instance_size = sizeof(GICState),
277 .class_size = sizeof(ARMGICCommonClass),
278 .class_init = arm_gic_common_class_init,
279 .abstract = true,
280 .interfaces = (InterfaceInfo []) {
281 { TYPE_ARM_LINUX_BOOT_IF },
282 { },
283 },
284};
285
286static void register_types(void)
287{
288 type_register_static(&arm_gic_common_type);
289}
290
291type_init(register_types)
292