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28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "qemu-common.h"
31#include "cpu.h"
32#include "hw/hw.h"
33#include "trace.h"
34#include "qemu/timer.h"
35#include "hw/ppc/xics.h"
36#include "qemu/error-report.h"
37#include "qapi/visitor.h"
38#include "monitor/monitor.h"
39#include "hw/intc/intc.h"
40
41void icp_pic_print_info(ICPState *icp, Monitor *mon)
42{
43 ICPStateClass *icpc = ICP_GET_CLASS(icp);
44 int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
45
46 if (!icp->output) {
47 return;
48 }
49
50 if (icpc->synchronize_state) {
51 icpc->synchronize_state(icp);
52 }
53
54 monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
55 cpu_index, icp->xirr, icp->xirr_owner,
56 icp->pending_priority, icp->mfrr);
57}
58
59void ics_pic_print_info(ICSState *ics, Monitor *mon)
60{
61 ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
62 uint32_t i;
63
64 monitor_printf(mon, "ICS %4x..%4x %p\n",
65 ics->offset, ics->offset + ics->nr_irqs - 1, ics);
66
67 if (!ics->irqs) {
68 return;
69 }
70
71 if (icsc->synchronize_state) {
72 icsc->synchronize_state(ics);
73 }
74
75 for (i = 0; i < ics->nr_irqs; i++) {
76 ICSIRQState *irq = ics->irqs + i;
77
78 if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
79 continue;
80 }
81 monitor_printf(mon, " %4x %s %02x %02x\n",
82 ics->offset + i,
83 (irq->flags & XICS_FLAGS_IRQ_LSI) ?
84 "LSI" : "MSI",
85 irq->priority, irq->status);
86 }
87}
88
89
90
91
92
93#define XISR_MASK 0x00ffffff
94#define CPPR_MASK 0xff000000
95
96#define XISR(icp) (((icp)->xirr) & XISR_MASK)
97#define CPPR(icp) (((icp)->xirr) >> 24)
98
99static void ics_reject(ICSState *ics, uint32_t nr)
100{
101 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
102
103 if (k->reject) {
104 k->reject(ics, nr);
105 }
106}
107
108void ics_resend(ICSState *ics)
109{
110 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
111
112 if (k->resend) {
113 k->resend(ics);
114 }
115}
116
117static void ics_eoi(ICSState *ics, int nr)
118{
119 ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
120
121 if (k->eoi) {
122 k->eoi(ics, nr);
123 }
124}
125
126static void icp_check_ipi(ICPState *icp)
127{
128 if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
129 return;
130 }
131
132 trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
133
134 if (XISR(icp) && icp->xirr_owner) {
135 ics_reject(icp->xirr_owner, XISR(icp));
136 }
137
138 icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
139 icp->pending_priority = icp->mfrr;
140 icp->xirr_owner = NULL;
141 qemu_irq_raise(icp->output);
142}
143
144void icp_resend(ICPState *icp)
145{
146 XICSFabric *xi = icp->xics;
147 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
148
149 if (icp->mfrr < CPPR(icp)) {
150 icp_check_ipi(icp);
151 }
152
153 xic->ics_resend(xi);
154}
155
156void icp_set_cppr(ICPState *icp, uint8_t cppr)
157{
158 uint8_t old_cppr;
159 uint32_t old_xisr;
160
161 old_cppr = CPPR(icp);
162 icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
163
164 if (cppr < old_cppr) {
165 if (XISR(icp) && (cppr <= icp->pending_priority)) {
166 old_xisr = XISR(icp);
167 icp->xirr &= ~XISR_MASK;
168 icp->pending_priority = 0xff;
169 qemu_irq_lower(icp->output);
170 if (icp->xirr_owner) {
171 ics_reject(icp->xirr_owner, old_xisr);
172 icp->xirr_owner = NULL;
173 }
174 }
175 } else {
176 if (!XISR(icp)) {
177 icp_resend(icp);
178 }
179 }
180}
181
182void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
183{
184 icp->mfrr = mfrr;
185 if (mfrr < CPPR(icp)) {
186 icp_check_ipi(icp);
187 }
188}
189
190uint32_t icp_accept(ICPState *icp)
191{
192 uint32_t xirr = icp->xirr;
193
194 qemu_irq_lower(icp->output);
195 icp->xirr = icp->pending_priority << 24;
196 icp->pending_priority = 0xff;
197 icp->xirr_owner = NULL;
198
199 trace_xics_icp_accept(xirr, icp->xirr);
200
201 return xirr;
202}
203
204uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
205{
206 if (mfrr) {
207 *mfrr = icp->mfrr;
208 }
209 return icp->xirr;
210}
211
212void icp_eoi(ICPState *icp, uint32_t xirr)
213{
214 XICSFabric *xi = icp->xics;
215 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
216 ICSState *ics;
217 uint32_t irq;
218
219
220 icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
221 trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
222 irq = xirr & XISR_MASK;
223
224 ics = xic->ics_get(xi, irq);
225 if (ics) {
226 ics_eoi(ics, irq);
227 }
228 if (!XISR(icp)) {
229 icp_resend(icp);
230 }
231}
232
233static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
234{
235 ICPState *icp = xics_icp_get(ics->xics, server);
236
237 trace_xics_icp_irq(server, nr, priority);
238
239 if ((priority >= CPPR(icp))
240 || (XISR(icp) && (icp->pending_priority <= priority))) {
241 ics_reject(ics, nr);
242 } else {
243 if (XISR(icp) && icp->xirr_owner) {
244 ics_reject(icp->xirr_owner, XISR(icp));
245 icp->xirr_owner = NULL;
246 }
247 icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
248 icp->xirr_owner = ics;
249 icp->pending_priority = priority;
250 trace_xics_icp_raise(icp->xirr, icp->pending_priority);
251 qemu_irq_raise(icp->output);
252 }
253}
254
255static int icp_dispatch_pre_save(void *opaque)
256{
257 ICPState *icp = opaque;
258 ICPStateClass *info = ICP_GET_CLASS(icp);
259
260 if (info->pre_save) {
261 info->pre_save(icp);
262 }
263
264 return 0;
265}
266
267static int icp_dispatch_post_load(void *opaque, int version_id)
268{
269 ICPState *icp = opaque;
270 ICPStateClass *info = ICP_GET_CLASS(icp);
271
272 if (info->post_load) {
273 return info->post_load(icp, version_id);
274 }
275
276 return 0;
277}
278
279static const VMStateDescription vmstate_icp_server = {
280 .name = "icp/server",
281 .version_id = 1,
282 .minimum_version_id = 1,
283 .pre_save = icp_dispatch_pre_save,
284 .post_load = icp_dispatch_post_load,
285 .fields = (VMStateField[]) {
286
287 VMSTATE_UINT32(xirr, ICPState),
288 VMSTATE_UINT8(pending_priority, ICPState),
289 VMSTATE_UINT8(mfrr, ICPState),
290 VMSTATE_END_OF_LIST()
291 },
292};
293
294static void icp_reset(void *dev)
295{
296 ICPState *icp = ICP(dev);
297 ICPStateClass *icpc = ICP_GET_CLASS(icp);
298
299 icp->xirr = 0;
300 icp->pending_priority = 0xff;
301 icp->mfrr = 0xff;
302
303
304 qemu_set_irq(icp->output, 0);
305
306 if (icpc->reset) {
307 icpc->reset(icp);
308 }
309}
310
311static void icp_realize(DeviceState *dev, Error **errp)
312{
313 ICPState *icp = ICP(dev);
314 ICPStateClass *icpc = ICP_GET_CLASS(dev);
315 PowerPCCPU *cpu;
316 CPUPPCState *env;
317 Object *obj;
318 Error *err = NULL;
319
320 obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
321 if (!obj) {
322 error_propagate(errp, err);
323 error_prepend(errp, "required link '" ICP_PROP_XICS "' not found: ");
324 return;
325 }
326
327 icp->xics = XICS_FABRIC(obj);
328
329 obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
330 if (!obj) {
331 error_propagate(errp, err);
332 error_prepend(errp, "required link '" ICP_PROP_CPU "' not found: ");
333 return;
334 }
335
336 cpu = POWERPC_CPU(obj);
337 icp->cs = CPU(obj);
338
339 env = &cpu->env;
340 switch (PPC_INPUT(env)) {
341 case PPC_FLAGS_INPUT_POWER7:
342 icp->output = env->irq_inputs[POWER7_INPUT_INT];
343 break;
344
345 case PPC_FLAGS_INPUT_970:
346 icp->output = env->irq_inputs[PPC970_INPUT_INT];
347 break;
348
349 default:
350 error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
351 return;
352 }
353
354 if (icpc->realize) {
355 icpc->realize(icp, errp);
356 }
357
358 qemu_register_reset(icp_reset, dev);
359 vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
360}
361
362static void icp_unrealize(DeviceState *dev, Error **errp)
363{
364 ICPState *icp = ICP(dev);
365
366 vmstate_unregister(NULL, &vmstate_icp_server, icp);
367 qemu_unregister_reset(icp_reset, dev);
368}
369
370static void icp_class_init(ObjectClass *klass, void *data)
371{
372 DeviceClass *dc = DEVICE_CLASS(klass);
373
374 dc->realize = icp_realize;
375 dc->unrealize = icp_unrealize;
376}
377
378static const TypeInfo icp_info = {
379 .name = TYPE_ICP,
380 .parent = TYPE_DEVICE,
381 .instance_size = sizeof(ICPState),
382 .class_init = icp_class_init,
383 .class_size = sizeof(ICPStateClass),
384};
385
386Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
387{
388 Error *local_err = NULL;
389 Object *obj;
390
391 obj = object_new(type);
392 object_property_add_child(cpu, type, obj, &error_abort);
393 object_unref(obj);
394 object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
395 &error_abort);
396 object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
397 object_property_set_bool(obj, true, "realized", &local_err);
398 if (local_err) {
399 object_unparent(obj);
400 error_propagate(errp, local_err);
401 obj = NULL;
402 }
403
404 return obj;
405}
406
407
408
409
410static void ics_simple_resend_msi(ICSState *ics, int srcno)
411{
412 ICSIRQState *irq = ics->irqs + srcno;
413
414
415 if (irq->status & XICS_STATUS_REJECTED) {
416 irq->status &= ~XICS_STATUS_REJECTED;
417 if (irq->priority != 0xff) {
418 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
419 }
420 }
421}
422
423static void ics_simple_resend_lsi(ICSState *ics, int srcno)
424{
425 ICSIRQState *irq = ics->irqs + srcno;
426
427 if ((irq->priority != 0xff)
428 && (irq->status & XICS_STATUS_ASSERTED)
429 && !(irq->status & XICS_STATUS_SENT)) {
430 irq->status |= XICS_STATUS_SENT;
431 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
432 }
433}
434
435static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
436{
437 ICSIRQState *irq = ics->irqs + srcno;
438
439 trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
440
441 if (val) {
442 if (irq->priority == 0xff) {
443 irq->status |= XICS_STATUS_MASKED_PENDING;
444 trace_xics_masked_pending();
445 } else {
446 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
447 }
448 }
449}
450
451static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
452{
453 ICSIRQState *irq = ics->irqs + srcno;
454
455 trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
456 if (val) {
457 irq->status |= XICS_STATUS_ASSERTED;
458 } else {
459 irq->status &= ~XICS_STATUS_ASSERTED;
460 }
461 ics_simple_resend_lsi(ics, srcno);
462}
463
464static void ics_simple_set_irq(void *opaque, int srcno, int val)
465{
466 ICSState *ics = (ICSState *)opaque;
467
468 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
469 ics_simple_set_irq_lsi(ics, srcno, val);
470 } else {
471 ics_simple_set_irq_msi(ics, srcno, val);
472 }
473}
474
475static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
476{
477 ICSIRQState *irq = ics->irqs + srcno;
478
479 if (!(irq->status & XICS_STATUS_MASKED_PENDING)
480 || (irq->priority == 0xff)) {
481 return;
482 }
483
484 irq->status &= ~XICS_STATUS_MASKED_PENDING;
485 icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
486}
487
488static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
489{
490 ics_simple_resend_lsi(ics, srcno);
491}
492
493void ics_simple_write_xive(ICSState *ics, int srcno, int server,
494 uint8_t priority, uint8_t saved_priority)
495{
496 ICSIRQState *irq = ics->irqs + srcno;
497
498 irq->server = server;
499 irq->priority = priority;
500 irq->saved_priority = saved_priority;
501
502 trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
503 priority);
504
505 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
506 ics_simple_write_xive_lsi(ics, srcno);
507 } else {
508 ics_simple_write_xive_msi(ics, srcno);
509 }
510}
511
512static void ics_simple_reject(ICSState *ics, uint32_t nr)
513{
514 ICSIRQState *irq = ics->irqs + nr - ics->offset;
515
516 trace_xics_ics_simple_reject(nr, nr - ics->offset);
517 if (irq->flags & XICS_FLAGS_IRQ_MSI) {
518 irq->status |= XICS_STATUS_REJECTED;
519 } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
520 irq->status &= ~XICS_STATUS_SENT;
521 }
522}
523
524static void ics_simple_resend(ICSState *ics)
525{
526 int i;
527
528 for (i = 0; i < ics->nr_irqs; i++) {
529
530 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
531 ics_simple_resend_lsi(ics, i);
532 } else {
533 ics_simple_resend_msi(ics, i);
534 }
535 }
536}
537
538static void ics_simple_eoi(ICSState *ics, uint32_t nr)
539{
540 int srcno = nr - ics->offset;
541 ICSIRQState *irq = ics->irqs + srcno;
542
543 trace_xics_ics_simple_eoi(nr);
544
545 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
546 irq->status &= ~XICS_STATUS_SENT;
547 }
548}
549
550static void ics_simple_reset(void *dev)
551{
552 ICSState *ics = ICS_SIMPLE(dev);
553 int i;
554 uint8_t flags[ics->nr_irqs];
555
556 for (i = 0; i < ics->nr_irqs; i++) {
557 flags[i] = ics->irqs[i].flags;
558 }
559
560 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
561
562 for (i = 0; i < ics->nr_irqs; i++) {
563 ics->irqs[i].priority = 0xff;
564 ics->irqs[i].saved_priority = 0xff;
565 ics->irqs[i].flags = flags[i];
566 }
567}
568
569static int ics_simple_dispatch_pre_save(void *opaque)
570{
571 ICSState *ics = opaque;
572 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
573
574 if (info->pre_save) {
575 info->pre_save(ics);
576 }
577
578 return 0;
579}
580
581static int ics_simple_dispatch_post_load(void *opaque, int version_id)
582{
583 ICSState *ics = opaque;
584 ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
585
586 if (info->post_load) {
587 return info->post_load(ics, version_id);
588 }
589
590 return 0;
591}
592
593static const VMStateDescription vmstate_ics_simple_irq = {
594 .name = "ics/irq",
595 .version_id = 2,
596 .minimum_version_id = 1,
597 .fields = (VMStateField[]) {
598 VMSTATE_UINT32(server, ICSIRQState),
599 VMSTATE_UINT8(priority, ICSIRQState),
600 VMSTATE_UINT8(saved_priority, ICSIRQState),
601 VMSTATE_UINT8(status, ICSIRQState),
602 VMSTATE_UINT8(flags, ICSIRQState),
603 VMSTATE_END_OF_LIST()
604 },
605};
606
607static const VMStateDescription vmstate_ics_simple = {
608 .name = "ics",
609 .version_id = 1,
610 .minimum_version_id = 1,
611 .pre_save = ics_simple_dispatch_pre_save,
612 .post_load = ics_simple_dispatch_post_load,
613 .fields = (VMStateField[]) {
614
615 VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
616
617 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
618 vmstate_ics_simple_irq,
619 ICSIRQState),
620 VMSTATE_END_OF_LIST()
621 },
622};
623
624static void ics_simple_initfn(Object *obj)
625{
626 ICSState *ics = ICS_SIMPLE(obj);
627
628 ics->offset = XICS_IRQ_BASE;
629}
630
631static void ics_simple_realize(ICSState *ics, Error **errp)
632{
633 if (!ics->nr_irqs) {
634 error_setg(errp, "Number of interrupts needs to be greater 0");
635 return;
636 }
637 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
638 ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
639
640 qemu_register_reset(ics_simple_reset, ics);
641}
642
643static Property ics_simple_properties[] = {
644 DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
645 DEFINE_PROP_END_OF_LIST(),
646};
647
648static void ics_simple_class_init(ObjectClass *klass, void *data)
649{
650 DeviceClass *dc = DEVICE_CLASS(klass);
651 ICSStateClass *isc = ICS_BASE_CLASS(klass);
652
653 isc->realize = ics_simple_realize;
654 dc->props = ics_simple_properties;
655 dc->vmsd = &vmstate_ics_simple;
656 isc->reject = ics_simple_reject;
657 isc->resend = ics_simple_resend;
658 isc->eoi = ics_simple_eoi;
659}
660
661static const TypeInfo ics_simple_info = {
662 .name = TYPE_ICS_SIMPLE,
663 .parent = TYPE_ICS_BASE,
664 .instance_size = sizeof(ICSState),
665 .class_init = ics_simple_class_init,
666 .class_size = sizeof(ICSStateClass),
667 .instance_init = ics_simple_initfn,
668};
669
670static void ics_base_realize(DeviceState *dev, Error **errp)
671{
672 ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
673 ICSState *ics = ICS_BASE(dev);
674 Object *obj;
675 Error *err = NULL;
676
677 obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
678 if (!obj) {
679 error_propagate(errp, err);
680 error_prepend(errp, "required link '" ICS_PROP_XICS "' not found: ");
681 return;
682 }
683 ics->xics = XICS_FABRIC(obj);
684
685
686 if (icsc->realize) {
687 icsc->realize(ics, errp);
688 }
689}
690
691static void ics_base_class_init(ObjectClass *klass, void *data)
692{
693 DeviceClass *dc = DEVICE_CLASS(klass);
694
695 dc->realize = ics_base_realize;
696}
697
698static const TypeInfo ics_base_info = {
699 .name = TYPE_ICS_BASE,
700 .parent = TYPE_DEVICE,
701 .abstract = true,
702 .instance_size = sizeof(ICSState),
703 .class_init = ics_base_class_init,
704 .class_size = sizeof(ICSStateClass),
705};
706
707static const TypeInfo xics_fabric_info = {
708 .name = TYPE_XICS_FABRIC,
709 .parent = TYPE_INTERFACE,
710 .class_size = sizeof(XICSFabricClass),
711};
712
713
714
715
716ICPState *xics_icp_get(XICSFabric *xi, int server)
717{
718 XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
719
720 return xic->icp_get(xi, server);
721}
722
723void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
724{
725 assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
726
727 ics->irqs[srcno].flags |=
728 lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
729}
730
731static void xics_register_types(void)
732{
733 type_register_static(&ics_simple_info);
734 type_register_static(&ics_base_info);
735 type_register_static(&icp_info);
736 type_register_static(&xics_fabric_info);
737}
738
739type_init(xics_register_types)
740
