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18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "qemu-common.h"
21#include "exec/address-spaces.h"
22#include "hw/boards.h"
23#include "hw/qdev-properties.h"
24#include "cpu.h"
25#include "boot.h"
26
27#include "hw/intc/xlnx-zynqmp-ipi.h"
28#include "hw/intc/xlnx-pmu-iomod-intc.h"
29
30
31
32#define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx,zynqmp-pmu-soc"
33#define XLNX_ZYNQMP_PMU_SOC(obj) OBJECT_CHECK(XlnxZynqMPPMUSoCState, (obj), \
34 TYPE_XLNX_ZYNQMP_PMU_SOC)
35
36#define XLNX_ZYNQMP_PMU_ROM_SIZE 0x8000
37#define XLNX_ZYNQMP_PMU_ROM_ADDR 0xFFD00000
38#define XLNX_ZYNQMP_PMU_RAM_ADDR 0xFFDC0000
39
40#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
41
42#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
43
44static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
45 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
46};
47static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
48 19, 20, 21, 22,
49};
50
51typedef struct XlnxZynqMPPMUSoCState {
52
53 DeviceState parent_obj;
54
55
56 MicroBlazeCPU cpu;
57 XlnxPMUIOIntc intc;
58} XlnxZynqMPPMUSoCState;
59
60
61static void xlnx_zynqmp_pmu_soc_init(Object *obj)
62{
63 XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
64
65 object_initialize(&s->cpu, sizeof(s->cpu),
66 TYPE_MICROBLAZE_CPU);
67 object_property_add_child(obj, "pmu-cpu", OBJECT(&s->cpu),
68 &error_abort);
69
70 object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC);
71 qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
72}
73
74static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
75{
76 XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(dev);
77 Error *err = NULL;
78
79 object_property_set_uint(OBJECT(&s->cpu), XLNX_ZYNQMP_PMU_ROM_ADDR,
80 "base-vectors", &error_abort);
81 object_property_set_bool(OBJECT(&s->cpu), true, "use-stack-protection",
82 &error_abort);
83 object_property_set_uint(OBJECT(&s->cpu), 0, "use-fpu", &error_abort);
84 object_property_set_uint(OBJECT(&s->cpu), 0, "use-hw-mul", &error_abort);
85 object_property_set_bool(OBJECT(&s->cpu), true, "use-barrel",
86 &error_abort);
87 object_property_set_bool(OBJECT(&s->cpu), true, "use-msr-instr",
88 &error_abort);
89 object_property_set_bool(OBJECT(&s->cpu), true, "use-pcmp-instr",
90 &error_abort);
91 object_property_set_bool(OBJECT(&s->cpu), false, "use-mmu", &error_abort);
92 object_property_set_bool(OBJECT(&s->cpu), true, "endianness",
93 &error_abort);
94 object_property_set_str(OBJECT(&s->cpu), "8.40.b", "version",
95 &error_abort);
96 object_property_set_uint(OBJECT(&s->cpu), 0, "pvr", &error_abort);
97 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
98 if (err) {
99 error_propagate(errp, err);
100 return;
101 }
102
103 object_property_set_uint(OBJECT(&s->intc), 0x10, "intc-intr-size",
104 &error_abort);
105 object_property_set_uint(OBJECT(&s->intc), 0x0, "intc-level-edge",
106 &error_abort);
107 object_property_set_uint(OBJECT(&s->intc), 0xffff, "intc-positive",
108 &error_abort);
109 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
110 if (err) {
111 error_propagate(errp, err);
112 return;
113 }
114 sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
115 sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
116 qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
117}
118
119static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
120{
121 DeviceClass *dc = DEVICE_CLASS(oc);
122
123 dc->realize = xlnx_zynqmp_pmu_soc_realize;
124}
125
126static const TypeInfo xlnx_zynqmp_pmu_soc_type_info = {
127 .name = TYPE_XLNX_ZYNQMP_PMU_SOC,
128 .parent = TYPE_DEVICE,
129 .instance_size = sizeof(XlnxZynqMPPMUSoCState),
130 .instance_init = xlnx_zynqmp_pmu_soc_init,
131 .class_init = xlnx_zynqmp_pmu_soc_class_init,
132};
133
134static void xlnx_zynqmp_pmu_soc_register_types(void)
135{
136 type_register_static(&xlnx_zynqmp_pmu_soc_type_info);
137}
138
139type_init(xlnx_zynqmp_pmu_soc_register_types)
140
141
142
143static void xlnx_zynqmp_pmu_init(MachineState *machine)
144{
145 XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1);
146 MemoryRegion *address_space_mem = get_system_memory();
147 MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
148 MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
149 XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
150 qemu_irq irq[32];
151 int i;
152
153
154 memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
155 XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal);
156 memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR,
157 pmu_rom);
158
159
160 memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram",
161 machine->ram_size, &error_fatal);
162 memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR,
163 pmu_ram);
164
165
166 object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);
167 object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
168 &error_abort);
169 object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
170
171 for (i = 0; i < 32; i++) {
172 irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
173 }
174
175
176 for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
177 ipi[i] = g_new0(XlnxZynqMPIPI, 1);
178 object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
179 qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());
180 }
181
182 for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
183 object_property_set_bool(OBJECT(ipi[i]), true, "realized",
184 &error_abort);
185 sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);
186 sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
187 }
188
189
190 microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
191 machine->ram_size,
192 machine->initrd_filename,
193 machine->dtb,
194 NULL);
195}
196
197static void xlnx_zynqmp_pmu_machine_init(MachineClass *mc)
198{
199 mc->desc = "Xilinx ZynqMP PMU machine";
200 mc->init = xlnx_zynqmp_pmu_init;
201}
202
203DEFINE_MACHINE("xlnx-zynqmp-pmu", xlnx_zynqmp_pmu_machine_init)
204
205
