1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include "qemu/osdep.h"
25#include "hw/pci/pci.h"
26#include "net/eth.h"
27#include "ne2000.h"
28#include "sysemu/sysemu.h"
29
30
31
32
33#define MAX_ETH_FRAME_SIZE 1514
34
35#define E8390_CMD 0x00
36
37#define EN0_CLDALO 0x01
38#define EN0_STARTPG 0x01
39#define EN0_CLDAHI 0x02
40#define EN0_STOPPG 0x02
41#define EN0_BOUNDARY 0x03
42#define EN0_TSR 0x04
43#define EN0_TPSR 0x04
44#define EN0_NCR 0x05
45#define EN0_TCNTLO 0x05
46#define EN0_FIFO 0x06
47#define EN0_TCNTHI 0x06
48#define EN0_ISR 0x07
49#define EN0_CRDALO 0x08
50#define EN0_RSARLO 0x08
51#define EN0_CRDAHI 0x09
52#define EN0_RSARHI 0x09
53#define EN0_RCNTLO 0x0a
54#define EN0_RTL8029ID0 0x0a
55#define EN0_RCNTHI 0x0b
56#define EN0_RTL8029ID1 0x0b
57#define EN0_RSR 0x0c
58#define EN0_RXCR 0x0c
59#define EN0_TXCR 0x0d
60#define EN0_COUNTER0 0x0d
61#define EN0_DCFG 0x0e
62#define EN0_COUNTER1 0x0e
63#define EN0_IMR 0x0f
64#define EN0_COUNTER2 0x0f
65
66#define EN1_PHYS 0x11
67#define EN1_CURPAG 0x17
68#define EN1_MULT 0x18
69
70#define EN2_STARTPG 0x21
71#define EN2_STOPPG 0x22
72
73#define EN3_CONFIG0 0x33
74#define EN3_CONFIG1 0x34
75#define EN3_CONFIG2 0x35
76#define EN3_CONFIG3 0x36
77
78
79#define E8390_STOP 0x01
80#define E8390_START 0x02
81#define E8390_TRANS 0x04
82#define E8390_RREAD 0x08
83#define E8390_RWRITE 0x10
84#define E8390_NODMA 0x20
85#define E8390_PAGE0 0x00
86#define E8390_PAGE1 0x40
87#define E8390_PAGE2 0x80
88
89
90#define ENISR_RX 0x01
91#define ENISR_TX 0x02
92#define ENISR_RX_ERR 0x04
93#define ENISR_TX_ERR 0x08
94#define ENISR_OVER 0x10
95#define ENISR_COUNTERS 0x20
96#define ENISR_RDC 0x40
97#define ENISR_RESET 0x80
98#define ENISR_ALL 0x3f
99
100
101#define ENRSR_RXOK 0x01
102#define ENRSR_CRC 0x02
103#define ENRSR_FAE 0x04
104#define ENRSR_FO 0x08
105#define ENRSR_MPA 0x10
106#define ENRSR_PHY 0x20
107#define ENRSR_DIS 0x40
108#define ENRSR_DEF 0x80
109
110
111#define ENTSR_PTX 0x01
112#define ENTSR_ND 0x02
113#define ENTSR_COL 0x04
114#define ENTSR_ABT 0x08
115#define ENTSR_CRS 0x10
116#define ENTSR_FU 0x20
117#define ENTSR_CDH 0x40
118#define ENTSR_OWC 0x80
119
120typedef struct PCINE2000State {
121 PCIDevice dev;
122 NE2000State ne2000;
123} PCINE2000State;
124
125void ne2000_reset(NE2000State *s)
126{
127 int i;
128
129 s->isr = ENISR_RESET;
130 memcpy(s->mem, &s->c.macaddr, 6);
131 s->mem[14] = 0x57;
132 s->mem[15] = 0x57;
133
134
135 for(i = 15;i >= 0; i--) {
136 s->mem[2 * i] = s->mem[i];
137 s->mem[2 * i + 1] = s->mem[i];
138 }
139}
140
141static void ne2000_update_irq(NE2000State *s)
142{
143 int isr;
144 isr = (s->isr & s->imr) & 0x7f;
145#if defined(DEBUG_NE2000)
146 printf("NE2000: Set IRQ to %d (%02x %02x)\n",
147 isr ? 1 : 0, s->isr, s->imr);
148#endif
149 qemu_set_irq(s->irq, (isr != 0));
150}
151
152static int ne2000_buffer_full(NE2000State *s)
153{
154 int avail, index, boundary;
155
156 if (s->stop <= s->start) {
157 return 1;
158 }
159
160 index = s->curpag << 8;
161 boundary = s->boundary << 8;
162 if (index < boundary)
163 avail = boundary - index;
164 else
165 avail = (s->stop - s->start) - (index - boundary);
166 if (avail < (MAX_ETH_FRAME_SIZE + 4))
167 return 1;
168 return 0;
169}
170
171#define MIN_BUF_SIZE 60
172
173ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
174{
175 NE2000State *s = qemu_get_nic_opaque(nc);
176 int size = size_;
177 uint8_t *p;
178 unsigned int total_len, next, avail, len, index, mcast_idx;
179 uint8_t buf1[60];
180 static const uint8_t broadcast_macaddr[6] =
181 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
182
183#if defined(DEBUG_NE2000)
184 printf("NE2000: received len=%d\n", size);
185#endif
186
187 if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
188 return -1;
189
190
191 if (s->rxcr & 0x10) {
192
193 } else {
194 if (!memcmp(buf, broadcast_macaddr, 6)) {
195
196 if (!(s->rxcr & 0x04))
197 return size;
198 } else if (buf[0] & 0x01) {
199
200 if (!(s->rxcr & 0x08))
201 return size;
202 mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
203 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
204 return size;
205 } else if (s->mem[0] == buf[0] &&
206 s->mem[2] == buf[1] &&
207 s->mem[4] == buf[2] &&
208 s->mem[6] == buf[3] &&
209 s->mem[8] == buf[4] &&
210 s->mem[10] == buf[5]) {
211
212 } else {
213 return size;
214 }
215 }
216
217
218
219 if (size < MIN_BUF_SIZE) {
220 memcpy(buf1, buf, size);
221 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
222 buf = buf1;
223 size = MIN_BUF_SIZE;
224 }
225
226 index = s->curpag << 8;
227 if (index >= NE2000_PMEM_END) {
228 index = s->start;
229 }
230
231 total_len = size + 4;
232
233 next = index + ((total_len + 4 + 255) & ~0xff);
234 if (next >= s->stop)
235 next -= (s->stop - s->start);
236
237 p = s->mem + index;
238 s->rsr = ENRSR_RXOK;
239
240 if (buf[0] & 0x01)
241 s->rsr |= ENRSR_PHY;
242 p[0] = s->rsr;
243 p[1] = next >> 8;
244 p[2] = total_len;
245 p[3] = total_len >> 8;
246 index += 4;
247
248
249 while (size > 0) {
250 if (index <= s->stop)
251 avail = s->stop - index;
252 else
253 break;
254 len = size;
255 if (len > avail)
256 len = avail;
257 memcpy(s->mem + index, buf, len);
258 buf += len;
259 index += len;
260 if (index == s->stop)
261 index = s->start;
262 size -= len;
263 }
264 s->curpag = next >> 8;
265
266
267 s->isr |= ENISR_RX;
268 ne2000_update_irq(s);
269
270 return size_;
271}
272
273static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
274{
275 NE2000State *s = opaque;
276 int offset, page, index;
277
278 addr &= 0xf;
279#ifdef DEBUG_NE2000
280 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
281#endif
282 if (addr == E8390_CMD) {
283
284 s->cmd = val;
285 if (!(val & E8390_STOP)) {
286 s->isr &= ~ENISR_RESET;
287
288 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
289 s->rcnt == 0) {
290 s->isr |= ENISR_RDC;
291 ne2000_update_irq(s);
292 }
293 if (val & E8390_TRANS) {
294 index = (s->tpsr << 8);
295
296 if (index >= NE2000_PMEM_END)
297 index -= NE2000_PMEM_SIZE;
298
299 if (index + s->tcnt <= NE2000_PMEM_END) {
300 qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
301 s->tcnt);
302 }
303
304 s->tsr = ENTSR_PTX;
305 s->isr |= ENISR_TX;
306 s->cmd &= ~E8390_TRANS;
307 ne2000_update_irq(s);
308 }
309 }
310 } else {
311 page = s->cmd >> 6;
312 offset = addr | (page << 4);
313 switch(offset) {
314 case EN0_STARTPG:
315 if (val << 8 <= NE2000_PMEM_END) {
316 s->start = val << 8;
317 }
318 break;
319 case EN0_STOPPG:
320 if (val << 8 <= NE2000_PMEM_END) {
321 s->stop = val << 8;
322 }
323 break;
324 case EN0_BOUNDARY:
325 if (val << 8 < NE2000_PMEM_END) {
326 s->boundary = val;
327 }
328 break;
329 case EN0_IMR:
330 s->imr = val;
331 ne2000_update_irq(s);
332 break;
333 case EN0_TPSR:
334 s->tpsr = val;
335 break;
336 case EN0_TCNTLO:
337 s->tcnt = (s->tcnt & 0xff00) | val;
338 break;
339 case EN0_TCNTHI:
340 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
341 break;
342 case EN0_RSARLO:
343 s->rsar = (s->rsar & 0xff00) | val;
344 break;
345 case EN0_RSARHI:
346 s->rsar = (s->rsar & 0x00ff) | (val << 8);
347 break;
348 case EN0_RCNTLO:
349 s->rcnt = (s->rcnt & 0xff00) | val;
350 break;
351 case EN0_RCNTHI:
352 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
353 break;
354 case EN0_RXCR:
355 s->rxcr = val;
356 break;
357 case EN0_DCFG:
358 s->dcfg = val;
359 break;
360 case EN0_ISR:
361 s->isr &= ~(val & 0x7f);
362 ne2000_update_irq(s);
363 break;
364 case EN1_PHYS ... EN1_PHYS + 5:
365 s->phys[offset - EN1_PHYS] = val;
366 break;
367 case EN1_CURPAG:
368 if (val << 8 < NE2000_PMEM_END) {
369 s->curpag = val;
370 }
371 break;
372 case EN1_MULT ... EN1_MULT + 7:
373 s->mult[offset - EN1_MULT] = val;
374 break;
375 }
376 }
377}
378
379static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
380{
381 NE2000State *s = opaque;
382 int offset, page, ret;
383
384 addr &= 0xf;
385 if (addr == E8390_CMD) {
386 ret = s->cmd;
387 } else {
388 page = s->cmd >> 6;
389 offset = addr | (page << 4);
390 switch(offset) {
391 case EN0_TSR:
392 ret = s->tsr;
393 break;
394 case EN0_BOUNDARY:
395 ret = s->boundary;
396 break;
397 case EN0_ISR:
398 ret = s->isr;
399 break;
400 case EN0_RSARLO:
401 ret = s->rsar & 0x00ff;
402 break;
403 case EN0_RSARHI:
404 ret = s->rsar >> 8;
405 break;
406 case EN1_PHYS ... EN1_PHYS + 5:
407 ret = s->phys[offset - EN1_PHYS];
408 break;
409 case EN1_CURPAG:
410 ret = s->curpag;
411 break;
412 case EN1_MULT ... EN1_MULT + 7:
413 ret = s->mult[offset - EN1_MULT];
414 break;
415 case EN0_RSR:
416 ret = s->rsr;
417 break;
418 case EN2_STARTPG:
419 ret = s->start >> 8;
420 break;
421 case EN2_STOPPG:
422 ret = s->stop >> 8;
423 break;
424 case EN0_RTL8029ID0:
425 ret = 0x50;
426 break;
427 case EN0_RTL8029ID1:
428 ret = 0x43;
429 break;
430 case EN3_CONFIG0:
431 ret = 0;
432 break;
433 case EN3_CONFIG2:
434 ret = 0x40;
435 break;
436 case EN3_CONFIG3:
437 ret = 0x40;
438 break;
439 default:
440 ret = 0x00;
441 break;
442 }
443 }
444#ifdef DEBUG_NE2000
445 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
446#endif
447 return ret;
448}
449
450static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
451 uint32_t val)
452{
453 if (addr < 32 ||
454 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
455 s->mem[addr] = val;
456 }
457}
458
459static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
460 uint32_t val)
461{
462 addr &= ~1;
463 if (addr < 32 ||
464 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
465 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
466 }
467}
468
469static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
470 uint32_t val)
471{
472 addr &= ~1;
473 if (addr < 32
474 || (addr >= NE2000_PMEM_START
475 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
476 stl_le_p(s->mem + addr, val);
477 }
478}
479
480static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
481{
482 if (addr < 32 ||
483 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
484 return s->mem[addr];
485 } else {
486 return 0xff;
487 }
488}
489
490static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
491{
492 addr &= ~1;
493 if (addr < 32 ||
494 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
495 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
496 } else {
497 return 0xffff;
498 }
499}
500
501static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
502{
503 addr &= ~1;
504 if (addr < 32
505 || (addr >= NE2000_PMEM_START
506 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
507 return ldl_le_p(s->mem + addr);
508 } else {
509 return 0xffffffff;
510 }
511}
512
513static inline void ne2000_dma_update(NE2000State *s, int len)
514{
515 s->rsar += len;
516
517
518 if (s->rsar == s->stop)
519 s->rsar = s->start;
520
521 if (s->rcnt <= len) {
522 s->rcnt = 0;
523
524 s->isr |= ENISR_RDC;
525 ne2000_update_irq(s);
526 } else {
527 s->rcnt -= len;
528 }
529}
530
531static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
532{
533 NE2000State *s = opaque;
534
535#ifdef DEBUG_NE2000
536 printf("NE2000: asic write val=0x%04x\n", val);
537#endif
538 if (s->rcnt == 0)
539 return;
540 if (s->dcfg & 0x01) {
541
542 ne2000_mem_writew(s, s->rsar, val);
543 ne2000_dma_update(s, 2);
544 } else {
545
546 ne2000_mem_writeb(s, s->rsar, val);
547 ne2000_dma_update(s, 1);
548 }
549}
550
551static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
552{
553 NE2000State *s = opaque;
554 int ret;
555
556 if (s->dcfg & 0x01) {
557
558 ret = ne2000_mem_readw(s, s->rsar);
559 ne2000_dma_update(s, 2);
560 } else {
561
562 ret = ne2000_mem_readb(s, s->rsar);
563 ne2000_dma_update(s, 1);
564 }
565#ifdef DEBUG_NE2000
566 printf("NE2000: asic read val=0x%04x\n", ret);
567#endif
568 return ret;
569}
570
571static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
572{
573 NE2000State *s = opaque;
574
575#ifdef DEBUG_NE2000
576 printf("NE2000: asic writel val=0x%04x\n", val);
577#endif
578 if (s->rcnt == 0)
579 return;
580
581 ne2000_mem_writel(s, s->rsar, val);
582 ne2000_dma_update(s, 4);
583}
584
585static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
586{
587 NE2000State *s = opaque;
588 int ret;
589
590
591 ret = ne2000_mem_readl(s, s->rsar);
592 ne2000_dma_update(s, 4);
593#ifdef DEBUG_NE2000
594 printf("NE2000: asic readl val=0x%04x\n", ret);
595#endif
596 return ret;
597}
598
599static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
600{
601
602}
603
604static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
605{
606 NE2000State *s = opaque;
607 ne2000_reset(s);
608 return 0;
609}
610
611static int ne2000_post_load(void* opaque, int version_id)
612{
613 NE2000State* s = opaque;
614
615 if (version_id < 2) {
616 s->rxcr = 0x0c;
617 }
618 return 0;
619}
620
621const VMStateDescription vmstate_ne2000 = {
622 .name = "ne2000",
623 .version_id = 2,
624 .minimum_version_id = 0,
625 .post_load = ne2000_post_load,
626 .fields = (VMStateField[]) {
627 VMSTATE_UINT8_V(rxcr, NE2000State, 2),
628 VMSTATE_UINT8(cmd, NE2000State),
629 VMSTATE_UINT32(start, NE2000State),
630 VMSTATE_UINT32(stop, NE2000State),
631 VMSTATE_UINT8(boundary, NE2000State),
632 VMSTATE_UINT8(tsr, NE2000State),
633 VMSTATE_UINT8(tpsr, NE2000State),
634 VMSTATE_UINT16(tcnt, NE2000State),
635 VMSTATE_UINT16(rcnt, NE2000State),
636 VMSTATE_UINT32(rsar, NE2000State),
637 VMSTATE_UINT8(rsr, NE2000State),
638 VMSTATE_UINT8(isr, NE2000State),
639 VMSTATE_UINT8(dcfg, NE2000State),
640 VMSTATE_UINT8(imr, NE2000State),
641 VMSTATE_BUFFER(phys, NE2000State),
642 VMSTATE_UINT8(curpag, NE2000State),
643 VMSTATE_BUFFER(mult, NE2000State),
644 VMSTATE_UNUSED(4),
645 VMSTATE_BUFFER(mem, NE2000State),
646 VMSTATE_END_OF_LIST()
647 }
648};
649
650static const VMStateDescription vmstate_pci_ne2000 = {
651 .name = "ne2000",
652 .version_id = 3,
653 .minimum_version_id = 3,
654 .fields = (VMStateField[]) {
655 VMSTATE_PCI_DEVICE(dev, PCINE2000State),
656 VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
657 VMSTATE_END_OF_LIST()
658 }
659};
660
661static uint64_t ne2000_read(void *opaque, hwaddr addr,
662 unsigned size)
663{
664 NE2000State *s = opaque;
665
666 if (addr < 0x10 && size == 1) {
667 return ne2000_ioport_read(s, addr);
668 } else if (addr == 0x10) {
669 if (size <= 2) {
670 return ne2000_asic_ioport_read(s, addr);
671 } else {
672 return ne2000_asic_ioport_readl(s, addr);
673 }
674 } else if (addr == 0x1f && size == 1) {
675 return ne2000_reset_ioport_read(s, addr);
676 }
677 return ((uint64_t)1 << (size * 8)) - 1;
678}
679
680static void ne2000_write(void *opaque, hwaddr addr,
681 uint64_t data, unsigned size)
682{
683 NE2000State *s = opaque;
684
685 if (addr < 0x10 && size == 1) {
686 ne2000_ioport_write(s, addr, data);
687 } else if (addr == 0x10) {
688 if (size <= 2) {
689 ne2000_asic_ioport_write(s, addr, data);
690 } else {
691 ne2000_asic_ioport_writel(s, addr, data);
692 }
693 } else if (addr == 0x1f && size == 1) {
694 ne2000_reset_ioport_write(s, addr, data);
695 }
696}
697
698static const MemoryRegionOps ne2000_ops = {
699 .read = ne2000_read,
700 .write = ne2000_write,
701 .endianness = DEVICE_LITTLE_ENDIAN,
702};
703
704
705
706
707void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
708{
709 memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
710}
711
712static NetClientInfo net_ne2000_info = {
713 .type = NET_CLIENT_DRIVER_NIC,
714 .size = sizeof(NICState),
715 .receive = ne2000_receive,
716};
717
718static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp)
719{
720 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
721 NE2000State *s;
722 uint8_t *pci_conf;
723
724 pci_conf = d->dev.config;
725 pci_conf[PCI_INTERRUPT_PIN] = 1;
726
727 s = &d->ne2000;
728 ne2000_setup_io(s, DEVICE(pci_dev), 0x100);
729 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
730 s->irq = pci_allocate_irq(&d->dev);
731
732 qemu_macaddr_default_if_unset(&s->c.macaddr);
733 ne2000_reset(s);
734
735 s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
736 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
737 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
738}
739
740static void pci_ne2000_exit(PCIDevice *pci_dev)
741{
742 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
743 NE2000State *s = &d->ne2000;
744
745 qemu_del_nic(s->nic);
746 qemu_free_irq(s->irq);
747}
748
749static void ne2000_instance_init(Object *obj)
750{
751 PCIDevice *pci_dev = PCI_DEVICE(obj);
752 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
753 NE2000State *s = &d->ne2000;
754
755 device_add_bootindex_property(obj, &s->c.bootindex,
756 "bootindex", "/ethernet-phy@0",
757 &pci_dev->qdev, NULL);
758}
759
760static Property ne2000_properties[] = {
761 DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
762 DEFINE_PROP_END_OF_LIST(),
763};
764
765static void ne2000_class_init(ObjectClass *klass, void *data)
766{
767 DeviceClass *dc = DEVICE_CLASS(klass);
768 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
769
770 k->realize = pci_ne2000_realize;
771 k->exit = pci_ne2000_exit;
772 k->romfile = "efi-ne2k_pci.rom",
773 k->vendor_id = PCI_VENDOR_ID_REALTEK;
774 k->device_id = PCI_DEVICE_ID_REALTEK_8029;
775 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
776 dc->vmsd = &vmstate_pci_ne2000;
777 dc->props = ne2000_properties;
778 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
779}
780
781static const TypeInfo ne2000_info = {
782 .name = "ne2k_pci",
783 .parent = TYPE_PCI_DEVICE,
784 .instance_size = sizeof(PCINE2000State),
785 .class_init = ne2000_class_init,
786 .instance_init = ne2000_instance_init,
787 .interfaces = (InterfaceInfo[]) {
788 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
789 { },
790 },
791};
792
793static void ne2000_register_types(void)
794{
795 type_register_static(&ne2000_info);
796}
797
798type_init(ne2000_register_types)
799