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30#include "qemu/osdep.h"
31#include "hw/pci/pci.h"
32#include "net/net.h"
33#include "qemu/timer.h"
34#include "sysemu/dma.h"
35#include "sysemu/sysemu.h"
36#include "trace.h"
37
38#include "pcnet.h"
39
40
41
42
43
44
45
46
47
48#define TYPE_PCI_PCNET "pcnet"
49
50#define PCI_PCNET(obj) \
51 OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
52
53typedef struct {
54
55 PCIDevice parent_obj;
56
57
58 PCNetState state;
59 MemoryRegion io_bar;
60} PCIPCNetState;
61
62static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
63{
64 PCNetState *s = opaque;
65
66 trace_pcnet_aprom_writeb(opaque, addr, val);
67 if (BCR_APROMWE(s)) {
68 s->prom[addr & 15] = val;
69 }
70}
71
72static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
73{
74 PCNetState *s = opaque;
75 uint32_t val = s->prom[addr & 15];
76
77 trace_pcnet_aprom_readb(opaque, addr, val);
78 return val;
79}
80
81static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
82 unsigned size)
83{
84 PCNetState *d = opaque;
85
86 trace_pcnet_ioport_read(opaque, addr, size);
87 if (addr < 0x10) {
88 if (!BCR_DWIO(d) && size == 1) {
89 return pcnet_aprom_readb(d, addr);
90 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
91 return pcnet_aprom_readb(d, addr) |
92 (pcnet_aprom_readb(d, addr + 1) << 8);
93 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
94 return pcnet_aprom_readb(d, addr) |
95 (pcnet_aprom_readb(d, addr + 1) << 8) |
96 (pcnet_aprom_readb(d, addr + 2) << 16) |
97 (pcnet_aprom_readb(d, addr + 3) << 24);
98 }
99 } else {
100 if (size == 2) {
101 return pcnet_ioport_readw(d, addr);
102 } else if (size == 4) {
103 return pcnet_ioport_readl(d, addr);
104 }
105 }
106 return ((uint64_t)1 << (size * 8)) - 1;
107}
108
109static void pcnet_ioport_write(void *opaque, hwaddr addr,
110 uint64_t data, unsigned size)
111{
112 PCNetState *d = opaque;
113
114 trace_pcnet_ioport_write(opaque, addr, data, size);
115 if (addr < 0x10) {
116 if (!BCR_DWIO(d) && size == 1) {
117 pcnet_aprom_writeb(d, addr, data);
118 } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
119 pcnet_aprom_writeb(d, addr, data & 0xff);
120 pcnet_aprom_writeb(d, addr + 1, data >> 8);
121 } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
122 pcnet_aprom_writeb(d, addr, data & 0xff);
123 pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
124 pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
125 pcnet_aprom_writeb(d, addr + 3, data >> 24);
126 }
127 } else {
128 if (size == 2) {
129 pcnet_ioport_writew(d, addr, data);
130 } else if (size == 4) {
131 pcnet_ioport_writel(d, addr, data);
132 }
133 }
134}
135
136static const MemoryRegionOps pcnet_io_ops = {
137 .read = pcnet_ioport_read,
138 .write = pcnet_ioport_write,
139 .endianness = DEVICE_LITTLE_ENDIAN,
140};
141
142static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
143{
144 PCNetState *d = opaque;
145
146 trace_pcnet_mmio_writeb(opaque, addr, val);
147 if (!(addr & 0x10))
148 pcnet_aprom_writeb(d, addr & 0x0f, val);
149}
150
151static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
152{
153 PCNetState *d = opaque;
154 uint32_t val = -1;
155
156 if (!(addr & 0x10))
157 val = pcnet_aprom_readb(d, addr & 0x0f);
158 trace_pcnet_mmio_readb(opaque, addr, val);
159 return val;
160}
161
162static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
163{
164 PCNetState *d = opaque;
165
166 trace_pcnet_mmio_writew(opaque, addr, val);
167 if (addr & 0x10)
168 pcnet_ioport_writew(d, addr & 0x0f, val);
169 else {
170 addr &= 0x0f;
171 pcnet_aprom_writeb(d, addr, val & 0xff);
172 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
173 }
174}
175
176static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
177{
178 PCNetState *d = opaque;
179 uint32_t val = -1;
180
181 if (addr & 0x10)
182 val = pcnet_ioport_readw(d, addr & 0x0f);
183 else {
184 addr &= 0x0f;
185 val = pcnet_aprom_readb(d, addr+1);
186 val <<= 8;
187 val |= pcnet_aprom_readb(d, addr);
188 }
189 trace_pcnet_mmio_readw(opaque, addr, val);
190 return val;
191}
192
193static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
194{
195 PCNetState *d = opaque;
196
197 trace_pcnet_mmio_writel(opaque, addr, val);
198 if (addr & 0x10)
199 pcnet_ioport_writel(d, addr & 0x0f, val);
200 else {
201 addr &= 0x0f;
202 pcnet_aprom_writeb(d, addr, val & 0xff);
203 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
204 pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
205 pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
206 }
207}
208
209static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
210{
211 PCNetState *d = opaque;
212 uint32_t val;
213
214 if (addr & 0x10)
215 val = pcnet_ioport_readl(d, addr & 0x0f);
216 else {
217 addr &= 0x0f;
218 val = pcnet_aprom_readb(d, addr+3);
219 val <<= 8;
220 val |= pcnet_aprom_readb(d, addr+2);
221 val <<= 8;
222 val |= pcnet_aprom_readb(d, addr+1);
223 val <<= 8;
224 val |= pcnet_aprom_readb(d, addr);
225 }
226 trace_pcnet_mmio_readl(opaque, addr, val);
227 return val;
228}
229
230static const VMStateDescription vmstate_pci_pcnet = {
231 .name = "pcnet",
232 .version_id = 3,
233 .minimum_version_id = 2,
234 .fields = (VMStateField[]) {
235 VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
236 VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
237 VMSTATE_END_OF_LIST()
238 }
239};
240
241
242
243static const MemoryRegionOps pcnet_mmio_ops = {
244 .old_mmio = {
245 .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
246 .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
247 },
248 .endianness = DEVICE_LITTLE_ENDIAN,
249};
250
251static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
252 uint8_t *buf, int len, int do_bswap)
253{
254 pci_dma_write(dma_opaque, addr, buf, len);
255}
256
257static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
258 uint8_t *buf, int len, int do_bswap)
259{
260 pci_dma_read(dma_opaque, addr, buf, len);
261}
262
263static void pci_pcnet_uninit(PCIDevice *dev)
264{
265 PCIPCNetState *d = PCI_PCNET(dev);
266
267 qemu_free_irq(d->state.irq);
268 timer_del(d->state.poll_timer);
269 timer_free(d->state.poll_timer);
270 qemu_del_nic(d->state.nic);
271}
272
273static NetClientInfo net_pci_pcnet_info = {
274 .type = NET_CLIENT_DRIVER_NIC,
275 .size = sizeof(NICState),
276 .receive = pcnet_receive,
277 .link_status_changed = pcnet_set_link_status,
278};
279
280static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
281{
282 PCIPCNetState *d = PCI_PCNET(pci_dev);
283 PCNetState *s = &d->state;
284 uint8_t *pci_conf;
285
286#if 0
287 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
288 sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
289#endif
290
291 pci_conf = pci_dev->config;
292
293 pci_set_word(pci_conf + PCI_STATUS,
294 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
295
296 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
297 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
298
299 pci_conf[PCI_INTERRUPT_PIN] = 1;
300 pci_conf[PCI_MIN_GNT] = 0x06;
301 pci_conf[PCI_MAX_LAT] = 0xff;
302
303
304 memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
305 "pcnet-mmio", PCNET_PNPMMIO_SIZE);
306
307 memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
308 PCNET_IOPORT_SIZE);
309 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
310
311 pci_register_bar(pci_dev, 1, 0, &s->mmio);
312
313 s->irq = pci_allocate_irq(pci_dev);
314 s->phys_mem_read = pci_physical_memory_read;
315 s->phys_mem_write = pci_physical_memory_write;
316 s->dma_opaque = pci_dev;
317
318 pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
319}
320
321static void pci_reset(DeviceState *dev)
322{
323 PCIPCNetState *d = PCI_PCNET(dev);
324
325 pcnet_h_reset(&d->state);
326}
327
328static void pcnet_instance_init(Object *obj)
329{
330 PCIPCNetState *d = PCI_PCNET(obj);
331 PCNetState *s = &d->state;
332
333 device_add_bootindex_property(obj, &s->conf.bootindex,
334 "bootindex", "/ethernet-phy@0",
335 DEVICE(obj), NULL);
336}
337
338static Property pcnet_properties[] = {
339 DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
340 DEFINE_PROP_END_OF_LIST(),
341};
342
343static void pcnet_class_init(ObjectClass *klass, void *data)
344{
345 DeviceClass *dc = DEVICE_CLASS(klass);
346 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
347
348 k->realize = pci_pcnet_realize;
349 k->exit = pci_pcnet_uninit;
350 k->romfile = "efi-pcnet.rom",
351 k->vendor_id = PCI_VENDOR_ID_AMD;
352 k->device_id = PCI_DEVICE_ID_AMD_LANCE;
353 k->revision = 0x10;
354 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
355 dc->reset = pci_reset;
356 dc->vmsd = &vmstate_pci_pcnet;
357 dc->props = pcnet_properties;
358 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
359}
360
361static const TypeInfo pcnet_info = {
362 .name = TYPE_PCI_PCNET,
363 .parent = TYPE_PCI_DEVICE,
364 .instance_size = sizeof(PCIPCNetState),
365 .class_init = pcnet_class_init,
366 .instance_init = pcnet_instance_init,
367 .interfaces = (InterfaceInfo[]) {
368 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
369 { },
370 },
371};
372
373static void pci_pcnet_register_types(void)
374{
375 type_register_static(&pcnet_info);
376}
377
378type_init(pci_pcnet_register_types)
379
