1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu-common.h"
28#include "cpu.h"
29
30#include "hw/sysbus.h"
31#include "hw/hw.h"
32#include "hw/char/serial.h"
33#include "sysemu/sysemu.h"
34#include "hw/boards.h"
35#include "exec/memory.h"
36#include "exec/address-spaces.h"
37#include "qemu/config-file.h"
38
39#include "boot.h"
40
41#define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb"
42
43static void nios2_10m50_ghrd_init(MachineState *machine)
44{
45 Nios2CPU *cpu;
46 DeviceState *dev;
47 MemoryRegion *address_space_mem = get_system_memory();
48 MemoryRegion *phys_tcm = g_new(MemoryRegion, 1);
49 MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1);
50 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
51 MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1);
52 ram_addr_t tcm_base = 0x0;
53 ram_addr_t tcm_size = 0x1000;
54 ram_addr_t ram_base = 0x08000000;
55 ram_addr_t ram_size = 0x08000000;
56 qemu_irq *cpu_irq, irq[32];
57 int i;
58
59
60 memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size,
61 &error_abort);
62 memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias",
63 phys_tcm, 0, tcm_size);
64 memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm);
65 memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base,
66 phys_tcm_alias);
67
68
69 memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size,
70 &error_abort);
71 memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias",
72 phys_ram, 0, ram_size);
73 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
74 memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
75 phys_ram_alias);
76
77
78 cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
79
80
81 cpu_irq = nios2_cpu_pic_init(cpu);
82
83
84 dev = qdev_create(NULL, "altera,iic");
85 object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu),
86 &error_abort);
87 qdev_init_nofail(dev);
88 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
89 for (i = 0; i < 32; i++) {
90 irq[i] = qdev_get_gpio_in(dev, i);
91 }
92
93
94 serial_mm_init(address_space_mem, 0xf8001600, 2, irq[1], 115200,
95 serial_hds[0], DEVICE_NATIVE_ENDIAN);
96
97
98 dev = qdev_create(NULL, "ALTR.timer");
99 qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
100 qdev_init_nofail(dev);
101 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440);
102 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]);
103
104
105 dev = qdev_create(NULL, "ALTR.timer");
106 qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
107 qdev_init_nofail(dev);
108 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
109 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
110
111
112 cpu->reset_addr = 0xd4000000;
113 cpu->exception_addr = 0xc8000120;
114 cpu->fast_tlb_miss_addr = 0xc0000100;
115
116 nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
117 BINARY_DEVICE_TREE_FILE, NULL);
118}
119
120static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc)
121{
122 mc->desc = "Altera 10M50 GHRD Nios II design";
123 mc->init = nios2_10m50_ghrd_init;
124 mc->is_default = 1;
125}
126
127DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init);
128