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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "sysemu/sysemu.h"
28#include "sysemu/dma.h"
29#include "hw/boards.h"
30#include "hw/isa/isa.h"
31#include "hw/nvram/fw_cfg.h"
32#include "hw/sysbus.h"
33#include "trace.h"
34#include "qemu/error-report.h"
35#include "qemu/option.h"
36#include "qemu/config-file.h"
37#include "qemu/cutils.h"
38#include "qapi/error.h"
39
40#define FW_CFG_FILE_SLOTS_DFLT 0x20
41
42
43#define FW_CFG_VERSION 0x01
44#define FW_CFG_VERSION_DMA 0x02
45
46
47#define FW_CFG_DMA_CTL_ERROR 0x01
48#define FW_CFG_DMA_CTL_READ 0x02
49#define FW_CFG_DMA_CTL_SKIP 0x04
50#define FW_CFG_DMA_CTL_SELECT 0x08
51#define FW_CFG_DMA_CTL_WRITE 0x10
52
53#define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL
54
55struct FWCfgEntry {
56 uint32_t len;
57 bool allow_write;
58 uint8_t *data;
59 void *callback_opaque;
60 FWCfgCallback select_cb;
61 FWCfgWriteCallback write_cb;
62};
63
64#define JPG_FILE 0
65#define BMP_FILE 1
66
67static char *read_splashfile(char *filename, gsize *file_sizep,
68 int *file_typep)
69{
70 GError *err = NULL;
71 gboolean res;
72 gchar *content;
73 int file_type;
74 unsigned int filehead;
75 int bmp_bpp;
76
77 res = g_file_get_contents(filename, &content, file_sizep, &err);
78 if (res == FALSE) {
79 error_report("failed to read splash file '%s'", filename);
80 g_error_free(err);
81 return NULL;
82 }
83
84
85 if (*file_sizep < 30) {
86 goto error;
87 }
88
89
90 filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff;
91 if (filehead == 0xd8ff) {
92 file_type = JPG_FILE;
93 } else if (filehead == 0x4d42) {
94 file_type = BMP_FILE;
95 } else {
96 goto error;
97 }
98
99
100 if (file_type == BMP_FILE) {
101 bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff;
102 if (bmp_bpp != 24) {
103 goto error;
104 }
105 }
106
107
108 *file_typep = file_type;
109
110 return content;
111
112error:
113 error_report("splash file '%s' format not recognized; must be JPEG "
114 "or 24 bit BMP", filename);
115 g_free(content);
116 return NULL;
117}
118
119static void fw_cfg_bootsplash(FWCfgState *s)
120{
121 int boot_splash_time = -1;
122 const char *boot_splash_filename = NULL;
123 char *p;
124 char *filename, *file_data;
125 gsize file_size;
126 int file_type;
127 const char *temp;
128
129
130 QemuOptsList *plist = qemu_find_opts("boot-opts");
131 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
132 if (opts != NULL) {
133 temp = qemu_opt_get(opts, "splash");
134 if (temp != NULL) {
135 boot_splash_filename = temp;
136 }
137 temp = qemu_opt_get(opts, "splash-time");
138 if (temp != NULL) {
139 p = (char *)temp;
140 boot_splash_time = strtol(p, &p, 10);
141 }
142 }
143
144
145 if (boot_splash_time >= 0) {
146
147 if (boot_splash_time > 0xffff) {
148 error_report("splash time is big than 65535, force it to 65535.");
149 boot_splash_time = 0xffff;
150 }
151
152 qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff);
153 qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff);
154 fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2);
155 }
156
157
158 if (boot_splash_filename != NULL) {
159 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
160 if (filename == NULL) {
161 error_report("failed to find file '%s'.", boot_splash_filename);
162 return;
163 }
164
165
166 file_data = read_splashfile(filename, &file_size, &file_type);
167 if (file_data == NULL) {
168 g_free(filename);
169 return;
170 }
171 g_free(boot_splash_filedata);
172 boot_splash_filedata = (uint8_t *)file_data;
173 boot_splash_filedata_size = file_size;
174
175
176 if (file_type == JPG_FILE) {
177 fw_cfg_add_file(s, "bootsplash.jpg",
178 boot_splash_filedata, boot_splash_filedata_size);
179 } else {
180 fw_cfg_add_file(s, "bootsplash.bmp",
181 boot_splash_filedata, boot_splash_filedata_size);
182 }
183 g_free(filename);
184 }
185}
186
187static void fw_cfg_reboot(FWCfgState *s)
188{
189 int reboot_timeout = -1;
190 char *p;
191 const char *temp;
192
193
194 QemuOptsList *plist = qemu_find_opts("boot-opts");
195 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
196 if (opts != NULL) {
197 temp = qemu_opt_get(opts, "reboot-timeout");
198 if (temp != NULL) {
199 p = (char *)temp;
200 reboot_timeout = strtol(p, &p, 10);
201 }
202 }
203
204 if (reboot_timeout > 0xffff) {
205 error_report("reboot timeout is larger than 65535, force it to 65535.");
206 reboot_timeout = 0xffff;
207 }
208 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4);
209}
210
211static void fw_cfg_write(FWCfgState *s, uint8_t value)
212{
213
214}
215
216static inline uint16_t fw_cfg_file_slots(const FWCfgState *s)
217{
218 return s->file_slots;
219}
220
221
222static inline uint32_t fw_cfg_max_entry(const FWCfgState *s)
223{
224 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s);
225}
226
227static int fw_cfg_select(FWCfgState *s, uint16_t key)
228{
229 int arch, ret;
230 FWCfgEntry *e;
231
232 s->cur_offset = 0;
233 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) {
234 s->cur_entry = FW_CFG_INVALID;
235 ret = 0;
236 } else {
237 s->cur_entry = key;
238 ret = 1;
239
240 arch = !!(key & FW_CFG_ARCH_LOCAL);
241 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK];
242 if (e->select_cb) {
243 e->select_cb(e->callback_opaque);
244 }
245 }
246
247 trace_fw_cfg_select(s, key, ret);
248 return ret;
249}
250
251static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size)
252{
253 FWCfgState *s = opaque;
254 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
255 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
256 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
257 uint64_t value = 0;
258
259 assert(size > 0 && size <= sizeof(value));
260 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) {
261
262
263
264
265
266
267 do {
268 value = (value << 8) | e->data[s->cur_offset++];
269 } while (--size && s->cur_offset < e->len);
270
271
272
273
274 value <<= 8 * size;
275 }
276
277 trace_fw_cfg_read(s, value);
278 return value;
279}
280
281static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
282 uint64_t value, unsigned size)
283{
284 FWCfgState *s = opaque;
285 unsigned i = size;
286
287 do {
288 fw_cfg_write(s, value >> (8 * --i));
289 } while (i);
290}
291
292static void fw_cfg_dma_transfer(FWCfgState *s)
293{
294 dma_addr_t len;
295 FWCfgDmaAccess dma;
296 int arch;
297 FWCfgEntry *e;
298 int read = 0, write = 0;
299 dma_addr_t dma_addr;
300
301
302 dma_addr = s->dma_addr;
303 s->dma_addr = 0;
304
305 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
306 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
307 FW_CFG_DMA_CTL_ERROR);
308 return;
309 }
310
311 dma.address = be64_to_cpu(dma.address);
312 dma.length = be32_to_cpu(dma.length);
313 dma.control = be32_to_cpu(dma.control);
314
315 if (dma.control & FW_CFG_DMA_CTL_SELECT) {
316 fw_cfg_select(s, dma.control >> 16);
317 }
318
319 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
320 e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
321 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
322
323 if (dma.control & FW_CFG_DMA_CTL_READ) {
324 read = 1;
325 write = 0;
326 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) {
327 read = 0;
328 write = 1;
329 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
330 read = 0;
331 write = 0;
332 } else {
333 dma.length = 0;
334 }
335
336 dma.control = 0;
337
338 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
339 if (s->cur_entry == FW_CFG_INVALID || !e->data ||
340 s->cur_offset >= e->len) {
341 len = dma.length;
342
343
344
345
346 if (read) {
347 if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
348 dma.control |= FW_CFG_DMA_CTL_ERROR;
349 }
350 }
351 if (write) {
352 dma.control |= FW_CFG_DMA_CTL_ERROR;
353 }
354 } else {
355 if (dma.length <= (e->len - s->cur_offset)) {
356 len = dma.length;
357 } else {
358 len = (e->len - s->cur_offset);
359 }
360
361
362
363
364 if (read) {
365 if (dma_memory_write(s->dma_as, dma.address,
366 &e->data[s->cur_offset], len)) {
367 dma.control |= FW_CFG_DMA_CTL_ERROR;
368 }
369 }
370 if (write) {
371 if (!e->allow_write ||
372 len != dma.length ||
373 dma_memory_read(s->dma_as, dma.address,
374 &e->data[s->cur_offset], len)) {
375 dma.control |= FW_CFG_DMA_CTL_ERROR;
376 } else if (e->write_cb) {
377 e->write_cb(e->callback_opaque, s->cur_offset, len);
378 }
379 }
380
381 s->cur_offset += len;
382 }
383
384 dma.address += len;
385 dma.length -= len;
386
387 }
388
389 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
390 dma.control);
391
392 trace_fw_cfg_read(s, 0);
393}
394
395static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
396 unsigned size)
397{
398
399 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
400}
401
402static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
403 uint64_t value, unsigned size)
404{
405 FWCfgState *s = opaque;
406
407 if (size == 4) {
408 if (addr == 0) {
409
410 s->dma_addr = value << 32;
411 } else if (addr == 4) {
412
413 s->dma_addr |= value;
414 fw_cfg_dma_transfer(s);
415 }
416 } else if (size == 8 && addr == 0) {
417 s->dma_addr = value;
418 fw_cfg_dma_transfer(s);
419 }
420}
421
422static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
423 unsigned size, bool is_write)
424{
425 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
426 (size == 8 && addr == 0));
427}
428
429static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
430 unsigned size, bool is_write)
431{
432 return addr == 0;
433}
434
435static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
436 uint64_t value, unsigned size)
437{
438 fw_cfg_select(opaque, (uint16_t)value);
439}
440
441static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
442 unsigned size, bool is_write)
443{
444 return is_write && size == 2;
445}
446
447static void fw_cfg_comb_write(void *opaque, hwaddr addr,
448 uint64_t value, unsigned size)
449{
450 switch (size) {
451 case 1:
452 fw_cfg_write(opaque, (uint8_t)value);
453 break;
454 case 2:
455 fw_cfg_select(opaque, (uint16_t)value);
456 break;
457 }
458}
459
460static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
461 unsigned size, bool is_write)
462{
463 return (size == 1) || (is_write && size == 2);
464}
465
466static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
467 .write = fw_cfg_ctl_mem_write,
468 .endianness = DEVICE_BIG_ENDIAN,
469 .valid.accepts = fw_cfg_ctl_mem_valid,
470};
471
472static const MemoryRegionOps fw_cfg_data_mem_ops = {
473 .read = fw_cfg_data_read,
474 .write = fw_cfg_data_mem_write,
475 .endianness = DEVICE_BIG_ENDIAN,
476 .valid = {
477 .min_access_size = 1,
478 .max_access_size = 1,
479 .accepts = fw_cfg_data_mem_valid,
480 },
481};
482
483static const MemoryRegionOps fw_cfg_comb_mem_ops = {
484 .read = fw_cfg_data_read,
485 .write = fw_cfg_comb_write,
486 .endianness = DEVICE_LITTLE_ENDIAN,
487 .valid.accepts = fw_cfg_comb_valid,
488};
489
490static const MemoryRegionOps fw_cfg_dma_mem_ops = {
491 .read = fw_cfg_dma_mem_read,
492 .write = fw_cfg_dma_mem_write,
493 .endianness = DEVICE_BIG_ENDIAN,
494 .valid.accepts = fw_cfg_dma_mem_valid,
495 .valid.max_access_size = 8,
496 .impl.max_access_size = 8,
497};
498
499static void fw_cfg_reset(DeviceState *d)
500{
501 FWCfgState *s = FW_CFG(d);
502
503
504 fw_cfg_select(s, FW_CFG_SIGNATURE);
505}
506
507
508
509
510
511
512static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size,
513 VMStateField *field)
514{
515 uint32_t *v = pv;
516 *v = qemu_get_be16(f);
517 return 0;
518}
519
520static int put_unused(QEMUFile *f, void *pv, size_t size, VMStateField *field,
521 QJSON *vmdesc)
522{
523 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
524 fprintf(stderr, "This functions shouldn't be called.\n");
525
526 return 0;
527}
528
529static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
530 .name = "int32_as_uint16",
531 .get = get_uint32_as_uint16,
532 .put = put_unused,
533};
534
535#define VMSTATE_UINT16_HACK(_f, _s, _t) \
536 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
537
538
539static bool is_version_1(void *opaque, int version_id)
540{
541 return version_id == 1;
542}
543
544bool fw_cfg_dma_enabled(void *opaque)
545{
546 FWCfgState *s = opaque;
547
548 return s->dma_enabled;
549}
550
551static const VMStateDescription vmstate_fw_cfg_dma = {
552 .name = "fw_cfg/dma",
553 .needed = fw_cfg_dma_enabled,
554 .fields = (VMStateField[]) {
555 VMSTATE_UINT64(dma_addr, FWCfgState),
556 VMSTATE_END_OF_LIST()
557 },
558};
559
560static const VMStateDescription vmstate_fw_cfg = {
561 .name = "fw_cfg",
562 .version_id = 2,
563 .minimum_version_id = 1,
564 .fields = (VMStateField[]) {
565 VMSTATE_UINT16(cur_entry, FWCfgState),
566 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
567 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
568 VMSTATE_END_OF_LIST()
569 },
570 .subsections = (const VMStateDescription*[]) {
571 &vmstate_fw_cfg_dma,
572 NULL,
573 }
574};
575
576static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key,
577 FWCfgCallback select_cb,
578 FWCfgWriteCallback write_cb,
579 void *callback_opaque,
580 void *data, size_t len,
581 bool read_only)
582{
583 int arch = !!(key & FW_CFG_ARCH_LOCAL);
584
585 key &= FW_CFG_ENTRY_MASK;
586
587 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
588 assert(s->entries[arch][key].data == NULL);
589
590 s->entries[arch][key].data = data;
591 s->entries[arch][key].len = (uint32_t)len;
592 s->entries[arch][key].select_cb = select_cb;
593 s->entries[arch][key].write_cb = write_cb;
594 s->entries[arch][key].callback_opaque = callback_opaque;
595 s->entries[arch][key].allow_write = !read_only;
596}
597
598static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
599 void *data, size_t len)
600{
601 void *ptr;
602 int arch = !!(key & FW_CFG_ARCH_LOCAL);
603
604 key &= FW_CFG_ENTRY_MASK;
605
606 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
607
608
609 ptr = s->entries[arch][key].data;
610 s->entries[arch][key].data = data;
611 s->entries[arch][key].len = len;
612 s->entries[arch][key].callback_opaque = NULL;
613 s->entries[arch][key].allow_write = false;
614
615 return ptr;
616}
617
618void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
619{
620 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true);
621}
622
623void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
624{
625 size_t sz = strlen(value) + 1;
626
627 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
628}
629
630void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
631{
632 uint16_t *copy;
633
634 copy = g_malloc(sizeof(value));
635 *copy = cpu_to_le16(value);
636 fw_cfg_add_bytes(s, key, copy, sizeof(value));
637}
638
639void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
640{
641 uint16_t *copy, *old;
642
643 copy = g_malloc(sizeof(value));
644 *copy = cpu_to_le16(value);
645 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
646 g_free(old);
647}
648
649void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
650{
651 uint32_t *copy;
652
653 copy = g_malloc(sizeof(value));
654 *copy = cpu_to_le32(value);
655 fw_cfg_add_bytes(s, key, copy, sizeof(value));
656}
657
658void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
659{
660 uint64_t *copy;
661
662 copy = g_malloc(sizeof(value));
663 *copy = cpu_to_le64(value);
664 fw_cfg_add_bytes(s, key, copy, sizeof(value));
665}
666
667void fw_cfg_set_order_override(FWCfgState *s, int order)
668{
669 assert(s->fw_cfg_order_override == 0);
670 s->fw_cfg_order_override = order;
671}
672
673void fw_cfg_reset_order_override(FWCfgState *s)
674{
675 assert(s->fw_cfg_order_override != 0);
676 s->fw_cfg_order_override = 0;
677}
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693static struct {
694 const char *name;
695 int order;
696} fw_cfg_order[] = {
697 { "etc/boot-menu-wait", 10 },
698 { "bootsplash.jpg", 11 },
699 { "bootsplash.bmp", 12 },
700 { "etc/boot-fail-wait", 15 },
701 { "etc/smbios/smbios-tables", 20 },
702 { "etc/smbios/smbios-anchor", 30 },
703 { "etc/e820", 40 },
704 { "etc/reserved-memory-end", 50 },
705 { "genroms/kvmvapic.bin", 55 },
706 { "genroms/linuxboot.bin", 60 },
707 { },
708 { },
709 { "etc/system-states", 90 },
710 { },
711 { },
712 { "etc/extra-pci-roots", 120 },
713 { "etc/acpi/tables", 130 },
714 { "etc/table-loader", 140 },
715 { "etc/tpm/log", 150 },
716 { "etc/acpi/rsdp", 160 },
717 { "bootorder", 170 },
718
719#define FW_CFG_ORDER_OVERRIDE_LAST 200
720};
721
722static int get_fw_cfg_order(FWCfgState *s, const char *name)
723{
724 int i;
725
726 if (s->fw_cfg_order_override > 0) {
727 return s->fw_cfg_order_override;
728 }
729
730 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
731 if (fw_cfg_order[i].name == NULL) {
732 continue;
733 }
734
735 if (strcmp(name, fw_cfg_order[i].name) == 0) {
736 return fw_cfg_order[i].order;
737 }
738 }
739
740
741 warn_report("Unknown firmware file in legacy mode: %s", name);
742 return FW_CFG_ORDER_OVERRIDE_LAST;
743}
744
745void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
746 FWCfgCallback select_cb,
747 FWCfgWriteCallback write_cb,
748 void *callback_opaque,
749 void *data, size_t len, bool read_only)
750{
751 int i, index, count;
752 size_t dsize;
753 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
754 int order = 0;
755
756 if (!s->files) {
757 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s);
758 s->files = g_malloc0(dsize);
759 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
760 }
761
762 count = be32_to_cpu(s->files->count);
763 assert(count < fw_cfg_file_slots(s));
764
765
766 if (mc->legacy_fw_cfg_order) {
767
768
769
770
771 order = get_fw_cfg_order(s, filename);
772 for (index = count;
773 index > 0 && order < s->entry_order[index - 1];
774 index--);
775 } else {
776
777 for (index = count;
778 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
779 index--);
780 }
781
782
783
784
785
786
787
788
789 for (i = count; i > index; i--) {
790 s->files->f[i] = s->files->f[i - 1];
791 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i);
792 s->entries[0][FW_CFG_FILE_FIRST + i] =
793 s->entries[0][FW_CFG_FILE_FIRST + i - 1];
794 s->entry_order[i] = s->entry_order[i - 1];
795 }
796
797 memset(&s->files->f[index], 0, sizeof(FWCfgFile));
798 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry));
799
800 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename);
801 for (i = 0; i <= count; i++) {
802 if (i != index &&
803 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
804 error_report("duplicate fw_cfg file name: %s",
805 s->files->f[index].name);
806 exit(1);
807 }
808 }
809
810 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index,
811 select_cb, write_cb,
812 callback_opaque, data, len,
813 read_only);
814
815 s->files->f[index].size = cpu_to_be32(len);
816 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
817 s->entry_order[index] = order;
818 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
819
820 s->files->count = cpu_to_be32(count+1);
821}
822
823void fw_cfg_add_file(FWCfgState *s, const char *filename,
824 void *data, size_t len)
825{
826 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
827}
828
829void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
830 void *data, size_t len)
831{
832 int i, index;
833 void *ptr = NULL;
834
835 assert(s->files);
836
837 index = be32_to_cpu(s->files->count);
838
839 for (i = 0; i < index; i++) {
840 if (strcmp(filename, s->files->f[i].name) == 0) {
841 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
842 data, len);
843 s->files->f[i].size = cpu_to_be32(len);
844 return ptr;
845 }
846 }
847
848 assert(index < fw_cfg_file_slots(s));
849
850
851 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
852 return NULL;
853}
854
855static void fw_cfg_machine_reset(void *opaque)
856{
857 void *ptr;
858 size_t len;
859 FWCfgState *s = opaque;
860 char *bootindex = get_boot_devices_list(&len, false);
861
862 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len);
863 g_free(ptr);
864}
865
866static void fw_cfg_machine_ready(struct Notifier *n, void *data)
867{
868 FWCfgState *s = container_of(n, FWCfgState, machine_ready);
869 qemu_register_reset(fw_cfg_machine_reset, s);
870}
871
872
873
874static void fw_cfg_common_realize(DeviceState *dev, Error **errp)
875{
876 FWCfgState *s = FW_CFG(dev);
877 MachineState *machine = MACHINE(qdev_get_machine());
878 uint32_t version = FW_CFG_VERSION;
879
880 if (!fw_cfg_find()) {
881 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG);
882 return;
883 }
884
885 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
886 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16);
887 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics);
888 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
889 fw_cfg_bootsplash(s);
890 fw_cfg_reboot(s);
891
892 if (s->dma_enabled) {
893 version |= FW_CFG_VERSION_DMA;
894 }
895
896 fw_cfg_add_i32(s, FW_CFG_ID, version);
897
898 s->machine_ready.notify = fw_cfg_machine_ready;
899 qemu_add_machine_init_done_notifier(&s->machine_ready);
900}
901
902FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
903 AddressSpace *dma_as)
904{
905 DeviceState *dev;
906 SysBusDevice *sbd;
907 FWCfgIoState *ios;
908 FWCfgState *s;
909 bool dma_requested = dma_iobase && dma_as;
910
911 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
912 if (!dma_requested) {
913 qdev_prop_set_bit(dev, "dma_enabled", false);
914 }
915
916 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
917 OBJECT(dev), NULL);
918 qdev_init_nofail(dev);
919
920 sbd = SYS_BUS_DEVICE(dev);
921 ios = FW_CFG_IO(dev);
922 sysbus_add_io(sbd, iobase, &ios->comb_iomem);
923
924 s = FW_CFG(dev);
925
926 if (s->dma_enabled) {
927
928 s->dma_as = dma_as;
929 s->dma_addr = 0;
930 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem);
931 }
932
933 return s;
934}
935
936FWCfgState *fw_cfg_init_io(uint32_t iobase)
937{
938 return fw_cfg_init_io_dma(iobase, 0, NULL);
939}
940
941FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
942 hwaddr data_addr, uint32_t data_width,
943 hwaddr dma_addr, AddressSpace *dma_as)
944{
945 DeviceState *dev;
946 SysBusDevice *sbd;
947 FWCfgState *s;
948 bool dma_requested = dma_addr && dma_as;
949
950 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
951 qdev_prop_set_uint32(dev, "data_width", data_width);
952 if (!dma_requested) {
953 qdev_prop_set_bit(dev, "dma_enabled", false);
954 }
955
956 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
957 OBJECT(dev), NULL);
958 qdev_init_nofail(dev);
959
960 sbd = SYS_BUS_DEVICE(dev);
961 sysbus_mmio_map(sbd, 0, ctl_addr);
962 sysbus_mmio_map(sbd, 1, data_addr);
963
964 s = FW_CFG(dev);
965
966 if (s->dma_enabled) {
967 s->dma_as = dma_as;
968 s->dma_addr = 0;
969 sysbus_mmio_map(sbd, 2, dma_addr);
970 }
971
972 return s;
973}
974
975FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
976{
977 return fw_cfg_init_mem_wide(ctl_addr, data_addr,
978 fw_cfg_data_mem_ops.valid.max_access_size,
979 0, NULL);
980}
981
982
983FWCfgState *fw_cfg_find(void)
984{
985
986 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
987}
988
989
990static void fw_cfg_class_init(ObjectClass *klass, void *data)
991{
992 DeviceClass *dc = DEVICE_CLASS(klass);
993
994 dc->reset = fw_cfg_reset;
995 dc->vmsd = &vmstate_fw_cfg;
996}
997
998static const TypeInfo fw_cfg_info = {
999 .name = TYPE_FW_CFG,
1000 .parent = TYPE_SYS_BUS_DEVICE,
1001 .abstract = true,
1002 .instance_size = sizeof(FWCfgState),
1003 .class_init = fw_cfg_class_init,
1004};
1005
1006static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp)
1007{
1008 uint16_t file_slots_max;
1009
1010 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) {
1011 error_setg(errp, "\"file_slots\" must be at least 0x%x",
1012 FW_CFG_FILE_SLOTS_MIN);
1013 return;
1014 }
1015
1016
1017
1018
1019 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1;
1020 if (fw_cfg_file_slots(s) > file_slots_max) {
1021 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16,
1022 file_slots_max);
1023 return;
1024 }
1025
1026 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1027 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1028 s->entry_order = g_new0(int, fw_cfg_max_entry(s));
1029}
1030
1031static Property fw_cfg_io_properties[] = {
1032 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
1033 true),
1034 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots,
1035 FW_CFG_FILE_SLOTS_DFLT),
1036 DEFINE_PROP_END_OF_LIST(),
1037};
1038
1039static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
1040{
1041 FWCfgIoState *s = FW_CFG_IO(dev);
1042 Error *local_err = NULL;
1043
1044 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1045 if (local_err) {
1046 error_propagate(errp, local_err);
1047 return;
1048 }
1049
1050
1051
1052
1053 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
1054 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
1055
1056 if (FW_CFG(s)->dma_enabled) {
1057 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1058 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1059 sizeof(dma_addr_t));
1060 }
1061
1062 fw_cfg_common_realize(dev, errp);
1063}
1064
1065static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
1066{
1067 DeviceClass *dc = DEVICE_CLASS(klass);
1068
1069 dc->realize = fw_cfg_io_realize;
1070 dc->props = fw_cfg_io_properties;
1071}
1072
1073static const TypeInfo fw_cfg_io_info = {
1074 .name = TYPE_FW_CFG_IO,
1075 .parent = TYPE_FW_CFG,
1076 .instance_size = sizeof(FWCfgIoState),
1077 .class_init = fw_cfg_io_class_init,
1078};
1079
1080
1081static Property fw_cfg_mem_properties[] = {
1082 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
1083 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
1084 true),
1085 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots,
1086 FW_CFG_FILE_SLOTS_DFLT),
1087 DEFINE_PROP_END_OF_LIST(),
1088};
1089
1090static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
1091{
1092 FWCfgMemState *s = FW_CFG_MEM(dev);
1093 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1094 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
1095 Error *local_err = NULL;
1096
1097 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1098 if (local_err) {
1099 error_propagate(errp, local_err);
1100 return;
1101 }
1102
1103 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
1104 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
1105 sysbus_init_mmio(sbd, &s->ctl_iomem);
1106
1107 if (s->data_width > data_ops->valid.max_access_size) {
1108
1109 s->wide_data_ops.read = data_ops->read;
1110 s->wide_data_ops.write = data_ops->write;
1111 s->wide_data_ops.endianness = data_ops->endianness;
1112 s->wide_data_ops.valid = data_ops->valid;
1113 s->wide_data_ops.impl = data_ops->impl;
1114
1115 s->wide_data_ops.valid.max_access_size = s->data_width;
1116 s->wide_data_ops.impl.max_access_size = s->data_width;
1117 data_ops = &s->wide_data_ops;
1118 }
1119 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
1120 "fwcfg.data", data_ops->valid.max_access_size);
1121 sysbus_init_mmio(sbd, &s->data_iomem);
1122
1123 if (FW_CFG(s)->dma_enabled) {
1124 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1125 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1126 sizeof(dma_addr_t));
1127 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
1128 }
1129
1130 fw_cfg_common_realize(dev, errp);
1131}
1132
1133static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
1134{
1135 DeviceClass *dc = DEVICE_CLASS(klass);
1136
1137 dc->realize = fw_cfg_mem_realize;
1138 dc->props = fw_cfg_mem_properties;
1139}
1140
1141static const TypeInfo fw_cfg_mem_info = {
1142 .name = TYPE_FW_CFG_MEM,
1143 .parent = TYPE_FW_CFG,
1144 .instance_size = sizeof(FWCfgMemState),
1145 .class_init = fw_cfg_mem_class_init,
1146};
1147
1148
1149static void fw_cfg_register_types(void)
1150{
1151 type_register_static(&fw_cfg_info);
1152 type_register_static(&fw_cfg_io_info);
1153 type_register_static(&fw_cfg_mem_info);
1154}
1155
1156type_init(fw_cfg_register_types)
1157