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26#include "qemu/osdep.h"
27#include "qapi/error.h"
28#include "hw/hw.h"
29#include "hw/pci/pci.h"
30#include "hw/pci/pci_bus.h"
31#include "hw/pci/pci_host.h"
32#include "hw/i386/pc.h"
33#include "hw/loader.h"
34#include "exec/address-spaces.h"
35#include "elf.h"
36
37#define TYPE_RAVEN_PCI_DEVICE "raven"
38#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
39
40#define RAVEN_PCI_DEVICE(obj) \
41 OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
42
43typedef struct RavenPCIState {
44 PCIDevice dev;
45
46 uint32_t elf_machine;
47 char *bios_name;
48 MemoryRegion bios;
49} RavenPCIState;
50
51#define RAVEN_PCI_HOST_BRIDGE(obj) \
52 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
53
54typedef struct PRePPCIState {
55 PCIHostState parent_obj;
56
57 qemu_irq irq[PCI_NUM_PINS];
58 PCIBus pci_bus;
59 AddressSpace pci_io_as;
60 MemoryRegion pci_io;
61 MemoryRegion pci_io_non_contiguous;
62 MemoryRegion pci_memory;
63 MemoryRegion pci_intack;
64 MemoryRegion bm;
65 MemoryRegion bm_ram_alias;
66 MemoryRegion bm_pci_memory_alias;
67 AddressSpace bm_as;
68 RavenPCIState pci_dev;
69
70 int contiguous_map;
71} PREPPCIState;
72
73#define BIOS_SIZE (1024 * 1024)
74
75static inline uint32_t raven_pci_io_config(hwaddr addr)
76{
77 int i;
78
79 for (i = 0; i < 11; i++) {
80 if ((addr & (1 << (11 + i))) != 0) {
81 break;
82 }
83 }
84 return (addr & 0x7ff) | (i << 11);
85}
86
87static void raven_pci_io_write(void *opaque, hwaddr addr,
88 uint64_t val, unsigned int size)
89{
90 PREPPCIState *s = opaque;
91 PCIHostState *phb = PCI_HOST_BRIDGE(s);
92 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
93}
94
95static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
96 unsigned int size)
97{
98 PREPPCIState *s = opaque;
99 PCIHostState *phb = PCI_HOST_BRIDGE(s);
100 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
101}
102
103static const MemoryRegionOps raven_pci_io_ops = {
104 .read = raven_pci_io_read,
105 .write = raven_pci_io_write,
106 .endianness = DEVICE_LITTLE_ENDIAN,
107};
108
109static uint64_t raven_intack_read(void *opaque, hwaddr addr,
110 unsigned int size)
111{
112 return pic_read_irq(isa_pic);
113}
114
115static const MemoryRegionOps raven_intack_ops = {
116 .read = raven_intack_read,
117 .valid = {
118 .max_access_size = 1,
119 },
120};
121
122static inline hwaddr raven_io_address(PREPPCIState *s,
123 hwaddr addr)
124{
125 if (s->contiguous_map == 0) {
126
127 addr &= 0xFFFF;
128 } else {
129
130 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
131 }
132
133
134
135 return addr;
136}
137
138static uint64_t raven_io_read(void *opaque, hwaddr addr,
139 unsigned int size)
140{
141 PREPPCIState *s = opaque;
142 uint8_t buf[4];
143
144 addr = raven_io_address(s, addr);
145 address_space_read(&s->pci_io_as, addr + 0x80000000,
146 MEMTXATTRS_UNSPECIFIED, buf, size);
147
148 if (size == 1) {
149 return buf[0];
150 } else if (size == 2) {
151 return lduw_le_p(buf);
152 } else if (size == 4) {
153 return ldl_le_p(buf);
154 } else {
155 g_assert_not_reached();
156 }
157}
158
159static void raven_io_write(void *opaque, hwaddr addr,
160 uint64_t val, unsigned int size)
161{
162 PREPPCIState *s = opaque;
163 uint8_t buf[4];
164
165 addr = raven_io_address(s, addr);
166
167 if (size == 1) {
168 buf[0] = val;
169 } else if (size == 2) {
170 stw_le_p(buf, val);
171 } else if (size == 4) {
172 stl_le_p(buf, val);
173 } else {
174 g_assert_not_reached();
175 }
176
177 address_space_write(&s->pci_io_as, addr + 0x80000000,
178 MEMTXATTRS_UNSPECIFIED, buf, size);
179}
180
181static const MemoryRegionOps raven_io_ops = {
182 .read = raven_io_read,
183 .write = raven_io_write,
184 .endianness = DEVICE_LITTLE_ENDIAN,
185 .impl.max_access_size = 4,
186 .valid.unaligned = true,
187};
188
189static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
190{
191 return (irq_num + (pci_dev->devfn >> 3)) & 1;
192}
193
194static void raven_set_irq(void *opaque, int irq_num, int level)
195{
196 qemu_irq *pic = opaque;
197
198 qemu_set_irq(pic[irq_num] , level);
199}
200
201static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
202 int devfn)
203{
204 PREPPCIState *s = opaque;
205
206 return &s->bm_as;
207}
208
209static void raven_change_gpio(void *opaque, int n, int level)
210{
211 PREPPCIState *s = opaque;
212
213 s->contiguous_map = level;
214}
215
216static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
217{
218 SysBusDevice *dev = SYS_BUS_DEVICE(d);
219 PCIHostState *h = PCI_HOST_BRIDGE(dev);
220 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
221 MemoryRegion *address_space_mem = get_system_memory();
222 int i;
223
224 for (i = 0; i < PCI_NUM_PINS; i++) {
225 sysbus_init_irq(dev, &s->irq[i]);
226 }
227
228 qdev_init_gpio_in(d, raven_change_gpio, 1);
229
230 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s->irq,
231 PCI_NUM_PINS);
232
233 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
234 "pci-conf-idx", 4);
235 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
236
237 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
238 "pci-conf-data", 4);
239 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
240
241 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
242 "pciio", 0x00400000);
243 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
244
245 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
246 "pci-intack", 1);
247 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
248
249
250 object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
251 object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
252}
253
254static void raven_pcihost_initfn(Object *obj)
255{
256 PCIHostState *h = PCI_HOST_BRIDGE(obj);
257 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
258 MemoryRegion *address_space_mem = get_system_memory();
259 DeviceState *pci_dev;
260
261 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
262 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
263 "pci-io-non-contiguous", 0x00800000);
264 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
265 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
266
267
268 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
269 memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
270 &s->pci_io_non_contiguous, 1);
271 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
272 pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
273 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
274
275
276 memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
277 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
278 &s->pci_memory, 0,
279 memory_region_size(&s->pci_memory));
280 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
281 get_system_memory(), 0, 0x80000000);
282 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
283 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
284 address_space_init(&s->bm_as, &s->bm, "raven-bm");
285 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
286
287 h->bus = &s->pci_bus;
288
289 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
290 pci_dev = DEVICE(&s->pci_dev);
291 qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
292 object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
293 NULL);
294 qdev_prop_set_bit(pci_dev, "multifunction", false);
295}
296
297static void raven_realize(PCIDevice *d, Error **errp)
298{
299 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
300 char *filename;
301 int bios_size = -1;
302
303 d->config[0x0C] = 0x08;
304 d->config[0x0D] = 0x10;
305 d->config[0x34] = 0x00;
306
307 memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
308 &error_fatal);
309 memory_region_set_readonly(&s->bios, true);
310 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
311 &s->bios);
312 if (s->bios_name) {
313 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
314 if (filename) {
315 if (s->elf_machine != EM_NONE) {
316 bios_size = load_elf(filename, NULL, NULL, NULL,
317 NULL, NULL, 1, s->elf_machine, 0, 0);
318 }
319 if (bios_size < 0) {
320 bios_size = get_image_size(filename);
321 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
322 hwaddr bios_addr;
323 bios_size = (bios_size + 0xfff) & ~0xfff;
324 bios_addr = (uint32_t)(-BIOS_SIZE);
325 bios_size = load_image_targphys(filename, bios_addr,
326 bios_size);
327 }
328 }
329 }
330 g_free(filename);
331 if (bios_size < 0 || bios_size > BIOS_SIZE) {
332 memory_region_del_subregion(get_system_memory(), &s->bios);
333 error_setg(errp, "Could not load bios image '%s'", s->bios_name);
334 return;
335 }
336 }
337
338 vmstate_register_ram_global(&s->bios);
339}
340
341static const VMStateDescription vmstate_raven = {
342 .name = "raven",
343 .version_id = 0,
344 .minimum_version_id = 0,
345 .fields = (VMStateField[]) {
346 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
347 VMSTATE_END_OF_LIST()
348 },
349};
350
351static void raven_class_init(ObjectClass *klass, void *data)
352{
353 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
354 DeviceClass *dc = DEVICE_CLASS(klass);
355
356 k->realize = raven_realize;
357 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
358 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
359 k->revision = 0x00;
360 k->class_id = PCI_CLASS_BRIDGE_HOST;
361 dc->desc = "PReP Host Bridge - Motorola Raven";
362 dc->vmsd = &vmstate_raven;
363
364
365
366
367 dc->user_creatable = false;
368}
369
370static const TypeInfo raven_info = {
371 .name = TYPE_RAVEN_PCI_DEVICE,
372 .parent = TYPE_PCI_DEVICE,
373 .instance_size = sizeof(RavenPCIState),
374 .class_init = raven_class_init,
375 .interfaces = (InterfaceInfo[]) {
376 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
377 { },
378 },
379};
380
381static Property raven_pcihost_properties[] = {
382 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
383 EM_NONE),
384 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
385 DEFINE_PROP_END_OF_LIST()
386};
387
388static void raven_pcihost_class_init(ObjectClass *klass, void *data)
389{
390 DeviceClass *dc = DEVICE_CLASS(klass);
391
392 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
393 dc->realize = raven_pcihost_realizefn;
394 dc->props = raven_pcihost_properties;
395 dc->fw_name = "pci";
396}
397
398static const TypeInfo raven_pcihost_info = {
399 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
400 .parent = TYPE_PCI_HOST_BRIDGE,
401 .instance_size = sizeof(PREPPCIState),
402 .instance_init = raven_pcihost_initfn,
403 .class_init = raven_pcihost_class_init,
404};
405
406static void raven_register_types(void)
407{
408 type_register_static(&raven_pcihost_info);
409 type_register_static(&raven_info);
410}
411
412type_init(raven_register_types)
413
