LXR qemu/hw/pci/shpc.c

   1#include "qemu/osdep.h"
   2#include "qapi/error.h"
   3#include "qemu-common.h"
   4#include "qemu/host-utils.h"
   5#include "qemu/range.h"
   6#include "qemu/error-report.h"
   7#include "hw/pci/shpc.h"
   8#include "hw/pci/pci.h"
   9#include "hw/pci/pci_bus.h"
  10#include "hw/pci/msi.h"
  11
  12/* TODO: model power only and disabled slot states. */
  13/* TODO: handle SERR and wakeups */
  14/* TODO: consider enabling 66MHz support */
  15
  16/* TODO: remove fully only on state DISABLED and LED off.
  17 * track state to properly record this. */
  18
  19/* SHPC Working Register Set */
  20#define SHPC_BASE_OFFSET  0x00 /* 4 bytes */
  21#define SHPC_SLOTS_33     0x04 /* 4 bytes. Also encodes PCI-X slots. */
  22#define SHPC_SLOTS_66     0x08 /* 4 bytes. */
  23#define SHPC_NSLOTS       0x0C /* 1 byte */
  24#define SHPC_FIRST_DEV    0x0D /* 1 byte */
  25#define SHPC_PHYS_SLOT    0x0E /* 2 byte */
  26#define SHPC_PHYS_NUM_MAX 0x7ff
  27#define SHPC_PHYS_NUM_UP  0x2000
  28#define SHPC_PHYS_MRL     0x4000
  29#define SHPC_PHYS_BUTTON  0x8000
  30#define SHPC_SEC_BUS      0x10 /* 2 bytes */
  31#define SHPC_SEC_BUS_33   0x0
  32#define SHPC_SEC_BUS_66   0x1 /* Unused */
  33#define SHPC_SEC_BUS_MASK 0x7
  34#define SHPC_MSI_CTL      0x12 /* 1 byte */
  35#define SHPC_PROG_IFC     0x13 /* 1 byte */
  36#define SHPC_PROG_IFC_1_0 0x1
  37#define SHPC_CMD_CODE     0x14 /* 1 byte */
  38#define SHPC_CMD_TRGT     0x15 /* 1 byte */
  39#define SHPC_CMD_TRGT_MIN 0x1
  40#define SHPC_CMD_TRGT_MAX 0x1f
  41#define SHPC_CMD_STATUS   0x16 /* 2 bytes */
  42#define SHPC_CMD_STATUS_BUSY          0x1
  43#define SHPC_CMD_STATUS_MRL_OPEN      0x2
  44#define SHPC_CMD_STATUS_INVALID_CMD   0x4
  45#define SHPC_CMD_STATUS_INVALID_MODE  0x8
  46#define SHPC_INT_LOCATOR  0x18 /* 4 bytes */
  47#define SHPC_INT_COMMAND  0x1
  48#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
  49#define SHPC_SERR_INT     0x20 /* 4 bytes */
  50#define SHPC_INT_DIS      0x1
  51#define SHPC_SERR_DIS     0x2
  52#define SHPC_CMD_INT_DIS  0x4
  53#define SHPC_ARB_SERR_DIS 0x8
  54#define SHPC_CMD_DETECTED 0x10000
  55#define SHPC_ARB_DETECTED 0x20000
  56 /* 4 bytes * slot # (start from 0) */
  57#define SHPC_SLOT_REG(s)         (0x24 + (s) * 4)
  58 /* 2 bytes */
  59#define SHPC_SLOT_STATUS(s)       (0x0 + SHPC_SLOT_REG(s))
  60
  61/* Same slot state masks are used for command and status registers */
  62#define SHPC_SLOT_STATE_MASK     0x03
  63#define SHPC_SLOT_STATE_SHIFT \
  64    ctz32(SHPC_SLOT_STATE_MASK)
  65
  66#define SHPC_STATE_NO       0x0
  67#define SHPC_STATE_PWRONLY  0x1
  68#define SHPC_STATE_ENABLED  0x2
  69#define SHPC_STATE_DISABLED 0x3
  70
  71#define SHPC_SLOT_PWR_LED_MASK   0xC
  72#define SHPC_SLOT_PWR_LED_SHIFT \
  73    ctz32(SHPC_SLOT_PWR_LED_MASK)
  74#define SHPC_SLOT_ATTN_LED_MASK  0x30
  75#define SHPC_SLOT_ATTN_LED_SHIFT \
  76    ctz32(SHPC_SLOT_ATTN_LED_MASK)
  77
  78#define SHPC_LED_NO     0x0
  79#define SHPC_LED_ON     0x1
  80#define SHPC_LED_BLINK  0x2
  81#define SHPC_LED_OFF    0x3
  82
  83#define SHPC_SLOT_STATUS_PWR_FAULT      0x40
  84#define SHPC_SLOT_STATUS_BUTTON         0x80
  85#define SHPC_SLOT_STATUS_MRL_OPEN       0x100
  86#define SHPC_SLOT_STATUS_66             0x200
  87#define SHPC_SLOT_STATUS_PRSNT_MASK     0xC00
  88#define SHPC_SLOT_STATUS_PRSNT_EMPTY    0x3
  89#define SHPC_SLOT_STATUS_PRSNT_25W      0x1
  90#define SHPC_SLOT_STATUS_PRSNT_15W      0x2
  91#define SHPC_SLOT_STATUS_PRSNT_7_5W     0x0
  92
  93#define SHPC_SLOT_STATUS_PRSNT_PCIX     0x3000
  94
  95
  96 /* 1 byte */
  97#define SHPC_SLOT_EVENT_LATCH(s)        (0x2 + SHPC_SLOT_REG(s))
  98 /* 1 byte */
  99#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
 100#define SHPC_SLOT_EVENT_PRESENCE        0x01
 101#define SHPC_SLOT_EVENT_ISOLATED_FAULT  0x02
 102#define SHPC_SLOT_EVENT_BUTTON          0x04
 103#define SHPC_SLOT_EVENT_MRL             0x08
 104#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
 105/* Bits below are used for Serr/Int disable only */
 106#define SHPC_SLOT_EVENT_MRL_SERR_DIS    0x20
 107#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
 108
 109#define SHPC_MIN_SLOTS        1
 110#define SHPC_MAX_SLOTS        31
 111#define SHPC_SIZEOF(d)    SHPC_SLOT_REG((d)->shpc->nslots)
 112
 113/* SHPC Slot identifiers */
 114
 115/* Hotplug supported at 31 slots out of the total 32.  We reserve slot 0,
 116   and give the rest of them physical *and* pci numbers starting from 1, so
 117   they match logical numbers.  Note: this means that multiple slots must have
 118   different chassis number values, to make chassis+physical slot unique.
 119   TODO: make this configurable? */
 120#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
 121#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
 122#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
 123#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
 124#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
 125
 126static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
 127{
 128    uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
 129    return (pci_get_word(status) & msk) >> ctz32(msk);
 130}
 131
 132static void shpc_set_status(SHPCDevice *shpc,
 133                            int slot, uint8_t value, uint16_t msk)
 134{
 135    uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
 136    pci_word_test_and_clear_mask(status, msk);
 137    pci_word_test_and_set_mask(status, value << ctz32(msk));
 138}
 139
 140static void shpc_interrupt_update(PCIDevice *d)
 141{
 142    SHPCDevice *shpc = d->shpc;
 143    int slot;
 144    int level = 0;
 145    uint32_t serr_int;
 146    uint32_t int_locator = 0;
 147
 148    /* Update interrupt locator register */
 149    for (slot = 0; slot < shpc->nslots; ++slot) {
 150        uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
 151        uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
 152        uint32_t mask = 1U << SHPC_IDX_TO_LOGICAL(slot);
 153        if (event & ~disable) {
 154            int_locator |= mask;
 155        }
 156    }
 157    serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
 158    if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
 159        int_locator |= SHPC_INT_COMMAND;
 160    }
 161    pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
 162    level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
 163    if (msi_enabled(d) && shpc->msi_requested != level)
 164        msi_notify(d, 0);
 165    else
 166        pci_set_irq(d, level);
 167    shpc->msi_requested = level;
 168}
 169
 170static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
 171{
 172    switch (speed) {
 173    case SHPC_SEC_BUS_33:
 174        shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
 175        shpc->config[SHPC_SEC_BUS] |= speed;
 176        break;
 177    default:
 178        pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
 179                                   SHPC_CMD_STATUS_INVALID_MODE);
 180    }
 181}
 182
 183void shpc_reset(PCIDevice *d)
 184{
 185    SHPCDevice *shpc = d->shpc;
 186    int nslots = shpc->nslots;
 187    int i;
 188    memset(shpc->config, 0, SHPC_SIZEOF(d));
 189    pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
 190    pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
 191    pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
 192    pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
 193    pci_set_word(shpc->config + SHPC_PHYS_SLOT,
 194                 SHPC_IDX_TO_PHYSICAL(0) |
 195                 SHPC_PHYS_NUM_UP |
 196                 SHPC_PHYS_MRL |
 197                 SHPC_PHYS_BUTTON);
 198    pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
 199                 SHPC_SERR_DIS |
 200                 SHPC_CMD_INT_DIS |
 201                 SHPC_ARB_SERR_DIS);
 202    pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
 203    pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
 204    for (i = 0; i < shpc->nslots; ++i) {
 205        pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
 206                     SHPC_SLOT_EVENT_PRESENCE |
 207                     SHPC_SLOT_EVENT_ISOLATED_FAULT |
 208                     SHPC_SLOT_EVENT_BUTTON |
 209                     SHPC_SLOT_EVENT_MRL |
 210                     SHPC_SLOT_EVENT_CONNECTED_FAULT |
 211                     SHPC_SLOT_EVENT_MRL_SERR_DIS |
 212                     SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
 213        if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
 214            shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
 215            shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
 216            shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
 217                            SHPC_SLOT_STATUS_PRSNT_MASK);
 218            shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
 219        } else {
 220            shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
 221            shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
 222            shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
 223                            SHPC_SLOT_STATUS_PRSNT_MASK);
 224            shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
 225        }
 226        shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
 227    }
 228    shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
 229    shpc->msi_requested = 0;
 230    shpc_interrupt_update(d);
 231}
 232
 233static void shpc_invalid_command(SHPCDevice *shpc)
 234{
 235    pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
 236                               SHPC_CMD_STATUS_INVALID_CMD);
 237}
 238
 239static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
 240{
 241    int devfn;
 242    int pci_slot = SHPC_IDX_TO_PCI(slot);
 243    for (devfn = PCI_DEVFN(pci_slot, 0);
 244         devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
 245         ++devfn) {
 246        PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
 247        if (affected_dev) {
 248            object_unparent(OBJECT(affected_dev));
 249        }
 250    }
 251}
 252
 253static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
 254                              uint8_t state, uint8_t power, uint8_t attn)
 255{
 256    uint8_t current_state;
 257    int slot = SHPC_LOGICAL_TO_IDX(target);
 258    if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
 259        shpc_invalid_command(shpc);
 260        return;
 261    }
 262    current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
 263    if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
 264        shpc_invalid_command(shpc);
 265        return;
 266    }
 267
 268    switch (power) {
 269    case SHPC_LED_NO:
 270        break;
 271    default:
 272        /* TODO: send event to monitor */
 273        shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
 274    }
 275    switch (attn) {
 276    case SHPC_LED_NO:
 277        break;
 278    default:
 279        /* TODO: send event to monitor */
 280        shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
 281    }
 282
 283    if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
 284        (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
 285        shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
 286    } else if ((current_state == SHPC_STATE_ENABLED ||
 287                current_state == SHPC_STATE_PWRONLY) &&
 288               state == SHPC_STATE_DISABLED) {
 289        shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
 290        power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
 291        /* TODO: track what monitor requested. */
 292        /* Look at LED to figure out whether it's ok to remove the device. */
 293        if (power == SHPC_LED_OFF) {
 294            shpc_free_devices_in_slot(shpc, slot);
 295            shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
 296            shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
 297                            SHPC_SLOT_STATUS_PRSNT_MASK);
 298            shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 299                SHPC_SLOT_EVENT_BUTTON |
 300                SHPC_SLOT_EVENT_MRL |
 301                SHPC_SLOT_EVENT_PRESENCE;
 302        }
 303    }
 304}
 305
 306static void shpc_command(SHPCDevice *shpc)
 307{
 308    uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
 309    uint8_t speed;
 310    uint8_t target;
 311    uint8_t attn;
 312    uint8_t power;
 313    uint8_t state;
 314    int i;
 315
 316    /* Clear status from the previous command. */
 317    pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
 318                                 SHPC_CMD_STATUS_BUSY |
 319                                 SHPC_CMD_STATUS_MRL_OPEN |
 320                                 SHPC_CMD_STATUS_INVALID_CMD |
 321                                 SHPC_CMD_STATUS_INVALID_MODE);
 322    switch (code) {
 323    case 0x00 ... 0x3f:
 324        target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
 325        state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
 326        power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
 327        attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
 328        shpc_slot_command(shpc, target, state, power, attn);
 329        break;
 330    case 0x40 ... 0x47:
 331        speed = code & SHPC_SEC_BUS_MASK;
 332        shpc_set_sec_bus_speed(shpc, speed);
 333        break;
 334    case 0x48:
 335        /* Power only all slots */
 336        /* first verify no slots are enabled */
 337        for (i = 0; i < shpc->nslots; ++i) {
 338            state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
 339            if (state == SHPC_STATE_ENABLED) {
 340                shpc_invalid_command(shpc);
 341                goto done;
 342            }
 343        }
 344        for (i = 0; i < shpc->nslots; ++i) {
 345            if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
 346                shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
 347                                  SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
 348            } else {
 349                shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
 350                                  SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
 351            }
 352        }
 353        break;
 354    case 0x49:
 355        /* Enable all slots */
 356        /* TODO: Spec says this shall fail if some are already enabled.
 357         * This doesn't make sense - why not? a spec bug? */
 358        for (i = 0; i < shpc->nslots; ++i) {
 359            state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
 360            if (state == SHPC_STATE_ENABLED) {
 361                shpc_invalid_command(shpc);
 362                goto done;
 363            }
 364        }
 365        for (i = 0; i < shpc->nslots; ++i) {
 366            if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
 367                shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
 368                                  SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
 369            } else {
 370                shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
 371                                  SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
 372            }
 373        }
 374        break;
 375    default:
 376        shpc_invalid_command(shpc);
 377        break;
 378    }
 379done:
 380    pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
 381}
 382
 383static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
 384{
 385    SHPCDevice *shpc = d->shpc;
 386    int i;
 387    if (addr >= SHPC_SIZEOF(d)) {
 388        return;
 389    }
 390    l = MIN(l, SHPC_SIZEOF(d) - addr);
 391
 392    /* TODO: code duplicated from pci.c */
 393    for (i = 0; i < l; val >>= 8, ++i) {
 394        unsigned a = addr + i;
 395        uint8_t wmask = shpc->wmask[a];
 396        uint8_t w1cmask = shpc->w1cmask[a];
 397        assert(!(wmask & w1cmask));
 398        shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
 399        shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
 400    }
 401    if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
 402        shpc_command(shpc);
 403    }
 404    shpc_interrupt_update(d);
 405}
 406
 407static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
 408{
 409    uint64_t val = 0x0;
 410    if (addr >= SHPC_SIZEOF(d)) {
 411        return val;
 412    }
 413    l = MIN(l, SHPC_SIZEOF(d) - addr);
 414    memcpy(&val, d->shpc->config + addr, l);
 415    return val;
 416}
 417
 418/* SHPC Bridge Capability */
 419#define SHPC_CAP_LENGTH 0x08
 420#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
 421#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
 422#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
 423#define SHPC_CAP_CSP_MASK 0x4
 424#define SHPC_CAP_CIP_MASK 0x8
 425
 426static uint8_t shpc_cap_dword(PCIDevice *d)
 427{
 428    return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
 429}
 430
 431/* Update dword data capability register */
 432static void shpc_cap_update_dword(PCIDevice *d)
 433{
 434    unsigned data;
 435    data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
 436    pci_set_long(d->config  + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
 437}
 438
 439/* Add SHPC capability to the config space for the device. */
 440static int shpc_cap_add_config(PCIDevice *d, Error **errp)
 441{
 442    uint8_t *config;
 443    int config_offset;
 444    config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
 445                                       0, SHPC_CAP_LENGTH,
 446                                       errp);
 447    if (config_offset < 0) {
 448        return config_offset;
 449    }
 450    config = d->config + config_offset;
 451
 452    pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
 453    pci_set_byte(config + SHPC_CAP_CxP, 0);
 454    pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
 455    d->shpc->cap = config_offset;
 456    /* Make dword select and data writeable. */
 457    pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
 458    pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
 459    return 0;
 460}
 461
 462static uint64_t shpc_mmio_read(void *opaque, hwaddr addr,
 463                               unsigned size)
 464{
 465    return shpc_read(opaque, addr, size);
 466}
 467
 468static void shpc_mmio_write(void *opaque, hwaddr addr,
 469                            uint64_t val, unsigned size)
 470{
 471    shpc_write(opaque, addr, val, size);
 472}
 473
 474static const MemoryRegionOps shpc_mmio_ops = {
 475    .read = shpc_mmio_read,
 476    .write = shpc_mmio_write,
 477    .endianness = DEVICE_LITTLE_ENDIAN,
 478    .valid = {
 479        /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
 480         * It's easier to suppport all sizes than worry about it. */
 481        .min_access_size = 1,
 482        .max_access_size = 4,
 483    },
 484};
 485static void shpc_device_hotplug_common(PCIDevice *affected_dev, int *slot,
 486                                       SHPCDevice *shpc, Error **errp)
 487{
 488    int pci_slot = PCI_SLOT(affected_dev->devfn);
 489    *slot = SHPC_PCI_TO_IDX(pci_slot);
 490
 491    if (pci_slot < SHPC_IDX_TO_PCI(0) || *slot >= shpc->nslots) {
 492        error_setg(errp, "Unsupported PCI slot %d for standard hotplug "
 493                   "controller. Valid slots are between %d and %d.",
 494                   pci_slot, SHPC_IDX_TO_PCI(0),
 495                   SHPC_IDX_TO_PCI(shpc->nslots) - 1);
 496        return;
 497    }
 498}
 499
 500void shpc_device_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
 501                            Error **errp)
 502{
 503    Error *local_err = NULL;
 504    PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
 505    SHPCDevice *shpc = pci_hotplug_dev->shpc;
 506    int slot;
 507
 508    shpc_device_hotplug_common(PCI_DEVICE(dev), &slot, shpc, &local_err);
 509    if (local_err) {
 510        error_propagate(errp, local_err);
 511        return;
 512    }
 513
 514    /* Don't send event when device is enabled during qemu machine creation:
 515     * it is present on boot, no hotplug event is necessary. We do send an
 516     * event when the device is disabled later. */
 517    if (!dev->hotplugged) {
 518        shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
 519        shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
 520                        SHPC_SLOT_STATUS_PRSNT_MASK);
 521        return;
 522    }
 523
 524    /* This could be a cancellation of the previous removal.
 525     * We check MRL state to figure out. */
 526    if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
 527        shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
 528        shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
 529                        SHPC_SLOT_STATUS_PRSNT_MASK);
 530        shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 531            SHPC_SLOT_EVENT_BUTTON |
 532            SHPC_SLOT_EVENT_MRL |
 533            SHPC_SLOT_EVENT_PRESENCE;
 534    } else {
 535        /* Press attention button to cancel removal */
 536        shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 537            SHPC_SLOT_EVENT_BUTTON;
 538    }
 539    shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
 540    shpc_interrupt_update(pci_hotplug_dev);
 541}
 542
 543void shpc_device_hot_unplug_request_cb(HotplugHandler *hotplug_dev,
 544                                       DeviceState *dev, Error **errp)
 545{
 546    Error *local_err = NULL;
 547    PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
 548    SHPCDevice *shpc = pci_hotplug_dev->shpc;
 549    uint8_t state;
 550    uint8_t led;
 551    int slot;
 552
 553    shpc_device_hotplug_common(PCI_DEVICE(dev), &slot, shpc, &local_err);
 554    if (local_err) {
 555        error_propagate(errp, local_err);
 556        return;
 557    }
 558
 559    shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
 560    state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
 561    led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
 562    if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
 563        shpc_free_devices_in_slot(shpc, slot);
 564        shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
 565        shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
 566                        SHPC_SLOT_STATUS_PRSNT_MASK);
 567        shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
 568            SHPC_SLOT_EVENT_MRL |
 569            SHPC_SLOT_EVENT_PRESENCE;
 570    }
 571    shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
 572    shpc_interrupt_update(pci_hotplug_dev);
 573}
 574
 575/* Initialize the SHPC structure in bridge's BAR. */
 576int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar,
 577              unsigned offset, Error **errp)
 578{
 579    int i, ret;
 580    int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
 581    SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
 582    shpc->sec_bus = sec_bus;
 583    ret = shpc_cap_add_config(d, errp);
 584    if (ret) {
 585        g_free(d->shpc);
 586        return ret;
 587    }
 588    if (nslots < SHPC_MIN_SLOTS) {
 589        return 0;
 590    }
 591    if (nslots > SHPC_MAX_SLOTS ||
 592        SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
 593        /* TODO: report an error mesage that makes sense. */
 594        return -EINVAL;
 595    }
 596    shpc->nslots = nslots;
 597    shpc->config = g_malloc0(SHPC_SIZEOF(d));
 598    shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
 599    shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
 600    shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
 601
 602    shpc_reset(d);
 603
 604    pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
 605
 606    pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
 607    pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
 608    pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
 609    pci_set_long(shpc->wmask + SHPC_SERR_INT,
 610                 SHPC_INT_DIS |
 611                 SHPC_SERR_DIS |
 612                 SHPC_CMD_INT_DIS |
 613                 SHPC_ARB_SERR_DIS);
 614    pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
 615                 SHPC_CMD_DETECTED |
 616                 SHPC_ARB_DETECTED);
 617    for (i = 0; i < nslots; ++i) {
 618        pci_set_byte(shpc->wmask +
 619                     SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
 620                     SHPC_SLOT_EVENT_PRESENCE |
 621                     SHPC_SLOT_EVENT_ISOLATED_FAULT |
 622                     SHPC_SLOT_EVENT_BUTTON |
 623                     SHPC_SLOT_EVENT_MRL |
 624                     SHPC_SLOT_EVENT_CONNECTED_FAULT |
 625                     SHPC_SLOT_EVENT_MRL_SERR_DIS |
 626                     SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
 627        pci_set_byte(shpc->w1cmask +
 628                     SHPC_SLOT_EVENT_LATCH(i),
 629                     SHPC_SLOT_EVENT_PRESENCE |
 630                     SHPC_SLOT_EVENT_ISOLATED_FAULT |
 631                     SHPC_SLOT_EVENT_BUTTON |
 632                     SHPC_SLOT_EVENT_MRL |
 633                     SHPC_SLOT_EVENT_CONNECTED_FAULT);
 634    }
 635
 636    /* TODO: init cmask */
 637    memory_region_init_io(&shpc->mmio, OBJECT(d), &shpc_mmio_ops,
 638                          d, "shpc-mmio", SHPC_SIZEOF(d));
 639    shpc_cap_update_dword(d);
 640    memory_region_add_subregion(bar, offset, &shpc->mmio);
 641
 642    qbus_set_hotplug_handler(BUS(sec_bus), DEVICE(d), NULL);
 643
 644    d->cap_present |= QEMU_PCI_CAP_SHPC;
 645    return 0;
 646}
 647
 648int shpc_bar_size(PCIDevice *d)
 649{
 650    return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
 651}
 652
 653void shpc_cleanup(PCIDevice *d, MemoryRegion *bar)
 654{
 655    SHPCDevice *shpc = d->shpc;
 656    d->cap_present &= ~QEMU_PCI_CAP_SHPC;
 657    memory_region_del_subregion(bar, &shpc->mmio);
 658    /* TODO: cleanup config space changes? */
 659}
 660
 661void shpc_free(PCIDevice *d)
 662{
 663    SHPCDevice *shpc = d->shpc;
 664    if (!shpc) {
 665        return;
 666    }
 667    object_unparent(OBJECT(&shpc->mmio));
 668    g_free(shpc->config);
 669    g_free(shpc->cmask);
 670    g_free(shpc->wmask);
 671    g_free(shpc->w1cmask);
 672    g_free(shpc);
 673    d->shpc = NULL;
 674}
 675
 676void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 677{
 678    if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
 679        return;
 680    }
 681    if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
 682        unsigned dword_data;
 683        dword_data = pci_get_long(d->shpc->config + d->shpc->cap
 684                                  + SHPC_CAP_DWORD_DATA);
 685        shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
 686    }
 687    /* Update cap dword data in case guest is going to read it. */
 688    shpc_cap_update_dword(d);
 689}
 690
 691static int shpc_save(QEMUFile *f, void *pv, size_t size, VMStateField *field,
 692                     QJSON *vmdesc)
 693{
 694    PCIDevice *d = container_of(pv, PCIDevice, shpc);
 695    qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
 696
 697    return 0;
 698}
 699
 700static int shpc_load(QEMUFile *f, void *pv, size_t size, VMStateField *field)
 701{
 702    PCIDevice *d = container_of(pv, PCIDevice, shpc);
 703    int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
 704    if (ret != SHPC_SIZEOF(d)) {
 705        return -EINVAL;
 706    }
 707    /* Make sure we don't lose notifications. An extra interrupt is harmless. */
 708    d->shpc->msi_requested = 0;
 709    shpc_interrupt_update(d);
 710    return 0;
 711}
 712
 713VMStateInfo shpc_vmstate_info = {
 714    .name = "shpc",
 715    .get  = shpc_load,
 716    .put  = shpc_save,
 717};
 718