LXR qemu/hw/ppc/prep

   1/*
   2 * QEMU PReP System I/O emulation
   3 *
   4 * Copyright (c) 2017 Hervé Poussineau
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/isa/isa.h"
  27#include "exec/address-spaces.h"
  28#include "qemu/error-report.h" /* for error_report() */
  29#include "sysemu/sysemu.h" /* for vm_stop() */
  30#include "cpu.h"
  31#include "trace.h"
  32
  33#define TYPE_PREP_SYSTEMIO "prep-systemio"
  34#define PREP_SYSTEMIO(obj) \
  35    OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
  36
  37/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
  38#define PREP_BIT(n) (1 << (7 - (n)))
  39
  40typedef struct PrepSystemIoState {
  41    ISADevice parent_obj;
  42    MemoryRegion ppc_parity_mem;
  43
  44    qemu_irq non_contiguous_io_map_irq;
  45    uint8_t sreset; /* 0x0092 */
  46    uint8_t equipment; /* 0x080c */
  47    uint8_t system_control; /* 0x081c */
  48    uint8_t iomap_type; /* 0x0850 */
  49    uint8_t ibm_planar_id; /* 0x0852 */
  50    qemu_irq softreset_irq;
  51    PortioList portio;
  52} PrepSystemIoState;
  53
  54/* PORT 0092 -- Special Port 92 (Read/Write) */
  55
  56enum {
  57    PORT0092_SOFTRESET  = PREP_BIT(7),
  58    PORT0092_LE_MODE    = PREP_BIT(6),
  59};
  60
  61static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val)
  62{
  63    PrepSystemIoState *s = opaque;
  64
  65    trace_prep_systemio_write(addr, val);
  66
  67    s->sreset = val & PORT0092_SOFTRESET;
  68    qemu_set_irq(s->softreset_irq, s->sreset);
  69
  70    if ((val & PORT0092_LE_MODE) != 0) {
  71        /* XXX Not supported yet */
  72        error_report("little-endian mode not supported");
  73        vm_stop(RUN_STATE_PAUSED);
  74    } else {
  75        /* Nothing to do */
  76    }
  77}
  78
  79static uint32_t prep_port0092_read(void *opaque, uint32_t addr)
  80{
  81    PrepSystemIoState *s = opaque;
  82    trace_prep_systemio_read(addr, s->sreset);
  83    return s->sreset;
  84}
  85
  86/* PORT 0808 -- Hardfile Light Register (Write Only) */
  87
  88enum {
  89    PORT0808_HARDFILE_LIGHT_ON  = PREP_BIT(7),
  90};
  91
  92static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val)
  93{
  94    trace_prep_systemio_write(addr, val);
  95}
  96
  97/* PORT 0810 -- Password Protect 1 Register (Write Only) */
  98
  99/* reset by port 0x4D in the SIO */
 100static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val)
 101{
 102    trace_prep_systemio_write(addr, val);
 103}
 104
 105/* PORT 0812 -- Password Protect 2 Register (Write Only) */
 106
 107/* reset by port 0x4D in the SIO */
 108static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val)
 109{
 110    trace_prep_systemio_write(addr, val);
 111}
 112
 113/* PORT 0814 -- L2 Invalidate Register (Write Only) */
 114
 115static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val)
 116{
 117    trace_prep_systemio_write(addr, val);
 118}
 119
 120/* PORT 0818 -- Reserved for Keylock (Read Only) */
 121
 122enum {
 123    PORT0818_KEYLOCK_SIGNAL_HIGH    = PREP_BIT(7),
 124};
 125
 126static uint32_t prep_port0818_read(void *opaque, uint32_t addr)
 127{
 128    uint32_t val = 0;
 129    trace_prep_systemio_read(addr, val);
 130    return val;
 131}
 132
 133/* PORT 080C -- Equipment */
 134
 135enum {
 136    PORT080C_SCSIFUSE               = PREP_BIT(1),
 137    PORT080C_L2_COPYBACK            = PREP_BIT(4),
 138    PORT080C_L2_256                 = PREP_BIT(5),
 139    PORT080C_UPGRADE_CPU            = PREP_BIT(6),
 140    PORT080C_L2                     = PREP_BIT(7),
 141};
 142
 143static uint32_t prep_port080c_read(void *opaque, uint32_t addr)
 144{
 145    PrepSystemIoState *s = opaque;
 146    trace_prep_systemio_read(addr, s->equipment);
 147    return s->equipment;
 148}
 149
 150/* PORT 081C -- System Control Register (Read/Write) */
 151
 152enum {
 153    PORT081C_FLOPPY_MOTOR_INHIBIT   = PREP_BIT(3),
 154    PORT081C_MASK_TEA               = PREP_BIT(2),
 155    PORT081C_L2_UPDATE_INHIBIT      = PREP_BIT(1),
 156    PORT081C_L2_CACHEMISS_INHIBIT   = PREP_BIT(0),
 157};
 158
 159static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val)
 160{
 161    static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT |
 162                                PORT081C_MASK_TEA |
 163                                PORT081C_L2_UPDATE_INHIBIT |
 164                                PORT081C_L2_CACHEMISS_INHIBIT;
 165    PrepSystemIoState *s = opaque;
 166    trace_prep_systemio_write(addr, val);
 167    s->system_control = val & mask;
 168}
 169
 170static uint32_t prep_port081c_read(void *opaque, uint32_t addr)
 171{
 172    PrepSystemIoState *s = opaque;
 173    trace_prep_systemio_read(addr, s->system_control);
 174    return s->system_control;
 175}
 176
 177/* System Board Identification */
 178
 179static uint32_t prep_port0852_read(void *opaque, uint32_t addr)
 180{
 181    PrepSystemIoState *s = opaque;
 182    trace_prep_systemio_read(addr, s->ibm_planar_id);
 183    return s->ibm_planar_id;
 184}
 185
 186/* PORT 0850 -- I/O Map Type Register (Read/Write) */
 187
 188enum {
 189    PORT0850_IOMAP_NONCONTIGUOUS    = PREP_BIT(7),
 190};
 191
 192static uint32_t prep_port0850_read(void *opaque, uint32_t addr)
 193{
 194    PrepSystemIoState *s = opaque;
 195    trace_prep_systemio_read(addr, s->iomap_type);
 196    return s->iomap_type;
 197}
 198
 199static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val)
 200{
 201    PrepSystemIoState *s = opaque;
 202
 203    trace_prep_systemio_write(addr, val);
 204    qemu_set_irq(s->non_contiguous_io_map_irq,
 205                 val & PORT0850_IOMAP_NONCONTIGUOUS);
 206    s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS;
 207}
 208
 209static const MemoryRegionPortio ppc_io800_port_list[] = {
 210    { 0x092, 1, 1, .read = prep_port0092_read,
 211                   .write = prep_port0092_write, },
 212    { 0x808, 1, 1, .write = prep_port0808_write, },
 213    { 0x80c, 1, 1, .read = prep_port080c_read, },
 214    { 0x810, 1, 1, .write = prep_port0810_write, },
 215    { 0x812, 1, 1, .write = prep_port0812_write, },
 216    { 0x814, 1, 1, .write = prep_port0814_write, },
 217    { 0x818, 1, 1, .read = prep_port0818_read },
 218    { 0x81c, 1, 1, .read = prep_port081c_read,
 219                   .write = prep_port081c_write, },
 220    { 0x850, 1, 1, .read = prep_port0850_read,
 221                   .write = prep_port0850_write, },
 222    { 0x852, 1, 1, .read = prep_port0852_read, },
 223    PORTIO_END_OF_LIST()
 224};
 225
 226static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr,
 227                                       unsigned int size)
 228{
 229    uint32_t val = 0;
 230    trace_prep_systemio_read((unsigned int)addr, val);
 231    return val;
 232}
 233
 234static const MemoryRegionOps ppc_parity_error_ops = {
 235    .read = ppc_parity_error_readl,
 236    .valid = {
 237        .min_access_size = 4,
 238        .max_access_size = 4,
 239    },
 240};
 241
 242static void prep_systemio_realize(DeviceState *dev, Error **errp)
 243{
 244    ISADevice *isa = ISA_DEVICE(dev);
 245    PrepSystemIoState *s = PREP_SYSTEMIO(dev);
 246    PowerPCCPU *cpu;
 247
 248    qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1);
 249    s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS;
 250    qemu_set_irq(s->non_contiguous_io_map_irq,
 251                 s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
 252    cpu = POWERPC_CPU(first_cpu);
 253    s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
 254
 255    isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
 256                             "systemio800");
 257
 258    memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev),
 259                          &ppc_parity_error_ops, s, "ppc-parity", 0x4);
 260    memory_region_add_subregion(get_system_memory(), 0xbfffeff0,
 261                                &s->ppc_parity_mem);
 262}
 263
 264static const VMStateDescription vmstate_prep_systemio = {
 265    .name = "prep_systemio",
 266    .version_id = 1,
 267    .minimum_version_id = 1,
 268    .fields = (VMStateField[]) {
 269        VMSTATE_UINT8(sreset, PrepSystemIoState),
 270        VMSTATE_UINT8(system_control, PrepSystemIoState),
 271        VMSTATE_UINT8(iomap_type, PrepSystemIoState),
 272        VMSTATE_END_OF_LIST()
 273    },
 274};
 275
 276static Property prep_systemio_properties[] = {
 277    DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0),
 278    DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0),
 279    DEFINE_PROP_END_OF_LIST()
 280};
 281
 282static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
 283{
 284    DeviceClass *dc = DEVICE_CLASS(klass);
 285
 286    dc->realize = prep_systemio_realize;
 287    dc->vmsd = &vmstate_prep_systemio;
 288    dc->props = prep_systemio_properties;
 289}
 290
 291static TypeInfo prep_systemio800_info = {
 292    .name          = TYPE_PREP_SYSTEMIO,
 293    .parent        = TYPE_ISA_DEVICE,
 294    .instance_size = sizeof(PrepSystemIoState),
 295    .class_init    = prep_systemio_class_initfn,
 296};
 297
 298static void prep_systemio_register_types(void)
 299{
 300    type_register_static(&prep_systemio800_info);
 301}
 302
 303type_init(prep_systemio_register_types)
 304