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26
27#include "qemu/osdep.h"
28#include "qapi/error.h"
29#include "qapi/visitor.h"
30#include "sysemu/sysemu.h"
31#include "sysemu/numa.h"
32#include "hw/hw.h"
33#include "qemu/log.h"
34#include "hw/fw-path-provider.h"
35#include "elf.h"
36#include "net/net.h"
37#include "sysemu/device_tree.h"
38#include "sysemu/block-backend.h"
39#include "sysemu/cpus.h"
40#include "sysemu/hw_accel.h"
41#include "kvm_ppc.h"
42#include "migration/misc.h"
43#include "migration/global_state.h"
44#include "migration/register.h"
45#include "mmu-hash64.h"
46#include "mmu-book3s-v3.h"
47#include "cpu-models.h"
48#include "qom/cpu.h"
49
50#include "hw/boards.h"
51#include "hw/ppc/ppc.h"
52#include "hw/loader.h"
53
54#include "hw/ppc/fdt.h"
55#include "hw/ppc/spapr.h"
56#include "hw/ppc/spapr_vio.h"
57#include "hw/pci-host/spapr.h"
58#include "hw/ppc/xics.h"
59#include "hw/pci/msi.h"
60
61#include "hw/pci/pci.h"
62#include "hw/scsi/scsi.h"
63#include "hw/virtio/virtio-scsi.h"
64#include "hw/virtio/vhost-scsi-common.h"
65
66#include "exec/address-spaces.h"
67#include "hw/usb.h"
68#include "qemu/config-file.h"
69#include "qemu/error-report.h"
70#include "trace.h"
71#include "hw/nmi.h"
72#include "hw/intc/intc.h"
73
74#include "hw/compat.h"
75#include "qemu/cutils.h"
76#include "hw/ppc/spapr_cpu_core.h"
77
78#include <libfdt.h>
79
80
81
82
83
84
85
86
87
88
89
90#define FDT_MAX_SIZE 0x100000
91#define RTAS_MAX_SIZE 0x10000
92#define RTAS_MAX_ADDR 0x80000000
93#define FW_MAX_SIZE 0x400000
94#define FW_FILE_NAME "slof.bin"
95#define FW_OVERHEAD 0x2800000
96#define KERNEL_LOAD_ADDR FW_MAX_SIZE
97
98#define MIN_RMA_SLOF 128UL
99
100#define PHANDLE_XICP 0x00001111
101
102
103
104
105
106static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index)
107{
108 assert(spapr->vsmt);
109 return
110 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
111}
112static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr,
113 PowerPCCPU *cpu)
114{
115 assert(spapr->vsmt);
116 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
117}
118
119static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
120 const char *type_ics,
121 int nr_irqs, Error **errp)
122{
123 Error *local_err = NULL;
124 Object *obj;
125
126 obj = object_new(type_ics);
127 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
128 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
129 &error_abort);
130 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
131 if (local_err) {
132 goto error;
133 }
134 object_property_set_bool(obj, true, "realized", &local_err);
135 if (local_err) {
136 goto error;
137 }
138
139 return ICS_SIMPLE(obj);
140
141error:
142 error_propagate(errp, local_err);
143 return NULL;
144}
145
146static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
147{
148
149
150
151
152 return false;
153}
154
155static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
156 .name = "icp/server",
157 .version_id = 1,
158 .minimum_version_id = 1,
159 .needed = pre_2_10_vmstate_dummy_icp_needed,
160 .fields = (VMStateField[]) {
161 VMSTATE_UNUSED(4),
162 VMSTATE_UNUSED(1),
163 VMSTATE_UNUSED(1),
164 VMSTATE_END_OF_LIST()
165 },
166};
167
168static void pre_2_10_vmstate_register_dummy_icp(int i)
169{
170 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
171 (void *)(uintptr_t) i);
172}
173
174static void pre_2_10_vmstate_unregister_dummy_icp(int i)
175{
176 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
177 (void *)(uintptr_t) i);
178}
179
180static int xics_max_server_number(sPAPRMachineState *spapr)
181{
182 assert(spapr->vsmt);
183 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
184}
185
186static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
187{
188 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
189
190 if (kvm_enabled()) {
191 if (machine_kernel_irqchip_allowed(machine) &&
192 !xics_kvm_init(spapr, errp)) {
193 spapr->icp_type = TYPE_KVM_ICP;
194 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
195 }
196 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
197 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
198 return;
199 }
200 }
201
202 if (!spapr->ics) {
203 xics_spapr_init(spapr);
204 spapr->icp_type = TYPE_ICP;
205 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
206 if (!spapr->ics) {
207 return;
208 }
209 }
210}
211
212static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
213 int smt_threads)
214{
215 int i, ret = 0;
216 uint32_t servers_prop[smt_threads];
217 uint32_t gservers_prop[smt_threads * 2];
218 int index = spapr_get_vcpu_id(cpu);
219
220 if (cpu->compat_pvr) {
221 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
222 if (ret < 0) {
223 return ret;
224 }
225 }
226
227
228 for (i = 0; i < smt_threads; i++) {
229 servers_prop[i] = cpu_to_be32(index + i);
230
231 gservers_prop[i*2] = cpu_to_be32(index + i);
232 gservers_prop[i*2 + 1] = 0;
233 }
234 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
235 servers_prop, sizeof(servers_prop));
236 if (ret < 0) {
237 return ret;
238 }
239 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
240 gservers_prop, sizeof(gservers_prop));
241
242 return ret;
243}
244
245static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
246{
247 int index = spapr_get_vcpu_id(cpu);
248 uint32_t associativity[] = {cpu_to_be32(0x5),
249 cpu_to_be32(0x0),
250 cpu_to_be32(0x0),
251 cpu_to_be32(0x0),
252 cpu_to_be32(cpu->node_id),
253 cpu_to_be32(index)};
254
255
256 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
257 sizeof(associativity));
258}
259
260
261static void spapr_populate_pa_features(sPAPRMachineState *spapr,
262 PowerPCCPU *cpu,
263 void *fdt, int offset,
264 bool legacy_guest)
265{
266 CPUPPCState *env = &cpu->env;
267 uint8_t pa_features_206[] = { 6, 0,
268 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
269 uint8_t pa_features_207[] = { 24, 0,
270 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
271 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
272 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
273 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
274 uint8_t pa_features_300[] = { 66, 0,
275
276
277 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
278
279 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
280
281 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
282
283 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
284
285 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
286
287 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
288
289 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
290
291 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
292
293 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
294
295 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
296
297 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
298 };
299 uint8_t *pa_features = NULL;
300 size_t pa_size;
301
302 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
303 pa_features = pa_features_206;
304 pa_size = sizeof(pa_features_206);
305 }
306 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
307 pa_features = pa_features_207;
308 pa_size = sizeof(pa_features_207);
309 }
310 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
311 pa_features = pa_features_300;
312 pa_size = sizeof(pa_features_300);
313 }
314 if (!pa_features) {
315 return;
316 }
317
318 if (env->ci_large_pages) {
319
320
321
322
323
324
325
326 pa_features[3] |= 0x20;
327 }
328 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
329 pa_features[24] |= 0x80;
330 }
331 if (legacy_guest && pa_size > 40) {
332
333
334
335 pa_features[40 + 2] &= ~0x80;
336 }
337
338 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
339}
340
341static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
342{
343 int ret = 0, offset, cpus_offset;
344 CPUState *cs;
345 char cpu_model[32];
346 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
347
348 CPU_FOREACH(cs) {
349 PowerPCCPU *cpu = POWERPC_CPU(cs);
350 DeviceClass *dc = DEVICE_GET_CLASS(cs);
351 int index = spapr_get_vcpu_id(cpu);
352 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
353
354 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
355 continue;
356 }
357
358 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
359
360 cpus_offset = fdt_path_offset(fdt, "/cpus");
361 if (cpus_offset < 0) {
362 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
363 if (cpus_offset < 0) {
364 return cpus_offset;
365 }
366 }
367 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
368 if (offset < 0) {
369 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
370 if (offset < 0) {
371 return offset;
372 }
373 }
374
375 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
376 pft_size_prop, sizeof(pft_size_prop));
377 if (ret < 0) {
378 return ret;
379 }
380
381 if (nb_numa_nodes > 1) {
382 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
383 if (ret < 0) {
384 return ret;
385 }
386 }
387
388 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
389 if (ret < 0) {
390 return ret;
391 }
392
393 spapr_populate_pa_features(spapr, cpu, fdt, offset,
394 spapr->cas_legacy_guest_workaround);
395 }
396 return ret;
397}
398
399static hwaddr spapr_node0_size(MachineState *machine)
400{
401 if (nb_numa_nodes) {
402 int i;
403 for (i = 0; i < nb_numa_nodes; ++i) {
404 if (numa_info[i].node_mem) {
405 return MIN(pow2floor(numa_info[i].node_mem),
406 machine->ram_size);
407 }
408 }
409 }
410 return machine->ram_size;
411}
412
413static void add_str(GString *s, const gchar *s1)
414{
415 g_string_append_len(s, s1, strlen(s1) + 1);
416}
417
418static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
419 hwaddr size)
420{
421 uint32_t associativity[] = {
422 cpu_to_be32(0x4),
423 cpu_to_be32(0x0), cpu_to_be32(0x0),
424 cpu_to_be32(0x0), cpu_to_be32(nodeid)
425 };
426 char mem_name[32];
427 uint64_t mem_reg_property[2];
428 int off;
429
430 mem_reg_property[0] = cpu_to_be64(start);
431 mem_reg_property[1] = cpu_to_be64(size);
432
433 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
434 off = fdt_add_subnode(fdt, 0, mem_name);
435 _FDT(off);
436 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
437 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
438 sizeof(mem_reg_property))));
439 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
440 sizeof(associativity))));
441 return off;
442}
443
444static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
445{
446 MachineState *machine = MACHINE(spapr);
447 hwaddr mem_start, node_size;
448 int i, nb_nodes = nb_numa_nodes;
449 NodeInfo *nodes = numa_info;
450 NodeInfo ramnode;
451
452
453 if (!nb_numa_nodes) {
454 nb_nodes = 1;
455 ramnode.node_mem = machine->ram_size;
456 nodes = &ramnode;
457 }
458
459 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
460 if (!nodes[i].node_mem) {
461 continue;
462 }
463 if (mem_start >= machine->ram_size) {
464 node_size = 0;
465 } else {
466 node_size = nodes[i].node_mem;
467 if (node_size > machine->ram_size - mem_start) {
468 node_size = machine->ram_size - mem_start;
469 }
470 }
471 if (!mem_start) {
472
473
474 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
475 mem_start += spapr->rma_size;
476 node_size -= spapr->rma_size;
477 }
478 for ( ; node_size; ) {
479 hwaddr sizetmp = pow2floor(node_size);
480
481
482 if (ctzl(mem_start) < ctzl(sizetmp)) {
483 sizetmp = 1ULL << ctzl(mem_start);
484 }
485
486 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
487 node_size -= sizetmp;
488 mem_start += sizetmp;
489 }
490 }
491
492 return 0;
493}
494
495static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
496 sPAPRMachineState *spapr)
497{
498 PowerPCCPU *cpu = POWERPC_CPU(cs);
499 CPUPPCState *env = &cpu->env;
500 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
501 int index = spapr_get_vcpu_id(cpu);
502 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
503 0xffffffff, 0xffffffff};
504 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
505 : SPAPR_TIMEBASE_FREQ;
506 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
507 uint32_t page_sizes_prop[64];
508 size_t page_sizes_prop_size;
509 uint32_t vcpus_per_socket = smp_threads * smp_cores;
510 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
511 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
512 sPAPRDRConnector *drc;
513 int drc_index;
514 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
515 int i;
516
517 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
518 if (drc) {
519 drc_index = spapr_drc_index(drc);
520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
521 }
522
523 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
524 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
525
526 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
527 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
528 env->dcache_line_size)));
529 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
530 env->dcache_line_size)));
531 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
532 env->icache_line_size)));
533 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
534 env->icache_line_size)));
535
536 if (pcc->l1_dcache_size) {
537 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
538 pcc->l1_dcache_size)));
539 } else {
540 warn_report("Unknown L1 dcache size for cpu");
541 }
542 if (pcc->l1_icache_size) {
543 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
544 pcc->l1_icache_size)));
545 } else {
546 warn_report("Unknown L1 icache size for cpu");
547 }
548
549 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
550 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
551 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
552 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
553 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
554 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
555
556 if (env->spr_cb[SPR_PURR].oea_read) {
557 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
558 }
559
560 if (env->mmu_model & POWERPC_MMU_1TSEG) {
561 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
562 segs, sizeof(segs))));
563 }
564
565
566
567
568
569
570
571 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
572 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
573 } else {
574 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
575 }
576
577
578
579
580 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
581 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
582 }
583
584 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
585 sizeof(page_sizes_prop));
586 if (page_sizes_prop_size) {
587 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
588 page_sizes_prop, page_sizes_prop_size)));
589 }
590
591 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
592
593 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
594 cs->cpu_index / vcpus_per_socket)));
595
596 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
597 pft_size_prop, sizeof(pft_size_prop))));
598
599 if (nb_numa_nodes > 1) {
600 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
601 }
602
603 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
604
605 if (pcc->radix_page_info) {
606 for (i = 0; i < pcc->radix_page_info->count; i++) {
607 radix_AP_encodings[i] =
608 cpu_to_be32(pcc->radix_page_info->entries[i]);
609 }
610 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
611 radix_AP_encodings,
612 pcc->radix_page_info->count *
613 sizeof(radix_AP_encodings[0]))));
614 }
615}
616
617static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
618{
619 CPUState *cs;
620 int cpus_offset;
621 char *nodename;
622
623 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
624 _FDT(cpus_offset);
625 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
626 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
627
628
629
630
631
632
633 CPU_FOREACH_REVERSE(cs) {
634 PowerPCCPU *cpu = POWERPC_CPU(cs);
635 int index = spapr_get_vcpu_id(cpu);
636 DeviceClass *dc = DEVICE_GET_CLASS(cs);
637 int offset;
638
639 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
640 continue;
641 }
642
643 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
644 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
645 g_free(nodename);
646 _FDT(offset);
647 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
648 }
649
650}
651
652static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
653{
654 MemoryDeviceInfoList *info;
655
656 for (info = list; info; info = info->next) {
657 MemoryDeviceInfo *value = info->value;
658
659 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
660 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
661
662 if (pcdimm_info->addr >= addr &&
663 addr < (pcdimm_info->addr + pcdimm_info->size)) {
664 return pcdimm_info->node;
665 }
666 }
667 }
668
669 return -1;
670}
671
672
673
674
675
676
677static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
678{
679 MachineState *machine = MACHINE(spapr);
680 int ret, i, offset;
681 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
682 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
683 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
684 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
685 memory_region_size(&spapr->hotplug_memory.mr)) /
686 lmb_size;
687 uint32_t *int_buf, *cur_index, buf_len;
688 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
689 MemoryDeviceInfoList *dimms = NULL;
690
691
692
693
694 if (machine->ram_size == machine->maxram_size) {
695 return 0;
696 }
697
698
699
700
701
702 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
703 * sizeof(uint32_t);
704 cur_index = int_buf = g_malloc0(buf_len);
705
706 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
707
708 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
709 sizeof(prop_lmb_size));
710 if (ret < 0) {
711 goto out;
712 }
713
714 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
715 if (ret < 0) {
716 goto out;
717 }
718
719 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
720 if (ret < 0) {
721 goto out;
722 }
723
724 if (hotplug_lmb_start) {
725 dimms = qmp_pc_dimm_device_list();
726 }
727
728
729 int_buf[0] = cpu_to_be32(nr_lmbs);
730 cur_index++;
731 for (i = 0; i < nr_lmbs; i++) {
732 uint64_t addr = i * lmb_size;
733 uint32_t *dynamic_memory = cur_index;
734
735 if (i >= hotplug_lmb_start) {
736 sPAPRDRConnector *drc;
737
738 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
739 g_assert(drc);
740
741 dynamic_memory[0] = cpu_to_be32(addr >> 32);
742 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
743 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
744 dynamic_memory[3] = cpu_to_be32(0);
745 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
746 if (memory_region_present(get_system_memory(), addr)) {
747 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
748 } else {
749 dynamic_memory[5] = cpu_to_be32(0);
750 }
751 } else {
752
753
754
755
756
757 dynamic_memory[0] = cpu_to_be32(addr >> 32);
758 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
759 dynamic_memory[2] = cpu_to_be32(0);
760 dynamic_memory[3] = cpu_to_be32(0);
761 dynamic_memory[4] = cpu_to_be32(-1);
762 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
763 SPAPR_LMB_FLAGS_DRC_INVALID);
764 }
765
766 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
767 }
768 qapi_free_MemoryDeviceInfoList(dimms);
769 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
770 if (ret < 0) {
771 goto out;
772 }
773
774
775 cur_index = int_buf;
776 int_buf[0] = cpu_to_be32(nr_nodes);
777 int_buf[1] = cpu_to_be32(4);
778 cur_index += 2;
779 for (i = 0; i < nr_nodes; i++) {
780 uint32_t associativity[] = {
781 cpu_to_be32(0x0),
782 cpu_to_be32(0x0),
783 cpu_to_be32(0x0),
784 cpu_to_be32(i)
785 };
786 memcpy(cur_index, associativity, sizeof(associativity));
787 cur_index += 4;
788 }
789 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
790 (cur_index - int_buf) * sizeof(uint32_t));
791out:
792 g_free(int_buf);
793 return ret;
794}
795
796static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
797 sPAPROptionVector *ov5_updates)
798{
799 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
800 int ret = 0, offset;
801
802
803 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
804 g_assert(smc->dr_lmb_enabled);
805 ret = spapr_populate_drconf_memory(spapr, fdt);
806 if (ret) {
807 goto out;
808 }
809 }
810
811 offset = fdt_path_offset(fdt, "/chosen");
812 if (offset < 0) {
813 offset = fdt_add_subnode(fdt, 0, "chosen");
814 if (offset < 0) {
815 return offset;
816 }
817 }
818 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
819 "ibm,architecture-vec-5");
820
821out:
822 return ret;
823}
824
825static bool spapr_hotplugged_dev_before_cas(void)
826{
827 Object *drc_container, *obj;
828 ObjectProperty *prop;
829 ObjectPropertyIterator iter;
830
831 drc_container = container_get(object_get_root(), "/dr-connector");
832 object_property_iter_init(&iter, drc_container);
833 while ((prop = object_property_iter_next(&iter))) {
834 if (!strstart(prop->type, "link<", NULL)) {
835 continue;
836 }
837 obj = object_property_get_link(drc_container, prop->name, NULL);
838 if (spapr_drc_needed(obj)) {
839 return true;
840 }
841 }
842 return false;
843}
844
845int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
846 target_ulong addr, target_ulong size,
847 sPAPROptionVector *ov5_updates)
848{
849 void *fdt, *fdt_skel;
850 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
851
852 if (spapr_hotplugged_dev_before_cas()) {
853 return 1;
854 }
855
856 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
857 error_report("SLOF provided an unexpected CAS buffer size "
858 TARGET_FMT_lu " (min: %zu, max: %u)",
859 size, sizeof(hdr), FW_MAX_SIZE);
860 exit(EXIT_FAILURE);
861 }
862
863 size -= sizeof(hdr);
864
865
866 fdt_skel = g_malloc0(size);
867 _FDT((fdt_create(fdt_skel, size)));
868 _FDT((fdt_finish_reservemap(fdt_skel)));
869 _FDT((fdt_begin_node(fdt_skel, "")));
870 _FDT((fdt_end_node(fdt_skel)));
871 _FDT((fdt_finish(fdt_skel)));
872 fdt = g_malloc0(size);
873 _FDT((fdt_open_into(fdt_skel, fdt, size)));
874 g_free(fdt_skel);
875
876
877 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
878
879 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
880 return -1;
881 }
882
883
884 _FDT((fdt_pack(fdt)));
885
886 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
887 trace_spapr_cas_failed(size);
888 return -1;
889 }
890
891 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
892 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
893 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
894 g_free(fdt);
895
896 return 0;
897}
898
899static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
900{
901 int rtas;
902 GString *hypertas = g_string_sized_new(256);
903 GString *qemu_hypertas = g_string_sized_new(256);
904 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
905 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
906 memory_region_size(&spapr->hotplug_memory.mr);
907 uint32_t lrdr_capacity[] = {
908 cpu_to_be32(max_hotplug_addr >> 32),
909 cpu_to_be32(max_hotplug_addr & 0xffffffff),
910 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
911 cpu_to_be32(max_cpus / smp_threads),
912 };
913
914 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
915
916
917 add_str(hypertas, "hcall-pft");
918 add_str(hypertas, "hcall-term");
919 add_str(hypertas, "hcall-dabr");
920 add_str(hypertas, "hcall-interrupt");
921 add_str(hypertas, "hcall-tce");
922 add_str(hypertas, "hcall-vio");
923 add_str(hypertas, "hcall-splpar");
924 add_str(hypertas, "hcall-bulk");
925 add_str(hypertas, "hcall-set-mode");
926 add_str(hypertas, "hcall-sprg0");
927 add_str(hypertas, "hcall-copy");
928 add_str(hypertas, "hcall-debug");
929 add_str(qemu_hypertas, "hcall-memop1");
930
931 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
932 add_str(hypertas, "hcall-multi-tce");
933 }
934
935 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
936 add_str(hypertas, "hcall-hpt-resize");
937 }
938
939 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
940 hypertas->str, hypertas->len));
941 g_string_free(hypertas, TRUE);
942 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
943 qemu_hypertas->str, qemu_hypertas->len));
944 g_string_free(qemu_hypertas, TRUE);
945
946 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
947 refpoints, sizeof(refpoints)));
948
949 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
950 RTAS_ERROR_LOG_MAX));
951 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
952 RTAS_EVENT_SCAN_RATE));
953
954 g_assert(msi_nonbroken);
955 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
956
957
958
959
960
961
962
963
964 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
965
966 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
967 lrdr_capacity, sizeof(lrdr_capacity)));
968
969 spapr_dt_rtas_tokens(fdt, rtas);
970}
971
972
973
974
975static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
976{
977 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
978
979 char val[2 * 4] = {
980 23, 0x00,
981 24, 0x00,
982 25, 0x00,
983 26, 0x40,
984 };
985
986 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
987 first_ppc_cpu->compat_pvr)) {
988
989 val[3] = 0x00;
990 } else if (kvm_enabled()) {
991 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
992 val[3] = 0x80;
993 } else if (kvmppc_has_cap_mmu_radix()) {
994 val[3] = 0x40;
995 } else {
996 val[3] = 0x00;
997 }
998 } else {
999
1000 val[3] = 0xC0;
1001 }
1002 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1003 val, sizeof(val)));
1004}
1005
1006static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1007{
1008 MachineState *machine = MACHINE(spapr);
1009 int chosen;
1010 const char *boot_device = machine->boot_order;
1011 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1012 size_t cb = 0;
1013 char *bootlist = get_boot_devices_list(&cb, true);
1014
1015 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1016
1017 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1018 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1019 spapr->initrd_base));
1020 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1021 spapr->initrd_base + spapr->initrd_size));
1022
1023 if (spapr->kernel_size) {
1024 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1025 cpu_to_be64(spapr->kernel_size) };
1026
1027 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1028 &kprop, sizeof(kprop)));
1029 if (spapr->kernel_le) {
1030 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1031 }
1032 }
1033 if (boot_menu) {
1034 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1035 }
1036 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1037 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1038 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1039
1040 if (cb && bootlist) {
1041 int i;
1042
1043 for (i = 0; i < cb; i++) {
1044 if (bootlist[i] == '\n') {
1045 bootlist[i] = ' ';
1046 }
1047 }
1048 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1049 }
1050
1051 if (boot_device && strlen(boot_device)) {
1052 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1053 }
1054
1055 if (!spapr->has_graphics && stdout_path) {
1056
1057
1058
1059
1060
1061
1062 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1063 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1064 }
1065
1066 spapr_dt_ov5_platform_support(fdt, chosen);
1067
1068 g_free(stdout_path);
1069 g_free(bootlist);
1070}
1071
1072static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1073{
1074
1075
1076 int hypervisor;
1077 uint8_t hypercall[16];
1078
1079 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1080
1081 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1082 if (kvmppc_has_cap_fixup_hcalls()) {
1083
1084
1085
1086
1087 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1088 sizeof(hypercall))) {
1089 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1090 hypercall, sizeof(hypercall)));
1091 }
1092 }
1093}
1094
1095static void *spapr_build_fdt(sPAPRMachineState *spapr,
1096 hwaddr rtas_addr,
1097 hwaddr rtas_size)
1098{
1099 MachineState *machine = MACHINE(spapr);
1100 MachineClass *mc = MACHINE_GET_CLASS(machine);
1101 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1102 int ret;
1103 void *fdt;
1104 sPAPRPHBState *phb;
1105 char *buf;
1106
1107 fdt = g_malloc0(FDT_MAX_SIZE);
1108 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1109
1110
1111 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1112 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1113 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1114
1115
1116
1117
1118
1119 if (kvmppc_get_host_model(&buf)) {
1120 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1121 g_free(buf);
1122 }
1123 if (kvmppc_get_host_serial(&buf)) {
1124 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1125 g_free(buf);
1126 }
1127
1128 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1129
1130 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1131 if (qemu_uuid_set) {
1132 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1133 }
1134 g_free(buf);
1135
1136 if (qemu_get_vm_name()) {
1137 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1138 qemu_get_vm_name()));
1139 }
1140
1141 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1142 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1143
1144
1145 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP);
1146
1147 ret = spapr_populate_memory(spapr, fdt);
1148 if (ret < 0) {
1149 error_report("couldn't setup memory nodes in fdt");
1150 exit(1);
1151 }
1152
1153
1154 spapr_dt_vdevice(spapr->vio_bus, fdt);
1155
1156 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1157 ret = spapr_rng_populate_dt(fdt);
1158 if (ret < 0) {
1159 error_report("could not set up rng device in the fdt");
1160 exit(1);
1161 }
1162 }
1163
1164 QLIST_FOREACH(phb, &spapr->phbs, list) {
1165 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1166 if (ret < 0) {
1167 error_report("couldn't setup PCI devices in fdt");
1168 exit(1);
1169 }
1170 }
1171
1172
1173 spapr_populate_cpus_dt_node(fdt, spapr);
1174
1175 if (smc->dr_lmb_enabled) {
1176 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1177 }
1178
1179 if (mc->has_hotpluggable_cpus) {
1180 int offset = fdt_path_offset(fdt, "/cpus");
1181 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1182 SPAPR_DR_CONNECTOR_TYPE_CPU);
1183 if (ret < 0) {
1184 error_report("Couldn't set up CPU DR device tree properties");
1185 exit(1);
1186 }
1187 }
1188
1189
1190 spapr_dt_events(spapr, fdt);
1191
1192
1193 spapr_dt_rtas(spapr, fdt);
1194
1195
1196 spapr_dt_chosen(spapr, fdt);
1197
1198
1199 if (kvm_enabled()) {
1200 spapr_dt_hypervisor(spapr, fdt);
1201 }
1202
1203
1204 if (spapr->kernel_size) {
1205 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1206 }
1207 if (spapr->initrd_size) {
1208 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1209 }
1210
1211
1212 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1213 if (ret < 0) {
1214 error_report("couldn't setup CAS properties fdt");
1215 exit(1);
1216 }
1217
1218 return fdt;
1219}
1220
1221static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1222{
1223 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1224}
1225
1226static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1227 PowerPCCPU *cpu)
1228{
1229 CPUPPCState *env = &cpu->env;
1230
1231
1232 g_assert(qemu_mutex_iothread_locked());
1233
1234 if (msr_pr) {
1235 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1236 env->gpr[3] = H_PRIVILEGE;
1237 } else {
1238 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1239 }
1240}
1241
1242static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1243{
1244 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1245
1246 return spapr->patb_entry;
1247}
1248
1249#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1250#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1251#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1252#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1253#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1254
1255
1256
1257
1258static int get_htab_fd(sPAPRMachineState *spapr)
1259{
1260 Error *local_err = NULL;
1261
1262 if (spapr->htab_fd >= 0) {
1263 return spapr->htab_fd;
1264 }
1265
1266 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1267 if (spapr->htab_fd < 0) {
1268 error_report_err(local_err);
1269 }
1270
1271 return spapr->htab_fd;
1272}
1273
1274void close_htab_fd(sPAPRMachineState *spapr)
1275{
1276 if (spapr->htab_fd >= 0) {
1277 close(spapr->htab_fd);
1278 }
1279 spapr->htab_fd = -1;
1280}
1281
1282static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1283{
1284 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1285
1286 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1287}
1288
1289static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1290{
1291 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1292
1293 assert(kvm_enabled());
1294
1295 if (!spapr->htab) {
1296 return 0;
1297 }
1298
1299 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1300}
1301
1302static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1303 hwaddr ptex, int n)
1304{
1305 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1306 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1307
1308 if (!spapr->htab) {
1309
1310
1311
1312 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1313 kvmppc_read_hptes(hptes, ptex, n);
1314 return hptes;
1315 }
1316
1317
1318
1319
1320
1321 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1322}
1323
1324static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1325 const ppc_hash_pte64_t *hptes,
1326 hwaddr ptex, int n)
1327{
1328 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1329
1330 if (!spapr->htab) {
1331 g_free((void *)hptes);
1332 }
1333
1334
1335}
1336
1337static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1338 uint64_t pte0, uint64_t pte1)
1339{
1340 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1341 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1342
1343 if (!spapr->htab) {
1344 kvmppc_write_hpte(ptex, pte0, pte1);
1345 } else {
1346 stq_p(spapr->htab + offset, pte0);
1347 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1348 }
1349}
1350
1351int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1352{
1353 int shift;
1354
1355
1356
1357
1358 shift = ctz64(pow2ceil(ramsize)) - 7;
1359 shift = MAX(shift, 18);
1360 shift = MIN(shift, 46);
1361 return shift;
1362}
1363
1364void spapr_free_hpt(sPAPRMachineState *spapr)
1365{
1366 g_free(spapr->htab);
1367 spapr->htab = NULL;
1368 spapr->htab_shift = 0;
1369 close_htab_fd(spapr);
1370}
1371
1372void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1373 Error **errp)
1374{
1375 long rc;
1376
1377
1378 spapr_free_hpt(spapr);
1379
1380 rc = kvmppc_reset_htab(shift);
1381 if (rc < 0) {
1382
1383 error_setg_errno(errp, errno,
1384 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1385 shift);
1386
1387
1388 } else if (rc > 0) {
1389
1390 if (rc != shift) {
1391 error_setg(errp,
1392 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1393 shift, rc);
1394 }
1395
1396 spapr->htab_shift = shift;
1397 spapr->htab = NULL;
1398 } else {
1399
1400 size_t size = 1ULL << shift;
1401 int i;
1402
1403 spapr->htab = qemu_memalign(size, size);
1404 if (!spapr->htab) {
1405 error_setg_errno(errp, errno,
1406 "Could not allocate HPT of order %d", shift);
1407 return;
1408 }
1409
1410 memset(spapr->htab, 0, size);
1411 spapr->htab_shift = shift;
1412
1413 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1414 DIRTY_HPTE(HPTE(spapr->htab, i));
1415 }
1416 }
1417
1418 spapr->patb_entry = 0;
1419}
1420
1421void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1422{
1423 int hpt_shift;
1424
1425 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1426 || (spapr->cas_reboot
1427 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1428 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1429 } else {
1430 uint64_t current_ram_size;
1431
1432 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1433 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1434 }
1435 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1436
1437 if (spapr->vrma_adjust) {
1438 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1439 spapr->htab_shift);
1440 }
1441}
1442
1443static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1444{
1445 bool matched = false;
1446
1447 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1448 matched = true;
1449 }
1450
1451 if (!matched) {
1452 error_report("Device %s is not supported by this machine yet.",
1453 qdev_fw_name(DEVICE(sbdev)));
1454 exit(1);
1455 }
1456}
1457
1458static int spapr_reset_drcs(Object *child, void *opaque)
1459{
1460 sPAPRDRConnector *drc =
1461 (sPAPRDRConnector *) object_dynamic_cast(child,
1462 TYPE_SPAPR_DR_CONNECTOR);
1463
1464 if (drc) {
1465 spapr_drc_reset(drc);
1466 }
1467
1468 return 0;
1469}
1470
1471static void spapr_machine_reset(void)
1472{
1473 MachineState *machine = MACHINE(qdev_get_machine());
1474 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1475 PowerPCCPU *first_ppc_cpu;
1476 uint32_t rtas_limit;
1477 hwaddr rtas_addr, fdt_addr;
1478 void *fdt;
1479 int rc;
1480
1481
1482 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1483
1484 spapr_caps_reset(spapr);
1485
1486 first_ppc_cpu = POWERPC_CPU(first_cpu);
1487 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1488 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1489 spapr->max_compat_pvr)) {
1490
1491
1492
1493 spapr->patb_entry = PATBE1_GR;
1494 } else {
1495 spapr_setup_hpt_and_vrma(spapr);
1496 }
1497
1498
1499
1500 if (!spapr->cas_reboot) {
1501 spapr_ovec_cleanup(spapr->ov5_cas);
1502 spapr->ov5_cas = spapr_ovec_new();
1503
1504 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1505 }
1506
1507 qemu_devices_reset();
1508
1509
1510
1511
1512
1513
1514 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1515
1516 spapr_clear_pending_events(spapr);
1517
1518
1519
1520
1521
1522
1523 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1524 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1525 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1526
1527 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1528
1529 spapr_load_rtas(spapr, fdt, rtas_addr);
1530
1531 rc = fdt_pack(fdt);
1532
1533
1534 assert(rc == 0);
1535
1536 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1537 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1538 fdt_totalsize(fdt), FDT_MAX_SIZE);
1539 exit(1);
1540 }
1541
1542
1543 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1544 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1545 g_free(fdt);
1546
1547
1548 first_ppc_cpu->env.gpr[3] = fdt_addr;
1549 first_ppc_cpu->env.gpr[5] = 0;
1550 first_cpu->halted = 0;
1551 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1552
1553 spapr->cas_reboot = false;
1554}
1555
1556static void spapr_create_nvram(sPAPRMachineState *spapr)
1557{
1558 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1559 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1560
1561 if (dinfo) {
1562 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1563 &error_fatal);
1564 }
1565
1566 qdev_init_nofail(dev);
1567
1568 spapr->nvram = (struct sPAPRNVRAM *)dev;
1569}
1570
1571static void spapr_rtc_create(sPAPRMachineState *spapr)
1572{
1573 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1574 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1575 &error_fatal);
1576 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1577 &error_fatal);
1578 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1579 "date", &error_fatal);
1580}
1581
1582
1583static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1584{
1585 switch (vga_interface_type) {
1586 case VGA_NONE:
1587 return false;
1588 case VGA_DEVICE:
1589 return true;
1590 case VGA_STD:
1591 case VGA_VIRTIO:
1592 return pci_vga_init(pci_bus) != NULL;
1593 default:
1594 error_setg(errp,
1595 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1596 return false;
1597 }
1598}
1599
1600static int spapr_pre_load(void *opaque)
1601{
1602 int rc;
1603
1604 rc = spapr_caps_pre_load(opaque);
1605 if (rc) {
1606 return rc;
1607 }
1608
1609 return 0;
1610}
1611
1612static int spapr_post_load(void *opaque, int version_id)
1613{
1614 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1615 int err = 0;
1616
1617 err = spapr_caps_post_migration(spapr);
1618 if (err) {
1619 return err;
1620 }
1621
1622 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1623 CPUState *cs;
1624 CPU_FOREACH(cs) {
1625 PowerPCCPU *cpu = POWERPC_CPU(cs);
1626 icp_resend(ICP(cpu->intc));
1627 }
1628 }
1629
1630
1631
1632
1633
1634 if (version_id < 3) {
1635 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1636 }
1637
1638 if (kvm_enabled() && spapr->patb_entry) {
1639 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1640 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1641 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1642
1643 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1644 if (err) {
1645 error_report("Process table config unsupported by the host");
1646 return -EINVAL;
1647 }
1648 }
1649
1650 return err;
1651}
1652
1653static int spapr_pre_save(void *opaque)
1654{
1655 int rc;
1656
1657 rc = spapr_caps_pre_save(opaque);
1658 if (rc) {
1659 return rc;
1660 }
1661
1662 return 0;
1663}
1664
1665static bool version_before_3(void *opaque, int version_id)
1666{
1667 return version_id < 3;
1668}
1669
1670static bool spapr_pending_events_needed(void *opaque)
1671{
1672 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1673 return !QTAILQ_EMPTY(&spapr->pending_events);
1674}
1675
1676static const VMStateDescription vmstate_spapr_event_entry = {
1677 .name = "spapr_event_log_entry",
1678 .version_id = 1,
1679 .minimum_version_id = 1,
1680 .fields = (VMStateField[]) {
1681 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1682 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1683 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1684 NULL, extended_length),
1685 VMSTATE_END_OF_LIST()
1686 },
1687};
1688
1689static const VMStateDescription vmstate_spapr_pending_events = {
1690 .name = "spapr_pending_events",
1691 .version_id = 1,
1692 .minimum_version_id = 1,
1693 .needed = spapr_pending_events_needed,
1694 .fields = (VMStateField[]) {
1695 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1696 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1697 VMSTATE_END_OF_LIST()
1698 },
1699};
1700
1701static bool spapr_ov5_cas_needed(void *opaque)
1702{
1703 sPAPRMachineState *spapr = opaque;
1704 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1705 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1706 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1707 bool cas_needed;
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1734 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1735
1736
1737
1738
1739
1740
1741 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1742 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1743
1744 spapr_ovec_cleanup(ov5_mask);
1745 spapr_ovec_cleanup(ov5_legacy);
1746 spapr_ovec_cleanup(ov5_removed);
1747
1748 return cas_needed;
1749}
1750
1751static const VMStateDescription vmstate_spapr_ov5_cas = {
1752 .name = "spapr_option_vector_ov5_cas",
1753 .version_id = 1,
1754 .minimum_version_id = 1,
1755 .needed = spapr_ov5_cas_needed,
1756 .fields = (VMStateField[]) {
1757 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1758 vmstate_spapr_ovec, sPAPROptionVector),
1759 VMSTATE_END_OF_LIST()
1760 },
1761};
1762
1763static bool spapr_patb_entry_needed(void *opaque)
1764{
1765 sPAPRMachineState *spapr = opaque;
1766
1767 return !!spapr->patb_entry;
1768}
1769
1770static const VMStateDescription vmstate_spapr_patb_entry = {
1771 .name = "spapr_patb_entry",
1772 .version_id = 1,
1773 .minimum_version_id = 1,
1774 .needed = spapr_patb_entry_needed,
1775 .fields = (VMStateField[]) {
1776 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1777 VMSTATE_END_OF_LIST()
1778 },
1779};
1780
1781static const VMStateDescription vmstate_spapr = {
1782 .name = "spapr",
1783 .version_id = 3,
1784 .minimum_version_id = 1,
1785 .pre_load = spapr_pre_load,
1786 .post_load = spapr_post_load,
1787 .pre_save = spapr_pre_save,
1788 .fields = (VMStateField[]) {
1789
1790 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1791
1792
1793 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1794
1795 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1796 VMSTATE_END_OF_LIST()
1797 },
1798 .subsections = (const VMStateDescription*[]) {
1799 &vmstate_spapr_ov5_cas,
1800 &vmstate_spapr_patb_entry,
1801 &vmstate_spapr_pending_events,
1802 &vmstate_spapr_cap_htm,
1803 &vmstate_spapr_cap_vsx,
1804 &vmstate_spapr_cap_dfp,
1805 &vmstate_spapr_cap_cfpc,
1806 &vmstate_spapr_cap_sbbc,
1807 &vmstate_spapr_cap_ibs,
1808 NULL
1809 }
1810};
1811
1812static int htab_save_setup(QEMUFile *f, void *opaque)
1813{
1814 sPAPRMachineState *spapr = opaque;
1815
1816
1817 if (!spapr->htab_shift) {
1818 qemu_put_be32(f, -1);
1819 } else {
1820 qemu_put_be32(f, spapr->htab_shift);
1821 }
1822
1823 if (spapr->htab) {
1824 spapr->htab_save_index = 0;
1825 spapr->htab_first_pass = true;
1826 } else {
1827 if (spapr->htab_shift) {
1828 assert(kvm_enabled());
1829 }
1830 }
1831
1832
1833 return 0;
1834}
1835
1836static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1837 int chunkstart, int n_valid, int n_invalid)
1838{
1839 qemu_put_be32(f, chunkstart);
1840 qemu_put_be16(f, n_valid);
1841 qemu_put_be16(f, n_invalid);
1842 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1843 HASH_PTE_SIZE_64 * n_valid);
1844}
1845
1846static void htab_save_end_marker(QEMUFile *f)
1847{
1848 qemu_put_be32(f, 0);
1849 qemu_put_be16(f, 0);
1850 qemu_put_be16(f, 0);
1851}
1852
1853static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1854 int64_t max_ns)
1855{
1856 bool has_timeout = max_ns != -1;
1857 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1858 int index = spapr->htab_save_index;
1859 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1860
1861 assert(spapr->htab_first_pass);
1862
1863 do {
1864 int chunkstart;
1865
1866
1867 while ((index < htabslots)
1868 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1869 CLEAN_HPTE(HPTE(spapr->htab, index));
1870 index++;
1871 }
1872
1873
1874 chunkstart = index;
1875 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1876 && HPTE_VALID(HPTE(spapr->htab, index))) {
1877 CLEAN_HPTE(HPTE(spapr->htab, index));
1878 index++;
1879 }
1880
1881 if (index > chunkstart) {
1882 int n_valid = index - chunkstart;
1883
1884 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
1885
1886 if (has_timeout &&
1887 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1888 break;
1889 }
1890 }
1891 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1892
1893 if (index >= htabslots) {
1894 assert(index == htabslots);
1895 index = 0;
1896 spapr->htab_first_pass = false;
1897 }
1898 spapr->htab_save_index = index;
1899}
1900
1901static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1902 int64_t max_ns)
1903{
1904 bool final = max_ns < 0;
1905 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1906 int examined = 0, sent = 0;
1907 int index = spapr->htab_save_index;
1908 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1909
1910 assert(!spapr->htab_first_pass);
1911
1912 do {
1913 int chunkstart, invalidstart;
1914
1915
1916 while ((index < htabslots)
1917 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1918 index++;
1919 examined++;
1920 }
1921
1922 chunkstart = index;
1923
1924 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1925 && HPTE_DIRTY(HPTE(spapr->htab, index))
1926 && HPTE_VALID(HPTE(spapr->htab, index))) {
1927 CLEAN_HPTE(HPTE(spapr->htab, index));
1928 index++;
1929 examined++;
1930 }
1931
1932 invalidstart = index;
1933
1934 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1935 && HPTE_DIRTY(HPTE(spapr->htab, index))
1936 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1937 CLEAN_HPTE(HPTE(spapr->htab, index));
1938 index++;
1939 examined++;
1940 }
1941
1942 if (index > chunkstart) {
1943 int n_valid = invalidstart - chunkstart;
1944 int n_invalid = index - invalidstart;
1945
1946 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
1947 sent += index - chunkstart;
1948
1949 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1950 break;
1951 }
1952 }
1953
1954 if (examined >= htabslots) {
1955 break;
1956 }
1957
1958 if (index >= htabslots) {
1959 assert(index == htabslots);
1960 index = 0;
1961 }
1962 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1963
1964 if (index >= htabslots) {
1965 assert(index == htabslots);
1966 index = 0;
1967 }
1968
1969 spapr->htab_save_index = index;
1970
1971 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1972}
1973
1974#define MAX_ITERATION_NS 5000000
1975#define MAX_KVM_BUF_SIZE 2048
1976
1977static int htab_save_iterate(QEMUFile *f, void *opaque)
1978{
1979 sPAPRMachineState *spapr = opaque;
1980 int fd;
1981 int rc = 0;
1982
1983
1984 if (!spapr->htab_shift) {
1985 qemu_put_be32(f, -1);
1986 return 1;
1987 } else {
1988 qemu_put_be32(f, 0);
1989 }
1990
1991 if (!spapr->htab) {
1992 assert(kvm_enabled());
1993
1994 fd = get_htab_fd(spapr);
1995 if (fd < 0) {
1996 return fd;
1997 }
1998
1999 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2000 if (rc < 0) {
2001 return rc;
2002 }
2003 } else if (spapr->htab_first_pass) {
2004 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2005 } else {
2006 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2007 }
2008
2009 htab_save_end_marker(f);
2010
2011 return rc;
2012}
2013
2014static int htab_save_complete(QEMUFile *f, void *opaque)
2015{
2016 sPAPRMachineState *spapr = opaque;
2017 int fd;
2018
2019
2020 if (!spapr->htab_shift) {
2021 qemu_put_be32(f, -1);
2022 return 0;
2023 } else {
2024 qemu_put_be32(f, 0);
2025 }
2026
2027 if (!spapr->htab) {
2028 int rc;
2029
2030 assert(kvm_enabled());
2031
2032 fd = get_htab_fd(spapr);
2033 if (fd < 0) {
2034 return fd;
2035 }
2036
2037 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2038 if (rc < 0) {
2039 return rc;
2040 }
2041 } else {
2042 if (spapr->htab_first_pass) {
2043 htab_save_first_pass(f, spapr, -1);
2044 }
2045 htab_save_later_pass(f, spapr, -1);
2046 }
2047
2048
2049 htab_save_end_marker(f);
2050
2051 return 0;
2052}
2053
2054static int htab_load(QEMUFile *f, void *opaque, int version_id)
2055{
2056 sPAPRMachineState *spapr = opaque;
2057 uint32_t section_hdr;
2058 int fd = -1;
2059 Error *local_err = NULL;
2060
2061 if (version_id < 1 || version_id > 1) {
2062 error_report("htab_load() bad version");
2063 return -EINVAL;
2064 }
2065
2066 section_hdr = qemu_get_be32(f);
2067
2068 if (section_hdr == -1) {
2069 spapr_free_hpt(spapr);
2070 return 0;
2071 }
2072
2073 if (section_hdr) {
2074
2075 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2076 if (local_err) {
2077 error_report_err(local_err);
2078 return -EINVAL;
2079 }
2080 return 0;
2081 }
2082
2083 if (!spapr->htab) {
2084 assert(kvm_enabled());
2085
2086 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2087 if (fd < 0) {
2088 error_report_err(local_err);
2089 return fd;
2090 }
2091 }
2092
2093 while (true) {
2094 uint32_t index;
2095 uint16_t n_valid, n_invalid;
2096
2097 index = qemu_get_be32(f);
2098 n_valid = qemu_get_be16(f);
2099 n_invalid = qemu_get_be16(f);
2100
2101 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2102
2103 break;
2104 }
2105
2106 if ((index + n_valid + n_invalid) >
2107 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2108
2109 error_report(
2110 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2111 index, n_valid, n_invalid, spapr->htab_shift);
2112 return -EINVAL;
2113 }
2114
2115 if (spapr->htab) {
2116 if (n_valid) {
2117 qemu_get_buffer(f, HPTE(spapr->htab, index),
2118 HASH_PTE_SIZE_64 * n_valid);
2119 }
2120 if (n_invalid) {
2121 memset(HPTE(spapr->htab, index + n_valid), 0,
2122 HASH_PTE_SIZE_64 * n_invalid);
2123 }
2124 } else {
2125 int rc;
2126
2127 assert(fd >= 0);
2128
2129 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2130 if (rc < 0) {
2131 return rc;
2132 }
2133 }
2134 }
2135
2136 if (!spapr->htab) {
2137 assert(fd >= 0);
2138 close(fd);
2139 }
2140
2141 return 0;
2142}
2143
2144static void htab_save_cleanup(void *opaque)
2145{
2146 sPAPRMachineState *spapr = opaque;
2147
2148 close_htab_fd(spapr);
2149}
2150
2151static SaveVMHandlers savevm_htab_handlers = {
2152 .save_setup = htab_save_setup,
2153 .save_live_iterate = htab_save_iterate,
2154 .save_live_complete_precopy = htab_save_complete,
2155 .save_cleanup = htab_save_cleanup,
2156 .load_state = htab_load,
2157};
2158
2159static void spapr_boot_set(void *opaque, const char *boot_device,
2160 Error **errp)
2161{
2162 MachineState *machine = MACHINE(opaque);
2163 machine->boot_order = g_strdup(boot_device);
2164}
2165
2166static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2167{
2168 MachineState *machine = MACHINE(spapr);
2169 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2170 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2171 int i;
2172
2173 for (i = 0; i < nr_lmbs; i++) {
2174 uint64_t addr;
2175
2176 addr = i * lmb_size + spapr->hotplug_memory.base;
2177 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2178 addr / lmb_size);
2179 }
2180}
2181
2182
2183
2184
2185
2186
2187static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2188{
2189 int i;
2190
2191 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2192 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2193 " is not aligned to %llu MiB",
2194 machine->ram_size,
2195 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2196 return;
2197 }
2198
2199 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2200 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2201 " is not aligned to %llu MiB",
2202 machine->ram_size,
2203 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2204 return;
2205 }
2206
2207 for (i = 0; i < nb_numa_nodes; i++) {
2208 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2209 error_setg(errp,
2210 "Node %d memory size 0x%" PRIx64
2211 " is not aligned to %llu MiB",
2212 i, numa_info[i].node_mem,
2213 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2214 return;
2215 }
2216 }
2217}
2218
2219
2220static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2221{
2222 int index = id / smp_threads;
2223
2224 if (index >= ms->possible_cpus->len) {
2225 return NULL;
2226 }
2227 if (idx) {
2228 *idx = index;
2229 }
2230 return &ms->possible_cpus->cpus[index];
2231}
2232
2233static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2234{
2235 Error *local_err = NULL;
2236 bool vsmt_user = !!spapr->vsmt;
2237 int kvm_smt = kvmppc_smt_threads();
2238 int ret;
2239
2240 if (!kvm_enabled() && (smp_threads > 1)) {
2241 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2242 "on a pseries machine");
2243 goto out;
2244 }
2245 if (!is_power_of_2(smp_threads)) {
2246 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2247 "machine because it must be a power of 2", smp_threads);
2248 goto out;
2249 }
2250
2251
2252 if (vsmt_user) {
2253 if (spapr->vsmt < smp_threads) {
2254 error_setg(&local_err, "Cannot support VSMT mode %d"
2255 " because it must be >= threads/core (%d)",
2256 spapr->vsmt, smp_threads);
2257 goto out;
2258 }
2259
2260 } else {
2261
2262
2263
2264
2265
2266
2267
2268 spapr->vsmt = MAX(8, smp_threads);
2269 }
2270
2271
2272 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2273 ret = kvmppc_set_smt_threads(spapr->vsmt);
2274 if (ret) {
2275
2276 error_setg(&local_err,
2277 "Failed to set KVM's VSMT mode to %d (errno %d)",
2278 spapr->vsmt, ret);
2279
2280
2281
2282
2283 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2284 warn_report_err(local_err);
2285 local_err = NULL;
2286 goto out;
2287 } else {
2288 if (!vsmt_user) {
2289 error_append_hint(&local_err,
2290 "On PPC, a VM with %d threads/core"
2291 " on a host with %d threads/core"
2292 " requires the use of VSMT mode %d.\n",
2293 smp_threads, kvm_smt, spapr->vsmt);
2294 }
2295 kvmppc_hint_smt_possible(&local_err);
2296 goto out;
2297 }
2298 }
2299 }
2300
2301out:
2302 error_propagate(errp, local_err);
2303}
2304
2305static void spapr_init_cpus(sPAPRMachineState *spapr)
2306{
2307 MachineState *machine = MACHINE(spapr);
2308 MachineClass *mc = MACHINE_GET_CLASS(machine);
2309 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2310 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2311 const CPUArchIdList *possible_cpus;
2312 int boot_cores_nr = smp_cpus / smp_threads;
2313 int i;
2314
2315 possible_cpus = mc->possible_cpu_arch_ids(machine);
2316 if (mc->has_hotpluggable_cpus) {
2317 if (smp_cpus % smp_threads) {
2318 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2319 smp_cpus, smp_threads);
2320 exit(1);
2321 }
2322 if (max_cpus % smp_threads) {
2323 error_report("max_cpus (%u) must be multiple of threads (%u)",
2324 max_cpus, smp_threads);
2325 exit(1);
2326 }
2327 } else {
2328 if (max_cpus != smp_cpus) {
2329 error_report("This machine version does not support CPU hotplug");
2330 exit(1);
2331 }
2332 boot_cores_nr = possible_cpus->len;
2333 }
2334
2335
2336
2337
2338 spapr_set_vsmt_mode(spapr, &error_fatal);
2339
2340 if (smc->pre_2_10_has_unused_icps) {
2341 int i;
2342
2343 for (i = 0; i < xics_max_server_number(spapr); i++) {
2344
2345
2346
2347 pre_2_10_vmstate_register_dummy_icp(i);
2348 }
2349 }
2350
2351 for (i = 0; i < possible_cpus->len; i++) {
2352 int core_id = i * smp_threads;
2353
2354 if (mc->has_hotpluggable_cpus) {
2355 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2356 spapr_vcpu_id(spapr, core_id));
2357 }
2358
2359 if (i < boot_cores_nr) {
2360 Object *core = object_new(type);
2361 int nr_threads = smp_threads;
2362
2363
2364 if ((i + 1) * smp_threads >= smp_cpus) {
2365 nr_threads = smp_cpus - i * smp_threads;
2366 }
2367
2368 object_property_set_int(core, nr_threads, "nr-threads",
2369 &error_fatal);
2370 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2371 &error_fatal);
2372 object_property_set_bool(core, true, "realized", &error_fatal);
2373 }
2374 }
2375}
2376
2377
2378static void spapr_machine_init(MachineState *machine)
2379{
2380 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2381 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2382 const char *kernel_filename = machine->kernel_filename;
2383 const char *initrd_filename = machine->initrd_filename;
2384 PCIHostState *phb;
2385 int i;
2386 MemoryRegion *sysmem = get_system_memory();
2387 MemoryRegion *ram = g_new(MemoryRegion, 1);
2388 MemoryRegion *rma_region;
2389 void *rma = NULL;
2390 hwaddr rma_alloc_size;
2391 hwaddr node0_size = spapr_node0_size(machine);
2392 long load_limit, fw_size;
2393 char *filename;
2394 Error *resize_hpt_err = NULL;
2395
2396 msi_nonbroken = true;
2397
2398 QLIST_INIT(&spapr->phbs);
2399 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2400
2401
2402 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2403 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2404
2405
2406
2407
2408
2409
2410 if (resize_hpt_err) {
2411 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2412 error_free(resize_hpt_err);
2413 resize_hpt_err = NULL;
2414 } else {
2415 spapr->resize_hpt = smc->resize_hpt_default;
2416 }
2417 }
2418
2419 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2420
2421 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2422
2423
2424
2425 error_report_err(resize_hpt_err);
2426 exit(1);
2427 }
2428
2429
2430 rma_alloc_size = kvmppc_alloc_rma(&rma);
2431
2432 if (rma_alloc_size == -1) {
2433 error_report("Unable to create RMA");
2434 exit(1);
2435 }
2436
2437 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2438 spapr->rma_size = rma_alloc_size;
2439 } else {
2440 spapr->rma_size = node0_size;
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451 if (kvm_enabled()) {
2452 spapr->vrma_adjust = 1;
2453 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2454 }
2455
2456
2457
2458
2459
2460
2461 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2462 }
2463
2464 if (spapr->rma_size > node0_size) {
2465 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2466 spapr->rma_size);
2467 exit(1);
2468 }
2469
2470
2471 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2472
2473
2474 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2475
2476
2477
2478 spapr->ov5 = spapr_ovec_new();
2479 spapr->ov5_cas = spapr_ovec_new();
2480
2481 if (smc->dr_lmb_enabled) {
2482 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2483 spapr_validate_node_memory(machine, &error_fatal);
2484 }
2485
2486 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2487 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2488
2489 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2490 }
2491
2492
2493
2494 if (spapr->use_hotplug_event_source) {
2495 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2496 }
2497
2498
2499 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2500 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2501 }
2502
2503
2504 spapr_init_cpus(spapr);
2505
2506 if (kvm_enabled()) {
2507
2508 kvmppc_enable_logical_ci_hcalls();
2509 kvmppc_enable_set_mode_hcall();
2510
2511
2512 kvmppc_enable_clear_ref_mod_hcalls();
2513 }
2514
2515
2516 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2517 machine->ram_size);
2518 memory_region_add_subregion(sysmem, 0, ram);
2519
2520 if (rma_alloc_size && rma) {
2521 rma_region = g_new(MemoryRegion, 1);
2522 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2523 rma_alloc_size, rma);
2524 vmstate_register_ram_global(rma_region);
2525 memory_region_add_subregion(sysmem, 0, rma_region);
2526 }
2527
2528
2529 if (machine->ram_size < machine->maxram_size) {
2530 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2531
2532
2533
2534
2535
2536 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2537 SPAPR_MAX_RAM_SLOTS;
2538
2539 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2540 max_memslots = SPAPR_MAX_RAM_SLOTS;
2541 }
2542 if (machine->ram_slots > max_memslots) {
2543 error_report("Specified number of memory slots %"
2544 PRIu64" exceeds max supported %d",
2545 machine->ram_slots, max_memslots);
2546 exit(1);
2547 }
2548
2549 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2550 SPAPR_HOTPLUG_MEM_ALIGN);
2551 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2552 "hotplug-memory", hotplug_mem_size);
2553 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2554 &spapr->hotplug_memory.mr);
2555 }
2556
2557 if (smc->dr_lmb_enabled) {
2558 spapr_create_lmb_dr_connectors(spapr);
2559 }
2560
2561 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2562 if (!filename) {
2563 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2564 exit(1);
2565 }
2566 spapr->rtas_size = get_image_size(filename);
2567 if (spapr->rtas_size < 0) {
2568 error_report("Could not get size of LPAR rtas '%s'", filename);
2569 exit(1);
2570 }
2571 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2572 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2573 error_report("Could not load LPAR rtas '%s'", filename);
2574 exit(1);
2575 }
2576 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2577 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2578 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2579 exit(1);
2580 }
2581 g_free(filename);
2582
2583
2584 spapr_events_init(spapr);
2585
2586
2587 spapr_rtc_create(spapr);
2588
2589
2590 spapr->vio_bus = spapr_vio_bus_init();
2591
2592 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2593 if (serial_hds[i]) {
2594 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2595 }
2596 }
2597
2598
2599 spapr_create_nvram(spapr);
2600
2601
2602 spapr_pci_rtas_init();
2603
2604 phb = spapr_create_phb(spapr, 0);
2605
2606 for (i = 0; i < nb_nics; i++) {
2607 NICInfo *nd = &nd_table[i];
2608
2609 if (!nd->model) {
2610 nd->model = g_strdup("spapr-vlan");
2611 }
2612
2613 if (g_str_equal(nd->model, "spapr-vlan") ||
2614 g_str_equal(nd->model, "ibmveth")) {
2615 spapr_vlan_create(spapr->vio_bus, nd);
2616 } else {
2617 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2618 }
2619 }
2620
2621 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2622 spapr_vscsi_create(spapr->vio_bus);
2623 }
2624
2625
2626 if (spapr_vga_init(phb->bus, &error_fatal)) {
2627 spapr->has_graphics = true;
2628 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2629 }
2630
2631 if (machine->usb) {
2632 if (smc->use_ohci_by_default) {
2633 pci_create_simple(phb->bus, -1, "pci-ohci");
2634 } else {
2635 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2636 }
2637
2638 if (spapr->has_graphics) {
2639 USBBus *usb_bus = usb_bus_find(-1);
2640
2641 usb_create_simple(usb_bus, "usb-kbd");
2642 usb_create_simple(usb_bus, "usb-mouse");
2643 }
2644 }
2645
2646 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2647 error_report(
2648 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2649 MIN_RMA_SLOF);
2650 exit(1);
2651 }
2652
2653 if (kernel_filename) {
2654 uint64_t lowaddr = 0;
2655
2656 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2657 NULL, NULL, &lowaddr, NULL, 1,
2658 PPC_ELF_MACHINE, 0, 0);
2659 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2660 spapr->kernel_size = load_elf(kernel_filename,
2661 translate_kernel_address, NULL, NULL,
2662 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2663 0, 0);
2664 spapr->kernel_le = spapr->kernel_size > 0;
2665 }
2666 if (spapr->kernel_size < 0) {
2667 error_report("error loading %s: %s", kernel_filename,
2668 load_elf_strerror(spapr->kernel_size));
2669 exit(1);
2670 }
2671
2672
2673 if (initrd_filename) {
2674
2675
2676
2677 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2678 + 0x1ffff) & ~0xffff;
2679 spapr->initrd_size = load_image_targphys(initrd_filename,
2680 spapr->initrd_base,
2681 load_limit
2682 - spapr->initrd_base);
2683 if (spapr->initrd_size < 0) {
2684 error_report("could not load initial ram disk '%s'",
2685 initrd_filename);
2686 exit(1);
2687 }
2688 }
2689 }
2690
2691 if (bios_name == NULL) {
2692 bios_name = FW_FILE_NAME;
2693 }
2694 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2695 if (!filename) {
2696 error_report("Could not find LPAR firmware '%s'", bios_name);
2697 exit(1);
2698 }
2699 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2700 if (fw_size <= 0) {
2701 error_report("Could not load LPAR firmware '%s'", filename);
2702 exit(1);
2703 }
2704 g_free(filename);
2705
2706
2707
2708
2709 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2710 register_savevm_live(NULL, "spapr/htab", -1, 1,
2711 &savevm_htab_handlers, spapr);
2712
2713 qemu_register_boot_set(spapr_boot_set, spapr);
2714
2715 if (kvm_enabled()) {
2716
2717 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2718 &spapr->tb);
2719
2720 kvmppc_spapr_enable_inkernel_multitce();
2721 }
2722}
2723
2724static int spapr_kvm_type(const char *vm_type)
2725{
2726 if (!vm_type) {
2727 return 0;
2728 }
2729
2730 if (!strcmp(vm_type, "HV")) {
2731 return 1;
2732 }
2733
2734 if (!strcmp(vm_type, "PR")) {
2735 return 2;
2736 }
2737
2738 error_report("Unknown kvm-type specified '%s'", vm_type);
2739 exit(1);
2740}
2741
2742
2743
2744
2745
2746static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2747 DeviceState *dev)
2748{
2749#define CAST(type, obj, name) \
2750 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2751 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2752 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2753 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2754
2755 if (d) {
2756 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2757 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2758 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2759
2760 if (spapr) {
2761
2762
2763
2764
2765
2766 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2767 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2768 (uint64_t)id << 48);
2769 } else if (virtio) {
2770
2771
2772
2773
2774
2775
2776
2777 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2778 if (d->lun >= 256) {
2779
2780 id |= 0x4000;
2781 }
2782 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2783 (uint64_t)id << 32);
2784 } else if (usb) {
2785
2786
2787
2788
2789 unsigned usb_port = atoi(usb->port->path);
2790 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2791 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2792 (uint64_t)id << 32);
2793 }
2794 }
2795
2796
2797
2798
2799
2800
2801
2802 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2803 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2804 if (usb_host_dev_is_scsi_storage(usbdev)) {
2805 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2806 }
2807 }
2808
2809 if (phb) {
2810
2811 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2812 }
2813
2814 if (vsc) {
2815
2816 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2817 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2818 }
2819
2820 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2821
2822 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2823 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2824 }
2825
2826 return NULL;
2827}
2828
2829static char *spapr_get_kvm_type(Object *obj, Error **errp)
2830{
2831 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2832
2833 return g_strdup(spapr->kvm_type);
2834}
2835
2836static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2837{
2838 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2839
2840 g_free(spapr->kvm_type);
2841 spapr->kvm_type = g_strdup(value);
2842}
2843
2844static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2845{
2846 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2847
2848 return spapr->use_hotplug_event_source;
2849}
2850
2851static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2852 Error **errp)
2853{
2854 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2855
2856 spapr->use_hotplug_event_source = value;
2857}
2858
2859static bool spapr_get_msix_emulation(Object *obj, Error **errp)
2860{
2861 return true;
2862}
2863
2864static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2865{
2866 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2867
2868 switch (spapr->resize_hpt) {
2869 case SPAPR_RESIZE_HPT_DEFAULT:
2870 return g_strdup("default");
2871 case SPAPR_RESIZE_HPT_DISABLED:
2872 return g_strdup("disabled");
2873 case SPAPR_RESIZE_HPT_ENABLED:
2874 return g_strdup("enabled");
2875 case SPAPR_RESIZE_HPT_REQUIRED:
2876 return g_strdup("required");
2877 }
2878 g_assert_not_reached();
2879}
2880
2881static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2882{
2883 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2884
2885 if (strcmp(value, "default") == 0) {
2886 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2887 } else if (strcmp(value, "disabled") == 0) {
2888 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2889 } else if (strcmp(value, "enabled") == 0) {
2890 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2891 } else if (strcmp(value, "required") == 0) {
2892 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2893 } else {
2894 error_setg(errp, "Bad value for \"resize-hpt\" property");
2895 }
2896}
2897
2898static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
2899 void *opaque, Error **errp)
2900{
2901 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2902}
2903
2904static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
2905 void *opaque, Error **errp)
2906{
2907 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2908}
2909
2910static void spapr_instance_init(Object *obj)
2911{
2912 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2913
2914 spapr->htab_fd = -1;
2915 spapr->use_hotplug_event_source = true;
2916 object_property_add_str(obj, "kvm-type",
2917 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2918 object_property_set_description(obj, "kvm-type",
2919 "Specifies the KVM virtualization mode (HV, PR)",
2920 NULL);
2921 object_property_add_bool(obj, "modern-hotplug-events",
2922 spapr_get_modern_hotplug_events,
2923 spapr_set_modern_hotplug_events,
2924 NULL);
2925 object_property_set_description(obj, "modern-hotplug-events",
2926 "Use dedicated hotplug event mechanism in"
2927 " place of standard EPOW events when possible"
2928 " (required for memory hot-unplug support)",
2929 NULL);
2930
2931 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2932 "Maximum permitted CPU compatibility mode",
2933 &error_fatal);
2934
2935 object_property_add_str(obj, "resize-hpt",
2936 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2937 object_property_set_description(obj, "resize-hpt",
2938 "Resizing of the Hash Page Table (enabled, disabled, required)",
2939 NULL);
2940 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
2941 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
2942 object_property_set_description(obj, "vsmt",
2943 "Virtual SMT: KVM behaves as if this were"
2944 " the host's SMT mode", &error_abort);
2945 object_property_add_bool(obj, "vfio-no-msix-emulation",
2946 spapr_get_msix_emulation, NULL, NULL);
2947}
2948
2949static void spapr_machine_finalizefn(Object *obj)
2950{
2951 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2952
2953 g_free(spapr->kvm_type);
2954}
2955
2956void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2957{
2958 cpu_synchronize_state(cs);
2959 ppc_cpu_do_system_reset(cs);
2960}
2961
2962static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2963{
2964 CPUState *cs;
2965
2966 CPU_FOREACH(cs) {
2967 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2968 }
2969}
2970
2971static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2972 uint32_t node, bool dedicated_hp_event_source,
2973 Error **errp)
2974{
2975 sPAPRDRConnector *drc;
2976 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2977 int i, fdt_offset, fdt_size;
2978 void *fdt;
2979 uint64_t addr = addr_start;
2980 bool hotplugged = spapr_drc_hotplugged(dev);
2981 Error *local_err = NULL;
2982
2983 for (i = 0; i < nr_lmbs; i++) {
2984 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2985 addr / SPAPR_MEMORY_BLOCK_SIZE);
2986 g_assert(drc);
2987
2988 fdt = create_device_tree(&fdt_size);
2989 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2990 SPAPR_MEMORY_BLOCK_SIZE);
2991
2992 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2993 if (local_err) {
2994 while (addr > addr_start) {
2995 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2996 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2997 addr / SPAPR_MEMORY_BLOCK_SIZE);
2998 spapr_drc_detach(drc);
2999 }
3000 g_free(fdt);
3001 error_propagate(errp, local_err);
3002 return;
3003 }
3004 if (!hotplugged) {
3005 spapr_drc_reset(drc);
3006 }
3007 addr += SPAPR_MEMORY_BLOCK_SIZE;
3008 }
3009
3010
3011
3012 if (hotplugged) {
3013 if (dedicated_hp_event_source) {
3014 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3015 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3016 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3017 nr_lmbs,
3018 spapr_drc_index(drc));
3019 } else {
3020 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3021 nr_lmbs);
3022 }
3023 }
3024}
3025
3026static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3027 uint32_t node, Error **errp)
3028{
3029 Error *local_err = NULL;
3030 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3031 PCDIMMDevice *dimm = PC_DIMM(dev);
3032 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3033 MemoryRegion *mr;
3034 uint64_t align, size, addr;
3035
3036 mr = ddc->get_memory_region(dimm, &local_err);
3037 if (local_err) {
3038 goto out;
3039 }
3040 align = memory_region_get_alignment(mr);
3041 size = memory_region_size(mr);
3042
3043 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
3044 if (local_err) {
3045 goto out;
3046 }
3047
3048 addr = object_property_get_uint(OBJECT(dimm),
3049 PC_DIMM_ADDR_PROP, &local_err);
3050 if (local_err) {
3051 goto out_unplug;
3052 }
3053
3054 spapr_add_lmbs(dev, addr, size, node,
3055 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3056 &local_err);
3057 if (local_err) {
3058 goto out_unplug;
3059 }
3060
3061 return;
3062
3063out_unplug:
3064 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
3065out:
3066 error_propagate(errp, local_err);
3067}
3068
3069static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3070 Error **errp)
3071{
3072 PCDIMMDevice *dimm = PC_DIMM(dev);
3073 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3074 MemoryRegion *mr;
3075 uint64_t size;
3076 char *mem_dev;
3077
3078 mr = ddc->get_memory_region(dimm, errp);
3079 if (!mr) {
3080 return;
3081 }
3082 size = memory_region_size(mr);
3083
3084 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3085 error_setg(errp, "Hotplugged memory size must be a multiple of "
3086 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
3087 return;
3088 }
3089
3090 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
3091 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
3092 error_setg(errp, "Memory backend has bad page size. "
3093 "Use 'memory-backend-file' with correct mem-path.");
3094 goto out;
3095 }
3096
3097out:
3098 g_free(mem_dev);
3099}
3100
3101struct sPAPRDIMMState {
3102 PCDIMMDevice *dimm;
3103 uint32_t nr_lmbs;
3104 QTAILQ_ENTRY(sPAPRDIMMState) next;
3105};
3106
3107static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
3108 PCDIMMDevice *dimm)
3109{
3110 sPAPRDIMMState *dimm_state = NULL;
3111
3112 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3113 if (dimm_state->dimm == dimm) {
3114 break;
3115 }
3116 }
3117 return dimm_state;
3118}
3119
3120static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3121 uint32_t nr_lmbs,
3122 PCDIMMDevice *dimm)
3123{
3124 sPAPRDIMMState *ds = NULL;
3125
3126
3127
3128
3129
3130
3131
3132 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3133 if (!ds) {
3134 ds = g_malloc0(sizeof(sPAPRDIMMState));
3135 ds->nr_lmbs = nr_lmbs;
3136 ds->dimm = dimm;
3137 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3138 }
3139 return ds;
3140}
3141
3142static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3143 sPAPRDIMMState *dimm_state)
3144{
3145 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3146 g_free(dimm_state);
3147}
3148
3149static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3150 PCDIMMDevice *dimm)
3151{
3152 sPAPRDRConnector *drc;
3153 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3154 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3155 uint64_t size = memory_region_size(mr);
3156 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3157 uint32_t avail_lmbs = 0;
3158 uint64_t addr_start, addr;
3159 int i;
3160
3161 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3162 &error_abort);
3163
3164 addr = addr_start;
3165 for (i = 0; i < nr_lmbs; i++) {
3166 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3167 addr / SPAPR_MEMORY_BLOCK_SIZE);
3168 g_assert(drc);
3169 if (drc->dev) {
3170 avail_lmbs++;
3171 }
3172 addr += SPAPR_MEMORY_BLOCK_SIZE;
3173 }
3174
3175 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3176}
3177
3178
3179void spapr_lmb_release(DeviceState *dev)
3180{
3181 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
3182 PCDIMMDevice *dimm = PC_DIMM(dev);
3183 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3184 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3185 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3186
3187
3188
3189 if (ds == NULL) {
3190 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3191 g_assert(ds);
3192
3193 g_assert(ds->nr_lmbs);
3194 }
3195
3196 if (--ds->nr_lmbs) {
3197 return;
3198 }
3199
3200
3201
3202
3203
3204 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
3205 object_unparent(OBJECT(dev));
3206 spapr_pending_dimm_unplugs_remove(spapr, ds);
3207}
3208
3209static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3210 DeviceState *dev, Error **errp)
3211{
3212 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3213 Error *local_err = NULL;
3214 PCDIMMDevice *dimm = PC_DIMM(dev);
3215 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3216 MemoryRegion *mr;
3217 uint32_t nr_lmbs;
3218 uint64_t size, addr_start, addr;
3219 int i;
3220 sPAPRDRConnector *drc;
3221
3222 mr = ddc->get_memory_region(dimm, &local_err);
3223 if (local_err) {
3224 goto out;
3225 }
3226 size = memory_region_size(mr);
3227 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3228
3229 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3230 &local_err);
3231 if (local_err) {
3232 goto out;
3233 }
3234
3235
3236
3237
3238
3239
3240
3241 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3242 error_setg(&local_err,
3243 "Memory unplug already in progress for device %s",
3244 dev->id);
3245 goto out;
3246 }
3247
3248 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3249
3250 addr = addr_start;
3251 for (i = 0; i < nr_lmbs; i++) {
3252 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3253 addr / SPAPR_MEMORY_BLOCK_SIZE);
3254 g_assert(drc);
3255
3256 spapr_drc_detach(drc);
3257 addr += SPAPR_MEMORY_BLOCK_SIZE;
3258 }
3259
3260 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3261 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3262 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3263 nr_lmbs, spapr_drc_index(drc));
3264out:
3265 error_propagate(errp, local_err);
3266}
3267
3268static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3269 sPAPRMachineState *spapr)
3270{
3271 PowerPCCPU *cpu = POWERPC_CPU(cs);
3272 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3273 int id = spapr_get_vcpu_id(cpu);
3274 void *fdt;
3275 int offset, fdt_size;
3276 char *nodename;
3277
3278 fdt = create_device_tree(&fdt_size);
3279 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3280 offset = fdt_add_subnode(fdt, 0, nodename);
3281
3282 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3283 g_free(nodename);
3284
3285 *fdt_offset = offset;
3286 return fdt;
3287}
3288
3289
3290void spapr_core_release(DeviceState *dev)
3291{
3292 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3293 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3294 CPUCore *cc = CPU_CORE(dev);
3295 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3296
3297 if (smc->pre_2_10_has_unused_icps) {
3298 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3299 int i;
3300
3301 for (i = 0; i < cc->nr_threads; i++) {
3302 CPUState *cs = CPU(sc->threads[i]);
3303
3304 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3305 }
3306 }
3307
3308 assert(core_slot);
3309 core_slot->cpu = NULL;
3310 object_unparent(OBJECT(dev));
3311}
3312
3313static
3314void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3315 Error **errp)
3316{
3317 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3318 int index;
3319 sPAPRDRConnector *drc;
3320 CPUCore *cc = CPU_CORE(dev);
3321
3322 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3323 error_setg(errp, "Unable to find CPU core with core-id: %d",
3324 cc->core_id);
3325 return;
3326 }
3327 if (index == 0) {
3328 error_setg(errp, "Boot CPU core may not be unplugged");
3329 return;
3330 }
3331
3332 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3333 spapr_vcpu_id(spapr, cc->core_id));
3334 g_assert(drc);
3335
3336 spapr_drc_detach(drc);
3337
3338 spapr_hotplug_req_remove_by_index(drc);
3339}
3340
3341static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3342 Error **errp)
3343{
3344 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3345 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3346 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3347 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3348 CPUCore *cc = CPU_CORE(dev);
3349 CPUState *cs = CPU(core->threads[0]);
3350 sPAPRDRConnector *drc;
3351 Error *local_err = NULL;
3352 CPUArchId *core_slot;
3353 int index;
3354 bool hotplugged = spapr_drc_hotplugged(dev);
3355
3356 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3357 if (!core_slot) {
3358 error_setg(errp, "Unable to find CPU core with core-id: %d",
3359 cc->core_id);
3360 return;
3361 }
3362 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3363 spapr_vcpu_id(spapr, cc->core_id));
3364
3365 g_assert(drc || !mc->has_hotpluggable_cpus);
3366
3367 if (drc) {
3368 void *fdt;
3369 int fdt_offset;
3370
3371 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3372
3373 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3374 if (local_err) {
3375 g_free(fdt);
3376 error_propagate(errp, local_err);
3377 return;
3378 }
3379
3380 if (hotplugged) {
3381
3382
3383
3384
3385 spapr_hotplug_req_add_by_index(drc);
3386 } else {
3387 spapr_drc_reset(drc);
3388 }
3389 }
3390
3391 core_slot->cpu = OBJECT(dev);
3392
3393 if (smc->pre_2_10_has_unused_icps) {
3394 int i;
3395
3396 for (i = 0; i < cc->nr_threads; i++) {
3397 cs = CPU(core->threads[i]);
3398 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3399 }
3400 }
3401}
3402
3403static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3404 Error **errp)
3405{
3406 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3407 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3408 Error *local_err = NULL;
3409 CPUCore *cc = CPU_CORE(dev);
3410 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3411 const char *type = object_get_typename(OBJECT(dev));
3412 CPUArchId *core_slot;
3413 int index;
3414
3415 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3416 error_setg(&local_err, "CPU hotplug not supported for this machine");
3417 goto out;
3418 }
3419
3420 if (strcmp(base_core_type, type)) {
3421 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3422 goto out;
3423 }
3424
3425 if (cc->core_id % smp_threads) {
3426 error_setg(&local_err, "invalid core id %d", cc->core_id);
3427 goto out;
3428 }
3429
3430
3431
3432
3433
3434
3435
3436 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3437 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3438 cc->nr_threads, smp_threads);
3439 goto out;
3440 }
3441
3442 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3443 if (!core_slot) {
3444 error_setg(&local_err, "core id %d out of range", cc->core_id);
3445 goto out;
3446 }
3447
3448 if (core_slot->cpu) {
3449 error_setg(&local_err, "core %d already populated", cc->core_id);
3450 goto out;
3451 }
3452
3453 numa_cpu_pre_plug(core_slot, dev, &local_err);
3454
3455out:
3456 error_propagate(errp, local_err);
3457}
3458
3459static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3460 DeviceState *dev, Error **errp)
3461{
3462 MachineState *ms = MACHINE(hotplug_dev);
3463 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3464
3465 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3466 int node;
3467
3468 if (!smc->dr_lmb_enabled) {
3469 error_setg(errp, "Memory hotplug not supported for this machine");
3470 return;
3471 }
3472 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3473 if (*errp) {
3474 return;
3475 }
3476 if (node < 0 || node >= MAX_NODES) {
3477 error_setg(errp, "Invaild node %d", node);
3478 return;
3479 }
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497 if (nb_numa_nodes && !numa_info[node].node_mem) {
3498 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3499 node);
3500 return;
3501 }
3502
3503 spapr_memory_plug(hotplug_dev, dev, node, errp);
3504 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3505 spapr_core_plug(hotplug_dev, dev, errp);
3506 }
3507}
3508
3509static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3510 DeviceState *dev, Error **errp)
3511{
3512 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3513 MachineClass *mc = MACHINE_GET_CLASS(sms);
3514
3515 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3516 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3517 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3518 } else {
3519
3520
3521
3522
3523
3524
3525 error_setg(errp, "Memory hot unplug not supported for this guest");
3526 }
3527 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3528 if (!mc->has_hotpluggable_cpus) {
3529 error_setg(errp, "CPU hot unplug not supported on this machine");
3530 return;
3531 }
3532 spapr_core_unplug_request(hotplug_dev, dev, errp);
3533 }
3534}
3535
3536static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3537 DeviceState *dev, Error **errp)
3538{
3539 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3540 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3541 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3542 spapr_core_pre_plug(hotplug_dev, dev, errp);
3543 }
3544}
3545
3546static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3547 DeviceState *dev)
3548{
3549 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3550 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3551 return HOTPLUG_HANDLER(machine);
3552 }
3553 return NULL;
3554}
3555
3556static CpuInstanceProperties
3557spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3558{
3559 CPUArchId *core_slot;
3560 MachineClass *mc = MACHINE_GET_CLASS(machine);
3561
3562
3563 mc->possible_cpu_arch_ids(machine);
3564
3565 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3566 assert(core_slot);
3567 return core_slot->props;
3568}
3569
3570static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3571{
3572 return idx / smp_cores % nb_numa_nodes;
3573}
3574
3575static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3576{
3577 int i;
3578 const char *core_type;
3579 int spapr_max_cores = max_cpus / smp_threads;
3580 MachineClass *mc = MACHINE_GET_CLASS(machine);
3581
3582 if (!mc->has_hotpluggable_cpus) {
3583 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3584 }
3585 if (machine->possible_cpus) {
3586 assert(machine->possible_cpus->len == spapr_max_cores);
3587 return machine->possible_cpus;
3588 }
3589
3590 core_type = spapr_get_cpu_core_type(machine->cpu_type);
3591 if (!core_type) {
3592 error_report("Unable to find sPAPR CPU Core definition");
3593 exit(1);
3594 }
3595
3596 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3597 sizeof(CPUArchId) * spapr_max_cores);
3598 machine->possible_cpus->len = spapr_max_cores;
3599 for (i = 0; i < machine->possible_cpus->len; i++) {
3600 int core_id = i * smp_threads;
3601
3602 machine->possible_cpus->cpus[i].type = core_type;
3603 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3604 machine->possible_cpus->cpus[i].arch_id = core_id;
3605 machine->possible_cpus->cpus[i].props.has_core_id = true;
3606 machine->possible_cpus->cpus[i].props.core_id = core_id;
3607 }
3608 return machine->possible_cpus;
3609}
3610
3611static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3612 uint64_t *buid, hwaddr *pio,
3613 hwaddr *mmio32, hwaddr *mmio64,
3614 unsigned n_dma, uint32_t *liobns, Error **errp)
3615{
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631 const uint64_t base_buid = 0x800000020000000ULL;
3632#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3633 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3634 int i;
3635
3636
3637 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3638 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3639 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3640 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3641
3642 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3643 SPAPR_PCI_MEM32_WIN_SIZE);
3644 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3645 SPAPR_PCI_MEM64_WIN_SIZE);
3646
3647 if (index >= SPAPR_MAX_PHBS) {
3648 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3649 SPAPR_MAX_PHBS - 1);
3650 return;
3651 }
3652
3653 *buid = base_buid + index;
3654 for (i = 0; i < n_dma; ++i) {
3655 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3656 }
3657
3658 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3659 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3660 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3661}
3662
3663static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3664{
3665 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3666
3667 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3668}
3669
3670static void spapr_ics_resend(XICSFabric *dev)
3671{
3672 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3673
3674 ics_resend(spapr->ics);
3675}
3676
3677static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3678{
3679 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3680
3681 return cpu ? ICP(cpu->intc) : NULL;
3682}
3683
3684#define ICS_IRQ_FREE(ics, srcno) \
3685 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3686
3687static int ics_find_free_block(ICSState *ics, int num, int alignnum)
3688{
3689 int first, i;
3690
3691 for (first = 0; first < ics->nr_irqs; first += alignnum) {
3692 if (num > (ics->nr_irqs - first)) {
3693 return -1;
3694 }
3695 for (i = first; i < first + num; ++i) {
3696 if (!ICS_IRQ_FREE(ics, i)) {
3697 break;
3698 }
3699 }
3700 if (i == (first + num)) {
3701 return first;
3702 }
3703 }
3704
3705 return -1;
3706}
3707
3708
3709
3710
3711static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi)
3712{
3713 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi);
3714}
3715
3716int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
3717 Error **errp)
3718{
3719 ICSState *ics = spapr->ics;
3720 int irq;
3721
3722 if (!ics) {
3723 return -1;
3724 }
3725 if (irq_hint) {
3726 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
3727 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
3728 return -1;
3729 }
3730 irq = irq_hint;
3731 } else {
3732 irq = ics_find_free_block(ics, 1, 1);
3733 if (irq < 0) {
3734 error_setg(errp, "can't allocate IRQ: no IRQ left");
3735 return -1;
3736 }
3737 irq += ics->offset;
3738 }
3739
3740 spapr_irq_set_lsi(spapr, irq, lsi);
3741 trace_spapr_irq_alloc(irq);
3742
3743 return irq;
3744}
3745
3746
3747
3748
3749
3750int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
3751 bool align, Error **errp)
3752{
3753 ICSState *ics = spapr->ics;
3754 int i, first = -1;
3755
3756 if (!ics) {
3757 return -1;
3758 }
3759
3760
3761
3762
3763
3764
3765
3766
3767 if (align) {
3768 assert((num == 1) || (num == 2) || (num == 4) ||
3769 (num == 8) || (num == 16) || (num == 32));
3770 first = ics_find_free_block(ics, num, num);
3771 } else {
3772 first = ics_find_free_block(ics, num, 1);
3773 }
3774 if (first < 0) {
3775 error_setg(errp, "can't find a free %d-IRQ block", num);
3776 return -1;
3777 }
3778
3779 first += ics->offset;
3780 for (i = first; i < first + num; ++i) {
3781 spapr_irq_set_lsi(spapr, i, lsi);
3782 }
3783
3784 trace_spapr_irq_alloc_block(first, num, lsi, align);
3785
3786 return first;
3787}
3788
3789void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
3790{
3791 ICSState *ics = spapr->ics;
3792 int srcno = irq - ics->offset;
3793 int i;
3794
3795 if (ics_valid_irq(ics, irq)) {
3796 trace_spapr_irq_free(0, irq, num);
3797 for (i = srcno; i < srcno + num; ++i) {
3798 if (ICS_IRQ_FREE(ics, i)) {
3799 trace_spapr_irq_free_warn(0, i + ics->offset);
3800 }
3801 memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
3802 }
3803 }
3804}
3805
3806qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
3807{
3808 ICSState *ics = spapr->ics;
3809
3810 if (ics_valid_irq(ics, irq)) {
3811 return ics->qirqs[irq - ics->offset];
3812 }
3813
3814 return NULL;
3815}
3816
3817static void spapr_pic_print_info(InterruptStatsProvider *obj,
3818 Monitor *mon)
3819{
3820 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3821 CPUState *cs;
3822
3823 CPU_FOREACH(cs) {
3824 PowerPCCPU *cpu = POWERPC_CPU(cs);
3825
3826 icp_pic_print_info(ICP(cpu->intc), mon);
3827 }
3828
3829 ics_pic_print_info(spapr->ics, mon);
3830}
3831
3832int spapr_get_vcpu_id(PowerPCCPU *cpu)
3833{
3834 return cpu->vcpu_id;
3835}
3836
3837void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
3838{
3839 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3840 int vcpu_id;
3841
3842 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
3843
3844 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
3845 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
3846 error_append_hint(errp, "Adjust the number of cpus to %d "
3847 "or try to raise the number of threads per core\n",
3848 vcpu_id * smp_threads / spapr->vsmt);
3849 return;
3850 }
3851
3852 cpu->vcpu_id = vcpu_id;
3853}
3854
3855PowerPCCPU *spapr_find_cpu(int vcpu_id)
3856{
3857 CPUState *cs;
3858
3859 CPU_FOREACH(cs) {
3860 PowerPCCPU *cpu = POWERPC_CPU(cs);
3861
3862 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
3863 return cpu;
3864 }
3865 }
3866
3867 return NULL;
3868}
3869
3870static void spapr_machine_class_init(ObjectClass *oc, void *data)
3871{
3872 MachineClass *mc = MACHINE_CLASS(oc);
3873 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3874 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3875 NMIClass *nc = NMI_CLASS(oc);
3876 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3877 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3878 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3879 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3880
3881 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3882
3883
3884
3885
3886
3887
3888 mc->init = spapr_machine_init;
3889 mc->reset = spapr_machine_reset;
3890 mc->block_default_type = IF_SCSI;
3891 mc->max_cpus = 1024;
3892 mc->no_parallel = 1;
3893 mc->default_boot_order = "";
3894 mc->default_ram_size = 512 * M_BYTE;
3895 mc->kvm_type = spapr_kvm_type;
3896 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
3897 mc->pci_allow_0_address = true;
3898 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3899 hc->pre_plug = spapr_machine_device_pre_plug;
3900 hc->plug = spapr_machine_device_plug;
3901 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3902 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3903 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3904 hc->unplug_request = spapr_machine_device_unplug_request;
3905
3906 smc->dr_lmb_enabled = true;
3907 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3908 mc->has_hotpluggable_cpus = true;
3909 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3910 fwc->get_dev_path = spapr_get_fw_dev_path;
3911 nc->nmi_monitor_handler = spapr_nmi;
3912 smc->phb_placement = spapr_phb_placement;
3913 vhc->hypercall = emulate_spapr_hypercall;
3914 vhc->hpt_mask = spapr_hpt_mask;
3915 vhc->map_hptes = spapr_map_hptes;
3916 vhc->unmap_hptes = spapr_unmap_hptes;
3917 vhc->store_hpte = spapr_store_hpte;
3918 vhc->get_patbe = spapr_get_patbe;
3919 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3920 xic->ics_get = spapr_ics_get;
3921 xic->ics_resend = spapr_ics_resend;
3922 xic->icp_get = spapr_icp_get;
3923 ispc->print_info = spapr_pic_print_info;
3924
3925
3926
3927
3928 mc->numa_mem_align_shift = 28;
3929
3930 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
3931 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
3932 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
3933 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
3934 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
3935 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
3936 spapr_caps_add_properties(smc, &error_abort);
3937}
3938
3939static const TypeInfo spapr_machine_info = {
3940 .name = TYPE_SPAPR_MACHINE,
3941 .parent = TYPE_MACHINE,
3942 .abstract = true,
3943 .instance_size = sizeof(sPAPRMachineState),
3944 .instance_init = spapr_instance_init,
3945 .instance_finalize = spapr_machine_finalizefn,
3946 .class_size = sizeof(sPAPRMachineClass),
3947 .class_init = spapr_machine_class_init,
3948 .interfaces = (InterfaceInfo[]) {
3949 { TYPE_FW_PATH_PROVIDER },
3950 { TYPE_NMI },
3951 { TYPE_HOTPLUG_HANDLER },
3952 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3953 { TYPE_XICS_FABRIC },
3954 { TYPE_INTERRUPT_STATS_PROVIDER },
3955 { }
3956 },
3957};
3958
3959#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3960 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3961 void *data) \
3962 { \
3963 MachineClass *mc = MACHINE_CLASS(oc); \
3964 spapr_machine_##suffix##_class_options(mc); \
3965 if (latest) { \
3966 mc->alias = "pseries"; \
3967 mc->is_default = 1; \
3968 } \
3969 } \
3970 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3971 { \
3972 MachineState *machine = MACHINE(obj); \
3973 spapr_machine_##suffix##_instance_options(machine); \
3974 } \
3975 static const TypeInfo spapr_machine_##suffix##_info = { \
3976 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3977 .parent = TYPE_SPAPR_MACHINE, \
3978 .class_init = spapr_machine_##suffix##_class_init, \
3979 .instance_init = spapr_machine_##suffix##_instance_init, \
3980 }; \
3981 static void spapr_machine_register_##suffix(void) \
3982 { \
3983 type_register(&spapr_machine_##suffix##_info); \
3984 } \
3985 type_init(spapr_machine_register_##suffix)
3986
3987
3988
3989
3990static void spapr_machine_2_12_instance_options(MachineState *machine)
3991{
3992}
3993
3994static void spapr_machine_2_12_class_options(MachineClass *mc)
3995{
3996
3997}
3998
3999DEFINE_SPAPR_MACHINE(2_12, "2.12", true);
4000
4001static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine)
4002{
4003 spapr_machine_2_12_instance_options(machine);
4004}
4005
4006static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4007{
4008 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4009
4010 spapr_machine_2_12_class_options(mc);
4011 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4012 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4013 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4014}
4015
4016DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4017
4018
4019
4020
4021#define SPAPR_COMPAT_2_11 \
4022 HW_COMPAT_2_11
4023
4024static void spapr_machine_2_11_instance_options(MachineState *machine)
4025{
4026 spapr_machine_2_12_instance_options(machine);
4027}
4028
4029static void spapr_machine_2_11_class_options(MachineClass *mc)
4030{
4031 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4032
4033 spapr_machine_2_12_class_options(mc);
4034 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4035 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
4036}
4037
4038DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4039
4040
4041
4042
4043#define SPAPR_COMPAT_2_10 \
4044 HW_COMPAT_2_10
4045
4046static void spapr_machine_2_10_instance_options(MachineState *machine)
4047{
4048 spapr_machine_2_11_instance_options(machine);
4049}
4050
4051static void spapr_machine_2_10_class_options(MachineClass *mc)
4052{
4053 spapr_machine_2_11_class_options(mc);
4054 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
4055}
4056
4057DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4058
4059
4060
4061
4062#define SPAPR_COMPAT_2_9 \
4063 HW_COMPAT_2_9 \
4064 { \
4065 .driver = TYPE_POWERPC_CPU, \
4066 .property = "pre-2.10-migration", \
4067 .value = "on", \
4068 }, \
4069
4070static void spapr_machine_2_9_instance_options(MachineState *machine)
4071{
4072 spapr_machine_2_10_instance_options(machine);
4073}
4074
4075static void spapr_machine_2_9_class_options(MachineClass *mc)
4076{
4077 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4078
4079 spapr_machine_2_10_class_options(mc);
4080 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
4081 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4082 smc->pre_2_10_has_unused_icps = true;
4083 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4084}
4085
4086DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4087
4088
4089
4090
4091#define SPAPR_COMPAT_2_8 \
4092 HW_COMPAT_2_8 \
4093 { \
4094 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4095 .property = "pcie-extended-configuration-space", \
4096 .value = "off", \
4097 },
4098
4099static void spapr_machine_2_8_instance_options(MachineState *machine)
4100{
4101 spapr_machine_2_9_instance_options(machine);
4102}
4103
4104static void spapr_machine_2_8_class_options(MachineClass *mc)
4105{
4106 spapr_machine_2_9_class_options(mc);
4107 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
4108 mc->numa_mem_align_shift = 23;
4109}
4110
4111DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4112
4113
4114
4115
4116#define SPAPR_COMPAT_2_7 \
4117 HW_COMPAT_2_7 \
4118 { \
4119 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4120 .property = "mem_win_size", \
4121 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4122 }, \
4123 { \
4124 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4125 .property = "mem64_win_size", \
4126 .value = "0", \
4127 }, \
4128 { \
4129 .driver = TYPE_POWERPC_CPU, \
4130 .property = "pre-2.8-migration", \
4131 .value = "on", \
4132 }, \
4133 { \
4134 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4135 .property = "pre-2.8-migration", \
4136 .value = "on", \
4137 },
4138
4139static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
4140 uint64_t *buid, hwaddr *pio,
4141 hwaddr *mmio32, hwaddr *mmio64,
4142 unsigned n_dma, uint32_t *liobns, Error **errp)
4143{
4144
4145 const uint64_t base_buid = 0x800000020000000ULL;
4146 const hwaddr phb_spacing = 0x1000000000ULL;
4147 const hwaddr mmio_offset = 0xa0000000;
4148 const hwaddr pio_offset = 0x80000000;
4149 const uint32_t max_index = 255;
4150 const hwaddr phb0_alignment = 0x10000000000ULL;
4151
4152 uint64_t ram_top = MACHINE(spapr)->ram_size;
4153 hwaddr phb0_base, phb_base;
4154 int i;
4155
4156
4157 if (MACHINE(spapr)->maxram_size > ram_top) {
4158
4159
4160
4161 ram_top = spapr->hotplug_memory.base +
4162 memory_region_size(&spapr->hotplug_memory.mr);
4163 }
4164
4165 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4166
4167 if (index > max_index) {
4168 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4169 max_index);
4170 return;
4171 }
4172
4173 *buid = base_buid + index;
4174 for (i = 0; i < n_dma; ++i) {
4175 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4176 }
4177
4178 phb_base = phb0_base + index * phb_spacing;
4179 *pio = phb_base + pio_offset;
4180 *mmio32 = phb_base + mmio_offset;
4181
4182
4183
4184
4185
4186}
4187
4188static void spapr_machine_2_7_instance_options(MachineState *machine)
4189{
4190 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
4191
4192 spapr_machine_2_8_instance_options(machine);
4193 spapr->use_hotplug_event_source = false;
4194}
4195
4196static void spapr_machine_2_7_class_options(MachineClass *mc)
4197{
4198 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4199
4200 spapr_machine_2_8_class_options(mc);
4201 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4202 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
4203 smc->phb_placement = phb_placement_2_7;
4204}
4205
4206DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4207
4208
4209
4210
4211#define SPAPR_COMPAT_2_6 \
4212 HW_COMPAT_2_6 \
4213 { \
4214 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4215 .property = "ddw",\
4216 .value = stringify(off),\
4217 },
4218
4219static void spapr_machine_2_6_instance_options(MachineState *machine)
4220{
4221 spapr_machine_2_7_instance_options(machine);
4222}
4223
4224static void spapr_machine_2_6_class_options(MachineClass *mc)
4225{
4226 spapr_machine_2_7_class_options(mc);
4227 mc->has_hotpluggable_cpus = false;
4228 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4229}
4230
4231DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4232
4233
4234
4235
4236#define SPAPR_COMPAT_2_5 \
4237 HW_COMPAT_2_5 \
4238 { \
4239 .driver = "spapr-vlan", \
4240 .property = "use-rx-buffer-pools", \
4241 .value = "off", \
4242 },
4243
4244static void spapr_machine_2_5_instance_options(MachineState *machine)
4245{
4246 spapr_machine_2_6_instance_options(machine);
4247}
4248
4249static void spapr_machine_2_5_class_options(MachineClass *mc)
4250{
4251 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4252
4253 spapr_machine_2_6_class_options(mc);
4254 smc->use_ohci_by_default = true;
4255 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
4256}
4257
4258DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4259
4260
4261
4262
4263#define SPAPR_COMPAT_2_4 \
4264 HW_COMPAT_2_4
4265
4266static void spapr_machine_2_4_instance_options(MachineState *machine)
4267{
4268 spapr_machine_2_5_instance_options(machine);
4269}
4270
4271static void spapr_machine_2_4_class_options(MachineClass *mc)
4272{
4273 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4274
4275 spapr_machine_2_5_class_options(mc);
4276 smc->dr_lmb_enabled = false;
4277 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
4278}
4279
4280DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4281
4282
4283
4284
4285#define SPAPR_COMPAT_2_3 \
4286 HW_COMPAT_2_3 \
4287 {\
4288 .driver = "spapr-pci-host-bridge",\
4289 .property = "dynamic-reconfiguration",\
4290 .value = "off",\
4291 },
4292
4293static void spapr_machine_2_3_instance_options(MachineState *machine)
4294{
4295 spapr_machine_2_4_instance_options(machine);
4296}
4297
4298static void spapr_machine_2_3_class_options(MachineClass *mc)
4299{
4300 spapr_machine_2_4_class_options(mc);
4301 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
4302}
4303DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4304
4305
4306
4307
4308
4309#define SPAPR_COMPAT_2_2 \
4310 HW_COMPAT_2_2 \
4311 {\
4312 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4313 .property = "mem_win_size",\
4314 .value = "0x20000000",\
4315 },
4316
4317static void spapr_machine_2_2_instance_options(MachineState *machine)
4318{
4319 spapr_machine_2_3_instance_options(machine);
4320 machine->suppress_vmdesc = true;
4321}
4322
4323static void spapr_machine_2_2_class_options(MachineClass *mc)
4324{
4325 spapr_machine_2_3_class_options(mc);
4326 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4327}
4328DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4329
4330
4331
4332
4333#define SPAPR_COMPAT_2_1 \
4334 HW_COMPAT_2_1
4335
4336static void spapr_machine_2_1_instance_options(MachineState *machine)
4337{
4338 spapr_machine_2_2_instance_options(machine);
4339}
4340
4341static void spapr_machine_2_1_class_options(MachineClass *mc)
4342{
4343 spapr_machine_2_2_class_options(mc);
4344 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4345}
4346DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4347
4348static void spapr_machine_register_types(void)
4349{
4350 type_register_static(&spapr_machine_info);
4351}
4352
4353type_init(spapr_machine_register_types)
4354