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19#include "qemu/osdep.h"
20#include "qemu/error-report.h"
21#include "hw/hw.h"
22#include "qemu/log.h"
23#include "sysemu/kvm.h"
24#include "hw/qdev.h"
25#include "kvm_ppc.h"
26#include "sysemu/dma.h"
27#include "exec/address-spaces.h"
28#include "trace.h"
29
30#include "hw/ppc/spapr.h"
31#include "hw/ppc/spapr_vio.h"
32
33#include <libfdt.h>
34
35enum sPAPRTCEAccess {
36 SPAPR_TCE_FAULT = 0,
37 SPAPR_TCE_RO = 1,
38 SPAPR_TCE_WO = 2,
39 SPAPR_TCE_RW = 3,
40};
41
42#define IOMMU_PAGE_SIZE(shift) (1ULL << (shift))
43#define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1))
44
45static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
46
47sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
48{
49 sPAPRTCETable *tcet;
50
51 if (liobn & 0xFFFFFFFF00000000ULL) {
52 hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
53 liobn);
54 return NULL;
55 }
56
57 QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
58 if (tcet->liobn == (uint32_t)liobn) {
59 return tcet;
60 }
61 }
62
63 return NULL;
64}
65
66static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
67{
68 switch (tce & SPAPR_TCE_RW) {
69 case SPAPR_TCE_FAULT:
70 return IOMMU_NONE;
71 case SPAPR_TCE_RO:
72 return IOMMU_RO;
73 case SPAPR_TCE_WO:
74 return IOMMU_WO;
75 default:
76 return IOMMU_RW;
77 }
78}
79
80static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
81 uint32_t page_shift,
82 uint64_t bus_offset,
83 uint32_t nb_table,
84 int *fd,
85 bool need_vfio)
86{
87 uint64_t *table = NULL;
88
89 if (kvm_enabled()) {
90 table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
91 fd, need_vfio);
92 }
93
94 if (!table) {
95 *fd = -1;
96 table = g_malloc0(nb_table * sizeof(uint64_t));
97 }
98
99 trace_spapr_iommu_new_table(liobn, table, *fd);
100
101 return table;
102}
103
104static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
105{
106 if (!kvm_enabled() ||
107 (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
108 g_free(table);
109 }
110}
111
112
113static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
114 hwaddr addr,
115 IOMMUAccessFlags flag)
116{
117 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
118 uint64_t tce;
119 IOMMUTLBEntry ret = {
120 .target_as = &address_space_memory,
121 .iova = 0,
122 .translated_addr = 0,
123 .addr_mask = ~(hwaddr)0,
124 .perm = IOMMU_NONE,
125 };
126
127 if ((addr >> tcet->page_shift) < tcet->nb_table) {
128
129 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
130
131 tce = tcet->table[addr >> tcet->page_shift];
132 ret.iova = addr & page_mask;
133 ret.translated_addr = tce & page_mask;
134 ret.addr_mask = ~page_mask;
135 ret.perm = spapr_tce_iommu_access_flags(tce);
136 }
137 trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
138 ret.addr_mask);
139
140 return ret;
141}
142
143static int spapr_tce_table_pre_save(void *opaque)
144{
145 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
146
147 tcet->mig_table = tcet->table;
148 tcet->mig_nb_table = tcet->nb_table;
149
150 trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
151 tcet->bus_offset, tcet->page_shift);
152
153 return 0;
154}
155
156static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
157{
158 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
159
160 return 1ULL << tcet->page_shift;
161}
162
163static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu,
164 enum IOMMUMemoryRegionAttr attr, void *data)
165{
166 sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
167
168 if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) {
169 *(int *) data = tcet->fd;
170 return 0;
171 }
172
173 return -EINVAL;
174}
175
176static void spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
177 IOMMUNotifierFlag old,
178 IOMMUNotifierFlag new)
179{
180 struct sPAPRTCETable *tbl = container_of(iommu, sPAPRTCETable, iommu);
181
182 if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
183 spapr_tce_set_need_vfio(tbl, true);
184 } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
185 spapr_tce_set_need_vfio(tbl, false);
186 }
187}
188
189static int spapr_tce_table_post_load(void *opaque, int version_id)
190{
191 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
192 uint32_t old_nb_table = tcet->nb_table;
193 uint64_t old_bus_offset = tcet->bus_offset;
194 uint32_t old_page_shift = tcet->page_shift;
195
196 if (tcet->vdev) {
197 spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
198 }
199
200 if (tcet->mig_nb_table != tcet->nb_table) {
201 spapr_tce_table_disable(tcet);
202 }
203
204 if (tcet->mig_nb_table) {
205 if (!tcet->nb_table) {
206 spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
207 tcet->mig_nb_table);
208 }
209
210 memcpy(tcet->table, tcet->mig_table,
211 tcet->nb_table * sizeof(tcet->table[0]));
212
213 free(tcet->mig_table);
214 tcet->mig_table = NULL;
215 }
216
217 trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
218 tcet->bus_offset, tcet->page_shift);
219
220 return 0;
221}
222
223static bool spapr_tce_table_ex_needed(void *opaque)
224{
225 sPAPRTCETable *tcet = opaque;
226
227 return tcet->bus_offset || tcet->page_shift != 0xC;
228}
229
230static const VMStateDescription vmstate_spapr_tce_table_ex = {
231 .name = "spapr_iommu_ex",
232 .version_id = 1,
233 .minimum_version_id = 1,
234 .needed = spapr_tce_table_ex_needed,
235 .fields = (VMStateField[]) {
236 VMSTATE_UINT64(bus_offset, sPAPRTCETable),
237 VMSTATE_UINT32(page_shift, sPAPRTCETable),
238 VMSTATE_END_OF_LIST()
239 },
240};
241
242static const VMStateDescription vmstate_spapr_tce_table = {
243 .name = "spapr_iommu",
244 .version_id = 2,
245 .minimum_version_id = 2,
246 .pre_save = spapr_tce_table_pre_save,
247 .post_load = spapr_tce_table_post_load,
248 .fields = (VMStateField []) {
249
250 VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable, NULL),
251
252
253 VMSTATE_UINT32(mig_nb_table, sPAPRTCETable),
254 VMSTATE_BOOL(bypass, sPAPRTCETable),
255 VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0,
256 vmstate_info_uint64, uint64_t),
257
258 VMSTATE_END_OF_LIST()
259 },
260 .subsections = (const VMStateDescription*[]) {
261 &vmstate_spapr_tce_table_ex,
262 NULL
263 }
264};
265
266static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
267{
268 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
269 Object *tcetobj = OBJECT(tcet);
270 gchar *tmp;
271
272 tcet->fd = -1;
273 tcet->need_vfio = false;
274 tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
275 memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
276 g_free(tmp);
277
278 tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
279 memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
280 TYPE_SPAPR_IOMMU_MEMORY_REGION,
281 tcetobj, tmp, 0);
282 g_free(tmp);
283
284 QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
285
286 vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
287 tcet);
288}
289
290void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
291{
292 size_t table_size = tcet->nb_table * sizeof(uint64_t);
293 uint64_t *oldtable;
294 int newfd = -1;
295
296 g_assert(need_vfio != tcet->need_vfio);
297
298 tcet->need_vfio = need_vfio;
299
300 if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) {
301 return;
302 }
303
304 oldtable = tcet->table;
305
306 tcet->table = spapr_tce_alloc_table(tcet->liobn,
307 tcet->page_shift,
308 tcet->bus_offset,
309 tcet->nb_table,
310 &newfd,
311 need_vfio);
312 memcpy(tcet->table, oldtable, table_size);
313
314 spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
315
316 tcet->fd = newfd;
317}
318
319sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
320{
321 sPAPRTCETable *tcet;
322 gchar *tmp;
323
324 if (spapr_tce_find_by_liobn(liobn)) {
325 error_report("Attempted to create TCE table with duplicate"
326 " LIOBN 0x%x", liobn);
327 return NULL;
328 }
329
330 tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
331 tcet->liobn = liobn;
332
333 tmp = g_strdup_printf("tce-table-%x", liobn);
334 object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
335 g_free(tmp);
336 object_unref(OBJECT(tcet));
337
338 object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
339
340 return tcet;
341}
342
343void spapr_tce_table_enable(sPAPRTCETable *tcet,
344 uint32_t page_shift, uint64_t bus_offset,
345 uint32_t nb_table)
346{
347 if (tcet->nb_table) {
348 warn_report("trying to enable already enabled TCE table");
349 return;
350 }
351
352 tcet->bus_offset = bus_offset;
353 tcet->page_shift = page_shift;
354 tcet->nb_table = nb_table;
355 tcet->table = spapr_tce_alloc_table(tcet->liobn,
356 tcet->page_shift,
357 tcet->bus_offset,
358 tcet->nb_table,
359 &tcet->fd,
360 tcet->need_vfio);
361
362 memory_region_set_size(MEMORY_REGION(&tcet->iommu),
363 (uint64_t)tcet->nb_table << tcet->page_shift);
364 memory_region_add_subregion(&tcet->root, tcet->bus_offset,
365 MEMORY_REGION(&tcet->iommu));
366}
367
368void spapr_tce_table_disable(sPAPRTCETable *tcet)
369{
370 if (!tcet->nb_table) {
371 return;
372 }
373
374 memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
375 memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
376
377 spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
378 tcet->fd = -1;
379 tcet->table = NULL;
380 tcet->bus_offset = 0;
381 tcet->page_shift = 0;
382 tcet->nb_table = 0;
383}
384
385static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
386{
387 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
388
389 vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet);
390
391 QLIST_REMOVE(tcet, list);
392
393 spapr_tce_table_disable(tcet);
394}
395
396MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
397{
398 return &tcet->root;
399}
400
401static void spapr_tce_reset(DeviceState *dev)
402{
403 sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
404 size_t table_size = tcet->nb_table * sizeof(uint64_t);
405
406 if (tcet->nb_table) {
407 memset(tcet->table, 0, table_size);
408 }
409}
410
411static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
412 target_ulong tce)
413{
414 IOMMUTLBEntry entry;
415 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
416 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
417
418 if (index >= tcet->nb_table) {
419 hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
420 TARGET_FMT_lx "\n", ioba);
421 return H_PARAMETER;
422 }
423
424 tcet->table[index] = tce;
425
426 entry.target_as = &address_space_memory,
427 entry.iova = (ioba - tcet->bus_offset) & page_mask;
428 entry.translated_addr = tce & page_mask;
429 entry.addr_mask = ~page_mask;
430 entry.perm = spapr_tce_iommu_access_flags(tce);
431 memory_region_notify_iommu(&tcet->iommu, entry);
432
433 return H_SUCCESS;
434}
435
436static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
437 sPAPRMachineState *spapr,
438 target_ulong opcode, target_ulong *args)
439{
440 int i;
441 target_ulong liobn = args[0];
442 target_ulong ioba = args[1];
443 target_ulong ioba1 = ioba;
444 target_ulong tce_list = args[2];
445 target_ulong npages = args[3];
446 target_ulong ret = H_PARAMETER, tce = 0;
447 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
448 CPUState *cs = CPU(cpu);
449 hwaddr page_mask, page_size;
450
451 if (!tcet) {
452 return H_PARAMETER;
453 }
454
455 if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
456 return H_PARAMETER;
457 }
458
459 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
460 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
461 ioba &= page_mask;
462
463 for (i = 0; i < npages; ++i, ioba += page_size) {
464 tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
465
466 ret = put_tce_emu(tcet, ioba, tce);
467 if (ret) {
468 break;
469 }
470 }
471
472
473 i = i ? (i - 1) : 0;
474 if (SPAPR_IS_PCI_LIOBN(liobn)) {
475 trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
476 } else {
477 trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
478 }
479 return ret;
480}
481
482static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
483 target_ulong opcode, target_ulong *args)
484{
485 int i;
486 target_ulong liobn = args[0];
487 target_ulong ioba = args[1];
488 target_ulong tce_value = args[2];
489 target_ulong npages = args[3];
490 target_ulong ret = H_PARAMETER;
491 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
492 hwaddr page_mask, page_size;
493
494 if (!tcet) {
495 return H_PARAMETER;
496 }
497
498 if (npages > tcet->nb_table) {
499 return H_PARAMETER;
500 }
501
502 page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
503 page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
504 ioba &= page_mask;
505
506 for (i = 0; i < npages; ++i, ioba += page_size) {
507 ret = put_tce_emu(tcet, ioba, tce_value);
508 if (ret) {
509 break;
510 }
511 }
512 if (SPAPR_IS_PCI_LIOBN(liobn)) {
513 trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
514 } else {
515 trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
516 }
517
518 return ret;
519}
520
521static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
522 target_ulong opcode, target_ulong *args)
523{
524 target_ulong liobn = args[0];
525 target_ulong ioba = args[1];
526 target_ulong tce = args[2];
527 target_ulong ret = H_PARAMETER;
528 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
529
530 if (tcet) {
531 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
532
533 ioba &= page_mask;
534
535 ret = put_tce_emu(tcet, ioba, tce);
536 }
537 if (SPAPR_IS_PCI_LIOBN(liobn)) {
538 trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
539 } else {
540 trace_spapr_iommu_put(liobn, ioba, tce, ret);
541 }
542
543 return ret;
544}
545
546static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
547 target_ulong *tce)
548{
549 unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
550
551 if (index >= tcet->nb_table) {
552 hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
553 TARGET_FMT_lx "\n", ioba);
554 return H_PARAMETER;
555 }
556
557 *tce = tcet->table[index];
558
559 return H_SUCCESS;
560}
561
562static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
563 target_ulong opcode, target_ulong *args)
564{
565 target_ulong liobn = args[0];
566 target_ulong ioba = args[1];
567 target_ulong tce = 0;
568 target_ulong ret = H_PARAMETER;
569 sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
570
571 if (tcet) {
572 hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
573
574 ioba &= page_mask;
575
576 ret = get_tce_emu(tcet, ioba, &tce);
577 if (!ret) {
578 args[0] = tce;
579 }
580 }
581 if (SPAPR_IS_PCI_LIOBN(liobn)) {
582 trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
583 } else {
584 trace_spapr_iommu_get(liobn, ioba, ret, tce);
585 }
586
587 return ret;
588}
589
590int spapr_dma_dt(void *fdt, int node_off, const char *propname,
591 uint32_t liobn, uint64_t window, uint32_t size)
592{
593 uint32_t dma_prop[5];
594 int ret;
595
596 dma_prop[0] = cpu_to_be32(liobn);
597 dma_prop[1] = cpu_to_be32(window >> 32);
598 dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
599 dma_prop[3] = 0;
600 dma_prop[4] = cpu_to_be32(size);
601
602 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
603 if (ret < 0) {
604 return ret;
605 }
606
607 ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
608 if (ret < 0) {
609 return ret;
610 }
611
612 ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
613 if (ret < 0) {
614 return ret;
615 }
616
617 return 0;
618}
619
620int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
621 sPAPRTCETable *tcet)
622{
623 if (!tcet) {
624 return 0;
625 }
626
627 return spapr_dma_dt(fdt, node_off, propname,
628 tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
629}
630
631static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
632{
633 DeviceClass *dc = DEVICE_CLASS(klass);
634 dc->realize = spapr_tce_table_realize;
635 dc->reset = spapr_tce_reset;
636 dc->unrealize = spapr_tce_table_unrealize;
637
638 dc->user_creatable = false;
639
640 QLIST_INIT(&spapr_tce_tables);
641
642
643 spapr_register_hypercall(H_PUT_TCE, h_put_tce);
644 spapr_register_hypercall(H_GET_TCE, h_get_tce);
645 spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
646 spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
647}
648
649static TypeInfo spapr_tce_table_info = {
650 .name = TYPE_SPAPR_TCE_TABLE,
651 .parent = TYPE_DEVICE,
652 .instance_size = sizeof(sPAPRTCETable),
653 .class_init = spapr_tce_table_class_init,
654};
655
656static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
657{
658 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
659
660 imrc->translate = spapr_tce_translate_iommu;
661 imrc->get_min_page_size = spapr_tce_get_min_page_size;
662 imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
663 imrc->get_attr = spapr_tce_get_attr;
664}
665
666static const TypeInfo spapr_iommu_memory_region_info = {
667 .parent = TYPE_IOMMU_MEMORY_REGION,
668 .name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
669 .class_init = spapr_iommu_memory_region_class_init,
670};
671
672static void register_types(void)
673{
674 type_register_static(&spapr_tce_table_info);
675 type_register_static(&spapr_iommu_memory_region_info);
676}
677
678type_init(register_types);
679
