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21#include "qemu/osdep.h"
22#include "hw/sysbus.h"
23#include "target/riscv/cpu.h"
24#include "hw/riscv/sifive_prci.h"
25
26
27
28static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
29{
30 if (addr == 0 ) {
31 return 1 << 31;
32 }
33 if (addr == 8 ) {
34 return 1 << 31;
35 }
36 hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
37 return 0;
38}
39
40static void sifive_prci_write(void *opaque, hwaddr addr,
41 uint64_t val64, unsigned int size)
42{
43
44}
45
46static const MemoryRegionOps sifive_prci_ops = {
47 .read = sifive_prci_read,
48 .write = sifive_prci_write,
49 .endianness = DEVICE_NATIVE_ENDIAN,
50 .valid = {
51 .min_access_size = 4,
52 .max_access_size = 4
53 }
54};
55
56static void sifive_prci_init(Object *obj)
57{
58 SiFivePRCIState *s = SIFIVE_PRCI(obj);
59
60 memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s,
61 TYPE_SIFIVE_PRCI, 0x8000);
62 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
63}
64
65static const TypeInfo sifive_prci_info = {
66 .name = TYPE_SIFIVE_PRCI,
67 .parent = TYPE_SYS_BUS_DEVICE,
68 .instance_size = sizeof(SiFivePRCIState),
69 .instance_init = sifive_prci_init,
70};
71
72static void sifive_prci_register_types(void)
73{
74 type_register_static(&sifive_prci_info);
75}
76
77type_init(sifive_prci_register_types)
78
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81
82
83DeviceState *sifive_prci_create(hwaddr addr)
84{
85 DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI);
86 qdev_init_nofail(dev);
87 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
88 return dev;
89}
90