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28#include "qemu/osdep.h"
29#include "qemu/log.h"
30#include "qemu/error-report.h"
31#include "qapi/error.h"
32#include "hw/hw.h"
33#include "hw/boards.h"
34#include "hw/loader.h"
35#include "hw/sysbus.h"
36#include "hw/char/serial.h"
37#include "target/riscv/cpu.h"
38#include "hw/riscv/riscv_hart.h"
39#include "hw/riscv/sifive_plic.h"
40#include "hw/riscv/sifive_clint.h"
41#include "hw/riscv/sifive_uart.h"
42#include "hw/riscv/sifive_prci.h"
43#include "hw/riscv/sifive_u.h"
44#include "chardev/char.h"
45#include "sysemu/arch_init.h"
46#include "sysemu/device_tree.h"
47#include "exec/address-spaces.h"
48#include "elf.h"
49
50static const struct MemmapEntry {
51 hwaddr base;
52 hwaddr size;
53} sifive_u_memmap[] = {
54 [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
55 [SIFIVE_U_MROM] = { 0x1000, 0x2000 },
56 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
57 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
58 [SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
59 [SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
60 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
61};
62
63static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
64{
65 int i;
66 for (i = 0; i < (len >> 2); i++) {
67 stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
68 }
69}
70
71static uint64_t identity_translate(void *opaque, uint64_t addr)
72{
73 return addr;
74}
75
76static uint64_t load_kernel(const char *kernel_filename)
77{
78 uint64_t kernel_entry, kernel_high;
79
80 if (load_elf(kernel_filename, identity_translate, NULL,
81 &kernel_entry, NULL, &kernel_high,
82 0, ELF_MACHINE, 1, 0) < 0) {
83 error_report("qemu: could not load kernel '%s'", kernel_filename);
84 exit(1);
85 }
86 return kernel_entry;
87}
88
89static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
90 uint64_t mem_size, const char *cmdline)
91{
92 void *fdt;
93 int cpu;
94 uint32_t *cells;
95 char *nodename;
96 uint32_t plic_phandle;
97
98 fdt = s->fdt = create_device_tree(&s->fdt_size);
99 if (!fdt) {
100 error_report("create_device_tree() failed");
101 exit(1);
102 }
103
104 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
105 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
106 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
107 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
108
109 qemu_fdt_add_subnode(fdt, "/soc");
110 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
111 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
112 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
113 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
114
115 nodename = g_strdup_printf("/memory@%lx",
116 (long)memmap[SIFIVE_U_DRAM].base);
117 qemu_fdt_add_subnode(fdt, nodename);
118 qemu_fdt_setprop_cells(fdt, nodename, "reg",
119 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
120 mem_size >> 32, mem_size);
121 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
122 g_free(nodename);
123
124 qemu_fdt_add_subnode(fdt, "/cpus");
125 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
126 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
127 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
128
129 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
130 nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
131 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
132 char *isa = riscv_isa_string(&s->soc.harts[cpu]);
133 qemu_fdt_add_subnode(fdt, nodename);
134 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
135 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
136 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
137 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
138 qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
139 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
140 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
141 qemu_fdt_add_subnode(fdt, intc);
142 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
143 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
144 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
145 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
146 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
147 g_free(isa);
148 g_free(intc);
149 g_free(nodename);
150 }
151
152 cells = g_new0(uint32_t, s->soc.num_harts * 4);
153 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
154 nodename =
155 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
156 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
157 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
158 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
159 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
160 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
161 g_free(nodename);
162 }
163 nodename = g_strdup_printf("/soc/clint@%lx",
164 (long)memmap[SIFIVE_U_CLINT].base);
165 qemu_fdt_add_subnode(fdt, nodename);
166 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
167 qemu_fdt_setprop_cells(fdt, nodename, "reg",
168 0x0, memmap[SIFIVE_U_CLINT].base,
169 0x0, memmap[SIFIVE_U_CLINT].size);
170 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
171 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
172 g_free(cells);
173 g_free(nodename);
174
175 cells = g_new0(uint32_t, s->soc.num_harts * 4);
176 for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
177 nodename =
178 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
179 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
180 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
181 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
182 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
183 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
184 g_free(nodename);
185 }
186 nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
187 (long)memmap[SIFIVE_U_PLIC].base);
188 qemu_fdt_add_subnode(fdt, nodename);
189 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
190 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
191 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
192 qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
193 cells, s->soc.num_harts * sizeof(uint32_t) * 4);
194 qemu_fdt_setprop_cells(fdt, nodename, "reg",
195 0x0, memmap[SIFIVE_U_PLIC].base,
196 0x0, memmap[SIFIVE_U_PLIC].size);
197 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
198 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
199 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
200 qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
201 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
202 plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
203 g_free(cells);
204 g_free(nodename);
205
206 nodename = g_strdup_printf("/uart@%lx",
207 (long)memmap[SIFIVE_U_UART0].base);
208 qemu_fdt_add_subnode(fdt, nodename);
209 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
210 qemu_fdt_setprop_cells(fdt, nodename, "reg",
211 0x0, memmap[SIFIVE_U_UART0].base,
212 0x0, memmap[SIFIVE_U_UART0].size);
213 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
214 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
215
216 qemu_fdt_add_subnode(fdt, "/chosen");
217 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
218 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
219 g_free(nodename);
220}
221
222static void riscv_sifive_u_init(MachineState *machine)
223{
224 const struct MemmapEntry *memmap = sifive_u_memmap;
225
226 SiFiveUState *s = g_new0(SiFiveUState, 1);
227 MemoryRegion *sys_memory = get_system_memory();
228 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
229 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
230
231
232 object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
233 object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
234 &error_abort);
235 object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
236 &error_abort);
237 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
238 &error_abort);
239 object_property_set_bool(OBJECT(&s->soc), true, "realized",
240 &error_abort);
241
242
243 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
244 machine->ram_size, &error_fatal);
245 memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base,
246 main_mem);
247
248
249 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
250
251
252 memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom",
253 memmap[SIFIVE_U_MROM].base, &error_fatal);
254 memory_region_set_readonly(boot_rom, true);
255 memory_region_add_subregion(sys_memory, 0x0, boot_rom);
256
257 if (machine->kernel_filename) {
258 load_kernel(machine->kernel_filename);
259 }
260
261
262 uint32_t reset_vec[8] = {
263 0x00000297,
264 0x02028593,
265 0xf1402573,
266#if defined(TARGET_RISCV32)
267 0x0182a283,
268#elif defined(TARGET_RISCV64)
269 0x0182b283,
270#endif
271 0x00028067,
272 0x00000000,
273 memmap[SIFIVE_U_DRAM].base,
274 0x00000000,
275
276 };
277
278
279 copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_vec));
280
281
282 qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
283 cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base +
284 sizeof(reset_vec), s->fdt, s->fdt_size);
285
286
287 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
288 (char *)SIFIVE_U_PLIC_HART_CONFIG,
289 SIFIVE_U_PLIC_NUM_SOURCES,
290 SIFIVE_U_PLIC_NUM_PRIORITIES,
291 SIFIVE_U_PLIC_PRIORITY_BASE,
292 SIFIVE_U_PLIC_PENDING_BASE,
293 SIFIVE_U_PLIC_ENABLE_BASE,
294 SIFIVE_U_PLIC_ENABLE_STRIDE,
295 SIFIVE_U_PLIC_CONTEXT_BASE,
296 SIFIVE_U_PLIC_CONTEXT_STRIDE,
297 memmap[SIFIVE_U_PLIC].size);
298 sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base,
299 serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
300
301
302 sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
303 memmap[SIFIVE_U_CLINT].size, smp_cpus,
304 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
305}
306
307static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
308{
309 return 0;
310}
311
312static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
313{
314 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
315 k->init = riscv_sifive_u_sysbus_device_init;
316}
317
318static const TypeInfo riscv_sifive_u_device = {
319 .name = TYPE_SIFIVE_U,
320 .parent = TYPE_SYS_BUS_DEVICE,
321 .instance_size = sizeof(SiFiveUState),
322 .class_init = riscv_sifive_u_class_init,
323};
324
325static void riscv_sifive_u_register_types(void)
326{
327 type_register_static(&riscv_sifive_u_device);
328}
329
330type_init(riscv_sifive_u_register_types);
331
332static void riscv_sifive_u_machine_init(MachineClass *mc)
333{
334 mc->desc = "RISC-V Board compatible with SiFive U SDK";
335 mc->init = riscv_sifive_u_init;
336 mc->max_cpus = 1;
337}
338
339DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
340
