qemu/hw/sd/bcm2835_sdhost.c
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   1/*
   2 * Raspberry Pi (BCM2835) SD Host Controller
   3 *
   4 * Copyright (c) 2017 Antfield SAS
   5 *
   6 * Authors:
   7 *  Clement Deschamps <clement.deschamps@antfield.fr>
   8 *  Luc Michel <luc.michel@antfield.fr>
   9 *
  10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11 * See the COPYING file in the top-level directory.
  12 */
  13
  14#include "qemu/osdep.h"
  15#include "qemu/log.h"
  16#include "sysemu/blockdev.h"
  17#include "hw/sd/bcm2835_sdhost.h"
  18#include "trace.h"
  19
  20#define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus"
  21#define BCM2835_SDHOST_BUS(obj) \
  22    OBJECT_CHECK(SDBus, (obj), TYPE_BCM2835_SDHOST_BUS)
  23
  24#define SDCMD  0x00 /* Command to SD card              - 16 R/W */
  25#define SDARG  0x04 /* Argument to SD card             - 32 R/W */
  26#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
  27#define SDCDIV 0x0c /* Start value for clock divider   - 11 R/W */
  28#define SDRSP0 0x10 /* SD card rsp (31:0)         - 32 R   */
  29#define SDRSP1 0x14 /* SD card rsp (63:32)        - 32 R   */
  30#define SDRSP2 0x18 /* SD card rsp (95:64)        - 32 R   */
  31#define SDRSP3 0x1c /* SD card rsp (127:96)       - 32 R   */
  32#define SDHSTS 0x20 /* SD host status                  - 11 R   */
  33#define SDVDD  0x30 /* SD card power control           -  1 R/W */
  34#define SDEDM  0x34 /* Emergency Debug Mode            - 13 R/W */
  35#define SDHCFG 0x38 /* Host configuration              -  2 R/W */
  36#define SDHBCT 0x3c /* Host byte count (debug)         - 32 R/W */
  37#define SDDATA 0x40 /* Data to/from SD card            - 32 R/W */
  38#define SDHBLC 0x50 /* Host block count (SDIO/SDHC)    -  9 R/W */
  39
  40#define SDCMD_NEW_FLAG                  0x8000
  41#define SDCMD_FAIL_FLAG                 0x4000
  42#define SDCMD_BUSYWAIT                  0x800
  43#define SDCMD_NO_RESPONSE               0x400
  44#define SDCMD_LONG_RESPONSE             0x200
  45#define SDCMD_WRITE_CMD                 0x80
  46#define SDCMD_READ_CMD                  0x40
  47#define SDCMD_CMD_MASK                  0x3f
  48
  49#define SDCDIV_MAX_CDIV                 0x7ff
  50
  51#define SDHSTS_BUSY_IRPT                0x400
  52#define SDHSTS_BLOCK_IRPT               0x200
  53#define SDHSTS_SDIO_IRPT                0x100
  54#define SDHSTS_REW_TIME_OUT             0x80
  55#define SDHSTS_CMD_TIME_OUT             0x40
  56#define SDHSTS_CRC16_ERROR              0x20
  57#define SDHSTS_CRC7_ERROR               0x10
  58#define SDHSTS_FIFO_ERROR               0x08
  59/* Reserved */
  60/* Reserved */
  61#define SDHSTS_DATA_FLAG                0x01
  62
  63#define SDHCFG_BUSY_IRPT_EN     (1 << 10)
  64#define SDHCFG_BLOCK_IRPT_EN    (1 << 8)
  65#define SDHCFG_SDIO_IRPT_EN     (1 << 5)
  66#define SDHCFG_DATA_IRPT_EN     (1 << 4)
  67#define SDHCFG_SLOW_CARD        (1 << 3)
  68#define SDHCFG_WIDE_EXT_BUS     (1 << 2)
  69#define SDHCFG_WIDE_INT_BUS     (1 << 1)
  70#define SDHCFG_REL_CMD_LINE     (1 << 0)
  71
  72#define SDEDM_FORCE_DATA_MODE   (1 << 19)
  73#define SDEDM_CLOCK_PULSE       (1 << 20)
  74#define SDEDM_BYPASS            (1 << 21)
  75
  76#define SDEDM_WRITE_THRESHOLD_SHIFT 9
  77#define SDEDM_READ_THRESHOLD_SHIFT 14
  78#define SDEDM_THRESHOLD_MASK     0x1f
  79
  80#define SDEDM_FSM_MASK           0xf
  81#define SDEDM_FSM_IDENTMODE      0x0
  82#define SDEDM_FSM_DATAMODE       0x1
  83#define SDEDM_FSM_READDATA       0x2
  84#define SDEDM_FSM_WRITEDATA      0x3
  85#define SDEDM_FSM_READWAIT       0x4
  86#define SDEDM_FSM_READCRC        0x5
  87#define SDEDM_FSM_WRITECRC       0x6
  88#define SDEDM_FSM_WRITEWAIT1     0x7
  89#define SDEDM_FSM_POWERDOWN      0x8
  90#define SDEDM_FSM_POWERUP        0x9
  91#define SDEDM_FSM_WRITESTART1    0xa
  92#define SDEDM_FSM_WRITESTART2    0xb
  93#define SDEDM_FSM_GENPULSES      0xc
  94#define SDEDM_FSM_WRITEWAIT2     0xd
  95#define SDEDM_FSM_STARTPOWDOWN   0xf
  96
  97#define SDDATA_FIFO_WORDS        16
  98
  99static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s)
 100{
 101    uint32_t irq = s->status &
 102        (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT);
 103    trace_bcm2835_sdhost_update_irq(irq);
 104    qemu_set_irq(s->irq, !!irq);
 105}
 106
 107static void bcm2835_sdhost_send_command(BCM2835SDHostState *s)
 108{
 109    SDRequest request;
 110    uint8_t rsp[16];
 111    int rlen;
 112
 113    request.cmd = s->cmd & SDCMD_CMD_MASK;
 114    request.arg = s->cmdarg;
 115
 116    rlen = sdbus_do_command(&s->sdbus, &request, rsp);
 117    if (rlen < 0) {
 118        goto error;
 119    }
 120    if (!(s->cmd & SDCMD_NO_RESPONSE)) {
 121#define RWORD(n) (((uint32_t)rsp[n] << 24) | (rsp[n + 1] << 16) \
 122                  | (rsp[n + 2] << 8) | rsp[n + 3])
 123        if (rlen == 0 || (rlen == 4 && (s->cmd & SDCMD_LONG_RESPONSE))) {
 124            goto error;
 125        }
 126        if (rlen != 4 && rlen != 16) {
 127            goto error;
 128        }
 129        if (rlen == 4) {
 130            s->rsp[0] = RWORD(0);
 131            s->rsp[1] = s->rsp[2] = s->rsp[3] = 0;
 132        } else {
 133            s->rsp[0] = RWORD(12);
 134            s->rsp[1] = RWORD(8);
 135            s->rsp[2] = RWORD(4);
 136            s->rsp[3] = RWORD(0);
 137        }
 138#undef RWORD
 139    }
 140    /* We never really delay commands, so if this was a 'busywait' command
 141     * then we've completed it now and can raise the interrupt.
 142     */
 143    if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
 144        s->status |= SDHSTS_BUSY_IRPT;
 145    }
 146    return;
 147
 148error:
 149    s->cmd |= SDCMD_FAIL_FLAG;
 150    s->status |= SDHSTS_CMD_TIME_OUT;
 151}
 152
 153static void bcm2835_sdhost_fifo_push(BCM2835SDHostState *s, uint32_t value)
 154{
 155    int n;
 156
 157    if (s->fifo_len == BCM2835_SDHOST_FIFO_LEN) {
 158        /* FIFO overflow */
 159        return;
 160    }
 161    n = (s->fifo_pos + s->fifo_len) & (BCM2835_SDHOST_FIFO_LEN - 1);
 162    s->fifo_len++;
 163    s->fifo[n] = value;
 164}
 165
 166static uint32_t bcm2835_sdhost_fifo_pop(BCM2835SDHostState *s)
 167{
 168    uint32_t value;
 169
 170    if (s->fifo_len == 0) {
 171        /* FIFO underflow */
 172        return 0;
 173    }
 174    value = s->fifo[s->fifo_pos];
 175    s->fifo_len--;
 176    s->fifo_pos = (s->fifo_pos + 1) & (BCM2835_SDHOST_FIFO_LEN - 1);
 177    return value;
 178}
 179
 180static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
 181{
 182    uint32_t value = 0;
 183    int n;
 184    int is_read;
 185
 186    is_read = (s->cmd & SDCMD_READ_CMD) != 0;
 187    if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus))) {
 188        if (is_read) {
 189            n = 0;
 190            while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) {
 191                value |= (uint32_t)sdbus_read_data(&s->sdbus) << (n * 8);
 192                s->datacnt--;
 193                n++;
 194                if (n == 4) {
 195                    bcm2835_sdhost_fifo_push(s, value);
 196                    s->status |= SDHSTS_DATA_FLAG;
 197                    if (s->config & SDHCFG_DATA_IRPT_EN) {
 198                        s->status |= SDHSTS_SDIO_IRPT;
 199                    }
 200                    n = 0;
 201                    value = 0;
 202                }
 203            }
 204            if (n != 0) {
 205                bcm2835_sdhost_fifo_push(s, value);
 206                s->status |= SDHSTS_DATA_FLAG;
 207            }
 208        } else { /* write */
 209            n = 0;
 210            while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
 211                if (n == 0) {
 212                    value = bcm2835_sdhost_fifo_pop(s);
 213                    s->status |= SDHSTS_DATA_FLAG;
 214                    if (s->config & SDHCFG_DATA_IRPT_EN) {
 215                        s->status |= SDHSTS_SDIO_IRPT;
 216                    }
 217                    n = 4;
 218                }
 219                n--;
 220                s->datacnt--;
 221                sdbus_write_data(&s->sdbus, value & 0xff);
 222                value >>= 8;
 223            }
 224        }
 225        if (s->datacnt == 0) {
 226            s->edm &= ~SDEDM_FSM_MASK;
 227            s->edm |= SDEDM_FSM_DATAMODE;
 228            trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
 229
 230            if ((s->cmd & SDCMD_WRITE_CMD) &&
 231                (s->config & SDHCFG_BLOCK_IRPT_EN)) {
 232                s->status |= SDHSTS_BLOCK_IRPT;
 233            }
 234        }
 235    }
 236
 237    bcm2835_sdhost_update_irq(s);
 238
 239    s->edm &= ~(0x1f << 4);
 240    s->edm |= ((s->fifo_len & 0x1f) << 4);
 241    trace_bcm2835_sdhost_edm_change("fifo run", s->edm);
 242}
 243
 244static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
 245    unsigned size)
 246{
 247    BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
 248    uint32_t res = 0;
 249
 250    switch (offset) {
 251    case SDCMD:
 252        res = s->cmd;
 253        break;
 254    case SDHSTS:
 255        res = s->status;
 256        break;
 257    case SDRSP0:
 258        res = s->rsp[0];
 259        break;
 260    case SDRSP1:
 261        res = s->rsp[1];
 262        break;
 263    case SDRSP2:
 264        res = s->rsp[2];
 265        break;
 266    case SDRSP3:
 267        res = s->rsp[3];
 268        break;
 269    case SDEDM:
 270        res = s->edm;
 271        break;
 272    case SDVDD:
 273        res = s->vdd;
 274        break;
 275    case SDDATA:
 276        res = bcm2835_sdhost_fifo_pop(s);
 277        bcm2835_sdhost_fifo_run(s);
 278        break;
 279    case SDHBCT:
 280        res = s->hbct;
 281        break;
 282    case SDHBLC:
 283        res = s->hblc;
 284        break;
 285
 286    default:
 287        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 288                      __func__, offset);
 289        res = 0;
 290        break;
 291    }
 292
 293    trace_bcm2835_sdhost_read(offset, res, size);
 294
 295    return res;
 296}
 297
 298static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
 299    uint64_t value, unsigned size)
 300{
 301    BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
 302
 303    trace_bcm2835_sdhost_write(offset, value, size);
 304
 305    switch (offset) {
 306    case SDCMD:
 307        s->cmd = value;
 308        if (value & SDCMD_NEW_FLAG) {
 309            bcm2835_sdhost_send_command(s);
 310            bcm2835_sdhost_fifo_run(s);
 311            s->cmd &= ~SDCMD_NEW_FLAG;
 312        }
 313        break;
 314    case SDTOUT:
 315        break;
 316    case SDCDIV:
 317        break;
 318    case SDHSTS:
 319        s->status &= ~value;
 320        bcm2835_sdhost_update_irq(s);
 321        break;
 322    case SDARG:
 323        s->cmdarg = value;
 324        break;
 325    case SDEDM:
 326        if ((value & 0xf) == 0xf) {
 327            /* power down */
 328            value &= ~0xf;
 329        }
 330        s->edm = value;
 331        trace_bcm2835_sdhost_edm_change("guest register write", s->edm);
 332        break;
 333    case SDHCFG:
 334        s->config = value;
 335        bcm2835_sdhost_fifo_run(s);
 336        break;
 337    case SDVDD:
 338        s->vdd = value;
 339        break;
 340    case SDDATA:
 341        bcm2835_sdhost_fifo_push(s, value);
 342        bcm2835_sdhost_fifo_run(s);
 343        break;
 344    case SDHBCT:
 345        s->hbct = value;
 346        break;
 347    case SDHBLC:
 348        s->hblc = value;
 349        s->datacnt = s->hblc * s->hbct;
 350        bcm2835_sdhost_fifo_run(s);
 351        break;
 352
 353    default:
 354        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 355                      __func__, offset);
 356        break;
 357    }
 358}
 359
 360static const MemoryRegionOps bcm2835_sdhost_ops = {
 361    .read = bcm2835_sdhost_read,
 362    .write = bcm2835_sdhost_write,
 363    .endianness = DEVICE_NATIVE_ENDIAN,
 364};
 365
 366static const VMStateDescription vmstate_bcm2835_sdhost = {
 367    .name = TYPE_BCM2835_SDHOST,
 368    .version_id = 1,
 369    .minimum_version_id = 1,
 370    .fields = (VMStateField[]) {
 371        VMSTATE_UINT32(cmd, BCM2835SDHostState),
 372        VMSTATE_UINT32(cmdarg, BCM2835SDHostState),
 373        VMSTATE_UINT32(status, BCM2835SDHostState),
 374        VMSTATE_UINT32_ARRAY(rsp, BCM2835SDHostState, 4),
 375        VMSTATE_UINT32(config, BCM2835SDHostState),
 376        VMSTATE_UINT32(edm, BCM2835SDHostState),
 377        VMSTATE_UINT32(vdd, BCM2835SDHostState),
 378        VMSTATE_UINT32(hbct, BCM2835SDHostState),
 379        VMSTATE_UINT32(hblc, BCM2835SDHostState),
 380        VMSTATE_INT32(fifo_pos, BCM2835SDHostState),
 381        VMSTATE_INT32(fifo_len, BCM2835SDHostState),
 382        VMSTATE_UINT32_ARRAY(fifo, BCM2835SDHostState, BCM2835_SDHOST_FIFO_LEN),
 383        VMSTATE_UINT32(datacnt, BCM2835SDHostState),
 384        VMSTATE_END_OF_LIST()
 385    }
 386};
 387
 388static void bcm2835_sdhost_init(Object *obj)
 389{
 390    BCM2835SDHostState *s = BCM2835_SDHOST(obj);
 391
 392    qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
 393                        TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
 394
 395    memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
 396                          TYPE_BCM2835_SDHOST, 0x1000);
 397    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 398    sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
 399}
 400
 401static void bcm2835_sdhost_reset(DeviceState *dev)
 402{
 403    BCM2835SDHostState *s = BCM2835_SDHOST(dev);
 404
 405    s->cmd = 0;
 406    s->cmdarg = 0;
 407    s->edm = 0x0000c60f;
 408    trace_bcm2835_sdhost_edm_change("device reset", s->edm);
 409    s->config = 0;
 410    s->hbct = 0;
 411    s->hblc = 0;
 412    s->datacnt = 0;
 413    s->fifo_pos = 0;
 414    s->fifo_len = 0;
 415}
 416
 417static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data)
 418{
 419    DeviceClass *dc = DEVICE_CLASS(klass);
 420
 421    dc->reset = bcm2835_sdhost_reset;
 422    dc->vmsd = &vmstate_bcm2835_sdhost;
 423}
 424
 425static TypeInfo bcm2835_sdhost_info = {
 426    .name          = TYPE_BCM2835_SDHOST,
 427    .parent        = TYPE_SYS_BUS_DEVICE,
 428    .instance_size = sizeof(BCM2835SDHostState),
 429    .class_init    = bcm2835_sdhost_class_init,
 430    .instance_init = bcm2835_sdhost_init,
 431};
 432
 433static const TypeInfo bcm2835_sdhost_bus_info = {
 434    .name = TYPE_BCM2835_SDHOST_BUS,
 435    .parent = TYPE_SD_BUS,
 436    .instance_size = sizeof(SDBus),
 437};
 438
 439static void bcm2835_sdhost_register_types(void)
 440{
 441    type_register_static(&bcm2835_sdhost_info);
 442    type_register_static(&bcm2835_sdhost_bus_info);
 443}
 444
 445type_init(bcm2835_sdhost_register_types)
 446