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24#ifndef HW_ARM_GICV3_COMMON_H
25#define HW_ARM_GICV3_COMMON_H
26
27#include "hw/sysbus.h"
28#include "hw/intc/arm_gic_common.h"
29
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34
35#define GICV3_MAXIRQ 1020
36#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
37
38
39#define GICV3_TARGETLIST_BITS 16
40
41
42#define GICV3_LR_MAX 16
43
44
45#define GIC_MIN_BPR 0
46
47#define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
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62
63#define GICV3_BMP_SIZE (DIV_ROUND_UP(GICV3_MAXIRQ, 32))
64
65#define GIC_DECLARE_BITMAP(name) \
66 uint32_t name[GICV3_BMP_SIZE]
67
68#define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
69#define GIC_BIT_WORD(nr) ((nr) / 32)
70
71static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
72{
73 uint32_t mask = GIC_BIT_MASK(nr);
74 uint32_t *p = addr + GIC_BIT_WORD(nr);
75
76 *p |= mask;
77}
78
79static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
80{
81 uint32_t mask = GIC_BIT_MASK(nr);
82 uint32_t *p = addr + GIC_BIT_WORD(nr);
83
84 *p &= ~mask;
85}
86
87static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
88{
89 return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
90}
91
92static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
93{
94 uint32_t mask = GIC_BIT_MASK(nr);
95 uint32_t *p = addr + GIC_BIT_WORD(nr);
96
97 *p &= ~mask;
98 *p |= (val & 1U) << (nr % 32);
99}
100
101
102static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
103{
104 return addr + GIC_BIT_WORD(nr);
105}
106
107typedef struct GICv3State GICv3State;
108typedef struct GICv3CPUState GICv3CPUState;
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127
128#define GICV3_G0 0
129#define GICV3_G1 1
130#define GICV3_G1NS 2
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136
137#define GICV3_S 0
138#define GICV3_NS 1
139
140typedef struct {
141 int irq;
142 uint8_t prio;
143 int grp;
144} PendingIrq;
145
146struct GICv3CPUState {
147 GICv3State *gic;
148 CPUState *cpu;
149 qemu_irq parent_irq;
150 qemu_irq parent_fiq;
151 qemu_irq parent_virq;
152 qemu_irq parent_vfiq;
153 qemu_irq maintenance_irq;
154
155
156 uint32_t level;
157
158 uint32_t gicr_ctlr;
159 uint64_t gicr_typer;
160 uint32_t gicr_statusr[2];
161 uint32_t gicr_waker;
162 uint64_t gicr_propbaser;
163 uint64_t gicr_pendbaser;
164
165 uint32_t gicr_igroupr0;
166 uint32_t gicr_ienabler0;
167 uint32_t gicr_ipendr0;
168 uint32_t gicr_iactiver0;
169 uint32_t edge_trigger;
170 uint32_t gicr_igrpmodr0;
171 uint32_t gicr_nsacr;
172 uint8_t gicr_ipriorityr[GIC_INTERNAL];
173
174
175 uint64_t icc_sre_el1;
176 uint64_t icc_ctlr_el1[2];
177 uint64_t icc_pmr_el1;
178 uint64_t icc_bpr[3];
179 uint64_t icc_apr[3][4];
180 uint64_t icc_igrpen[3];
181 uint64_t icc_ctlr_el3;
182
183
184 uint64_t ich_apr[3][4];
185 uint64_t ich_hcr_el2;
186 uint64_t ich_lr_el2[GICV3_LR_MAX];
187 uint64_t ich_vmcr_el2;
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193
194 int num_list_regs;
195 int vpribits;
196 int vprebits;
197
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201
202 PendingIrq hppi;
203
204 bool seenbetter;
205};
206
207struct GICv3State {
208
209 SysBusDevice parent_obj;
210
211
212 MemoryRegion iomem_dist;
213 MemoryRegion iomem_redist;
214
215 uint32_t num_cpu;
216 uint32_t num_irq;
217 uint32_t revision;
218 bool security_extn;
219 bool irq_reset_nonsecure;
220
221 int dev_fd;
222 Error *migration_blocker;
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228
229 uint32_t gicd_ctlr;
230 uint32_t gicd_statusr[2];
231 GIC_DECLARE_BITMAP(group);
232 GIC_DECLARE_BITMAP(grpmod);
233 GIC_DECLARE_BITMAP(enabled);
234 GIC_DECLARE_BITMAP(pending);
235 GIC_DECLARE_BITMAP(active);
236 GIC_DECLARE_BITMAP(level);
237 GIC_DECLARE_BITMAP(edge_trigger);
238 uint8_t gicd_ipriority[GICV3_MAXIRQ];
239 uint64_t gicd_irouter[GICV3_MAXIRQ];
240
241
242
243 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
244 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
245
246 GICv3CPUState *cpu;
247};
248
249#define GICV3_BITMAP_ACCESSORS(BMP) \
250 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \
251 { \
252 gic_bmp_set_bit(irq, s->BMP); \
253 } \
254 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \
255 { \
256 return gic_bmp_test_bit(irq, s->BMP); \
257 } \
258 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
259 { \
260 gic_bmp_clear_bit(irq, s->BMP); \
261 } \
262 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \
263 int irq, int value) \
264 { \
265 gic_bmp_replace_bit(irq, s->BMP, value); \
266 }
267
268GICV3_BITMAP_ACCESSORS(group)
269GICV3_BITMAP_ACCESSORS(grpmod)
270GICV3_BITMAP_ACCESSORS(enabled)
271GICV3_BITMAP_ACCESSORS(pending)
272GICV3_BITMAP_ACCESSORS(active)
273GICV3_BITMAP_ACCESSORS(level)
274GICV3_BITMAP_ACCESSORS(edge_trigger)
275
276#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
277#define ARM_GICV3_COMMON(obj) \
278 OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
279#define ARM_GICV3_COMMON_CLASS(klass) \
280 OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON)
281#define ARM_GICV3_COMMON_GET_CLASS(obj) \
282 OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
283
284typedef struct ARMGICv3CommonClass {
285
286 SysBusDeviceClass parent_class;
287
288
289 void (*pre_save)(GICv3State *s);
290 void (*post_load)(GICv3State *s);
291} ARMGICv3CommonClass;
292
293void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
294 const MemoryRegionOps *ops);
295
296#endif
297