1#ifndef HW_SPAPR_H
2#define HW_SPAPR_H
3
4#include "sysemu/dma.h"
5#include "hw/boards.h"
6#include "hw/ppc/xics.h"
7#include "hw/ppc/spapr_drc.h"
8#include "hw/mem/pc-dimm.h"
9#include "hw/ppc/spapr_ovec.h"
10
11struct VIOsPAPRBus;
12struct sPAPRPHBState;
13struct sPAPRNVRAM;
14typedef struct sPAPREventLogEntry sPAPREventLogEntry;
15typedef struct sPAPREventSource sPAPREventSource;
16typedef struct sPAPRPendingHPT sPAPRPendingHPT;
17
18#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
19#define SPAPR_ENTRY_POINT 0x100
20
21#define SPAPR_TIMEBASE_FREQ 512000000ULL
22
23#define TYPE_SPAPR_RTC "spapr-rtc"
24
25#define SPAPR_RTC(obj) \
26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
27
28typedef struct sPAPRRTCState sPAPRRTCState;
29struct sPAPRRTCState {
30
31 DeviceState parent_obj;
32 int64_t ns_offset;
33};
34
35typedef struct sPAPRDIMMState sPAPRDIMMState;
36typedef struct sPAPRMachineClass sPAPRMachineClass;
37
38#define TYPE_SPAPR_MACHINE "spapr-machine"
39#define SPAPR_MACHINE(obj) \
40 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
41#define SPAPR_MACHINE_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
43#define SPAPR_MACHINE_CLASS(klass) \
44 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
45
46typedef enum {
47 SPAPR_RESIZE_HPT_DEFAULT = 0,
48 SPAPR_RESIZE_HPT_DISABLED,
49 SPAPR_RESIZE_HPT_ENABLED,
50 SPAPR_RESIZE_HPT_REQUIRED,
51} sPAPRResizeHPT;
52
53
54
55
56
57
58#define SPAPR_CAP_HTM 0x00
59
60#define SPAPR_CAP_VSX 0x01
61
62#define SPAPR_CAP_DFP 0x02
63
64#define SPAPR_CAP_CFPC 0x03
65
66#define SPAPR_CAP_SBBC 0x04
67
68#define SPAPR_CAP_IBS 0x05
69
70#define SPAPR_CAP_NUM (SPAPR_CAP_IBS + 1)
71
72
73
74
75
76#define SPAPR_CAP_OFF 0x00
77#define SPAPR_CAP_ON 0x01
78
79#define SPAPR_CAP_BROKEN 0x00
80#define SPAPR_CAP_WORKAROUND 0x01
81#define SPAPR_CAP_FIXED 0x02
82#define SPAPR_CAP_FIXED_IBS 0x02
83#define SPAPR_CAP_FIXED_CCD 0x03
84
85typedef struct sPAPRCapabilities sPAPRCapabilities;
86struct sPAPRCapabilities {
87 uint8_t caps[SPAPR_CAP_NUM];
88};
89
90
91
92
93struct sPAPRMachineClass {
94
95 MachineClass parent_class;
96
97
98 bool dr_lmb_enabled;
99 bool use_ohci_by_default;
100 bool pre_2_10_has_unused_icps;
101 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
102 uint64_t *buid, hwaddr *pio,
103 hwaddr *mmio32, hwaddr *mmio64,
104 unsigned n_dma, uint32_t *liobns, Error **errp);
105 sPAPRResizeHPT resize_hpt_default;
106 sPAPRCapabilities default_caps;
107};
108
109
110
111
112struct sPAPRMachineState {
113
114 MachineState parent_obj;
115
116 struct VIOsPAPRBus *vio_bus;
117 QLIST_HEAD(, sPAPRPHBState) phbs;
118 struct sPAPRNVRAM *nvram;
119 ICSState *ics;
120 sPAPRRTCState rtc;
121
122 sPAPRResizeHPT resize_hpt;
123 void *htab;
124 uint32_t htab_shift;
125 uint64_t patb_entry;
126 sPAPRPendingHPT *pending_hpt;
127
128 hwaddr rma_size;
129 int vrma_adjust;
130 ssize_t rtas_size;
131 void *rtas_blob;
132 long kernel_size;
133 bool kernel_le;
134 uint32_t initrd_base;
135 long initrd_size;
136 uint64_t rtc_offset;
137 struct PPCTimebase tb;
138 bool has_graphics;
139 uint32_t vsmt;
140
141 Notifier epow_notifier;
142 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
143 bool use_hotplug_event_source;
144 sPAPREventSource *event_sources;
145
146
147 bool cas_reboot;
148 bool cas_legacy_guest_workaround;
149 sPAPROptionVector *ov5;
150 sPAPROptionVector *ov5_cas;
151 uint32_t max_compat_pvr;
152
153
154 int htab_save_index;
155 bool htab_first_pass;
156 int htab_fd;
157
158
159
160
161 QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs;
162
163
164 char *kvm_type;
165 MemoryHotplugState hotplug_memory;
166
167 const char *icp_type;
168
169 bool cmd_line_caps[SPAPR_CAP_NUM];
170 sPAPRCapabilities def, eff, mig;
171};
172
173#define H_SUCCESS 0
174#define H_BUSY 1
175#define H_CLOSED 2
176#define H_NOT_AVAILABLE 3
177#define H_CONSTRAINED 4
178#define H_PARTIAL 5
179#define H_IN_PROGRESS 14
180#define H_PAGE_REGISTERED 15
181#define H_PARTIAL_STORE 16
182#define H_PENDING 17
183#define H_CONTINUE 18
184#define H_LONG_BUSY_START_RANGE 9900
185#define H_LONG_BUSY_ORDER_1_MSEC 9900
186
187#define H_LONG_BUSY_ORDER_10_MSEC 9901
188
189#define H_LONG_BUSY_ORDER_100_MSEC 9902
190
191#define H_LONG_BUSY_ORDER_1_SEC 9903
192
193#define H_LONG_BUSY_ORDER_10_SEC 9904
194
195#define H_LONG_BUSY_ORDER_100_SEC 9905
196
197#define H_LONG_BUSY_END_RANGE 9905
198#define H_HARDWARE -1
199#define H_FUNCTION -2
200#define H_PRIVILEGE -3
201#define H_PARAMETER -4
202#define H_BAD_MODE -5
203#define H_PTEG_FULL -6
204#define H_NOT_FOUND -7
205#define H_RESERVED_DABR -8
206#define H_NO_MEM -9
207#define H_AUTHORITY -10
208#define H_PERMISSION -11
209#define H_DROPPED -12
210#define H_SOURCE_PARM -13
211#define H_DEST_PARM -14
212#define H_REMOTE_PARM -15
213#define H_RESOURCE -16
214#define H_ADAPTER_PARM -17
215#define H_RH_PARM -18
216#define H_RCQ_PARM -19
217#define H_SCQ_PARM -20
218#define H_EQ_PARM -21
219#define H_RT_PARM -22
220#define H_ST_PARM -23
221#define H_SIGT_PARM -24
222#define H_TOKEN_PARM -25
223#define H_MLENGTH_PARM -27
224#define H_MEM_PARM -28
225#define H_MEM_ACCESS_PARM -29
226#define H_ATTR_PARM -30
227#define H_PORT_PARM -31
228#define H_MCG_PARM -32
229#define H_VL_PARM -33
230#define H_TSIZE_PARM -34
231#define H_TRACE_PARM -35
232
233#define H_MASK_PARM -37
234#define H_MCG_FULL -38
235#define H_ALIAS_EXIST -39
236#define H_P_COUNTER -40
237#define H_TABLE_FULL -41
238#define H_ALT_TABLE -42
239#define H_MR_CONDITION -43
240#define H_NOT_ENOUGH_RESOURCES -44
241#define H_R_STATE -45
242#define H_RESCINDEND -46
243#define H_P2 -55
244#define H_P3 -56
245#define H_P4 -57
246#define H_P5 -58
247#define H_P6 -59
248#define H_P7 -60
249#define H_P8 -61
250#define H_P9 -62
251#define H_UNSUPPORTED_FLAG -256
252#define H_MULTI_THREADS_ACTIVE -9005
253
254
255
256
257
258
259
260
261
262
263#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
264 && (x <= H_LONG_BUSY_END_RANGE))
265
266
267#define H_LARGE_PAGE (1ULL<<(63-16))
268#define H_EXACT (1ULL<<(63-24))
269#define H_R_XLATE (1ULL<<(63-25))
270#define H_READ_4 (1ULL<<(63-26))
271#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
272#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
273#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
274#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
275#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
276#define H_AVPN (1ULL<<(63-32))
277#define H_ANDCOND (1ULL<<(63-33))
278#define H_ICACHE_INVALIDATE (1ULL<<(63-40))
279#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))
280#define H_ZERO_PAGE (1ULL<<(63-48))
281#define H_COPY_PAGE (1ULL<<(63-49))
282#define H_N (1ULL<<(63-61))
283#define H_PP1 (1ULL<<(63-62))
284#define H_PP2 (1ULL<<(63-63))
285
286
287#define H_SET_MODE_RESOURCE_SET_CIABR 1
288#define H_SET_MODE_RESOURCE_SET_DAWR 2
289#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
290#define H_SET_MODE_RESOURCE_LE 4
291
292
293#define H_SET_MODE_ENDIAN_BIG 0
294#define H_SET_MODE_ENDIAN_LITTLE 1
295
296
297#define H_VASI_INVALID 0
298#define H_VASI_ENABLED 1
299#define H_VASI_ABORTED 2
300#define H_VASI_SUSPENDING 3
301#define H_VASI_SUSPENDED 4
302#define H_VASI_RESUMED 5
303#define H_VASI_COMPLETED 6
304
305
306#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
307#define H_DABRX_KERNEL (1ULL<<(63-62))
308#define H_DABRX_USER (1ULL<<(63-63))
309
310
311#define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
312#define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
313#define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
314#define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
315#define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
316#define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
317#define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
318#define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
319#define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
320#define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
321#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
322
323
324#define H_CB_ALIGNMENT 4096
325
326
327#define H_REMOVE 0x04
328#define H_ENTER 0x08
329#define H_READ 0x0c
330#define H_CLEAR_MOD 0x10
331#define H_CLEAR_REF 0x14
332#define H_PROTECT 0x18
333#define H_GET_TCE 0x1c
334#define H_PUT_TCE 0x20
335#define H_SET_SPRG0 0x24
336#define H_SET_DABR 0x28
337#define H_PAGE_INIT 0x2c
338#define H_SET_ASR 0x30
339#define H_ASR_ON 0x34
340#define H_ASR_OFF 0x38
341#define H_LOGICAL_CI_LOAD 0x3c
342#define H_LOGICAL_CI_STORE 0x40
343#define H_LOGICAL_CACHE_LOAD 0x44
344#define H_LOGICAL_CACHE_STORE 0x48
345#define H_LOGICAL_ICBI 0x4c
346#define H_LOGICAL_DCBF 0x50
347#define H_GET_TERM_CHAR 0x54
348#define H_PUT_TERM_CHAR 0x58
349#define H_REAL_TO_LOGICAL 0x5c
350#define H_HYPERVISOR_DATA 0x60
351#define H_EOI 0x64
352#define H_CPPR 0x68
353#define H_IPI 0x6c
354#define H_IPOLL 0x70
355#define H_XIRR 0x74
356#define H_PERFMON 0x7c
357#define H_MIGRATE_DMA 0x78
358#define H_REGISTER_VPA 0xDC
359#define H_CEDE 0xE0
360#define H_CONFER 0xE4
361#define H_PROD 0xE8
362#define H_GET_PPP 0xEC
363#define H_SET_PPP 0xF0
364#define H_PURR 0xF4
365#define H_PIC 0xF8
366#define H_REG_CRQ 0xFC
367#define H_FREE_CRQ 0x100
368#define H_VIO_SIGNAL 0x104
369#define H_SEND_CRQ 0x108
370#define H_COPY_RDMA 0x110
371#define H_REGISTER_LOGICAL_LAN 0x114
372#define H_FREE_LOGICAL_LAN 0x118
373#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
374#define H_SEND_LOGICAL_LAN 0x120
375#define H_BULK_REMOVE 0x124
376#define H_MULTICAST_CTRL 0x130
377#define H_SET_XDABR 0x134
378#define H_STUFF_TCE 0x138
379#define H_PUT_TCE_INDIRECT 0x13C
380#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
381#define H_VTERM_PARTNER_INFO 0x150
382#define H_REGISTER_VTERM 0x154
383#define H_FREE_VTERM 0x158
384#define H_RESET_EVENTS 0x15C
385#define H_ALLOC_RESOURCE 0x160
386#define H_FREE_RESOURCE 0x164
387#define H_MODIFY_QP 0x168
388#define H_QUERY_QP 0x16C
389#define H_REREGISTER_PMR 0x170
390#define H_REGISTER_SMR 0x174
391#define H_QUERY_MR 0x178
392#define H_QUERY_MW 0x17C
393#define H_QUERY_HCA 0x180
394#define H_QUERY_PORT 0x184
395#define H_MODIFY_PORT 0x188
396#define H_DEFINE_AQP1 0x18C
397#define H_GET_TRACE_BUFFER 0x190
398#define H_DEFINE_AQP0 0x194
399#define H_RESIZE_MR 0x198
400#define H_ATTACH_MCQP 0x19C
401#define H_DETACH_MCQP 0x1A0
402#define H_CREATE_RPT 0x1A4
403#define H_REMOVE_RPT 0x1A8
404#define H_REGISTER_RPAGES 0x1AC
405#define H_DISABLE_AND_GETC 0x1B0
406#define H_ERROR_DATA 0x1B4
407#define H_GET_HCA_INFO 0x1B8
408#define H_GET_PERF_COUNT 0x1BC
409#define H_MANAGE_TRACE 0x1C0
410#define H_GET_CPU_CHARACTERISTICS 0x1C8
411#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
412#define H_QUERY_INT_STATE 0x1E4
413#define H_POLL_PENDING 0x1D8
414#define H_ILLAN_ATTRIBUTES 0x244
415#define H_MODIFY_HEA_QP 0x250
416#define H_QUERY_HEA_QP 0x254
417#define H_QUERY_HEA 0x258
418#define H_QUERY_HEA_PORT 0x25C
419#define H_MODIFY_HEA_PORT 0x260
420#define H_REG_BCMC 0x264
421#define H_DEREG_BCMC 0x268
422#define H_REGISTER_HEA_RPAGES 0x26C
423#define H_DISABLE_AND_GET_HEA 0x270
424#define H_GET_HEA_INFO 0x274
425#define H_ALLOC_HEA_RESOURCE 0x278
426#define H_ADD_CONN 0x284
427#define H_DEL_CONN 0x288
428#define H_JOIN 0x298
429#define H_VASI_STATE 0x2A4
430#define H_ENABLE_CRQ 0x2B0
431#define H_GET_EM_PARMS 0x2B8
432#define H_SET_MPP 0x2D0
433#define H_GET_MPP 0x2D4
434#define H_XIRR_X 0x2FC
435#define H_RANDOM 0x300
436#define H_SET_MODE 0x31C
437#define H_RESIZE_HPT_PREPARE 0x36C
438#define H_RESIZE_HPT_COMMIT 0x370
439#define H_CLEAN_SLB 0x374
440#define H_INVALIDATE_PID 0x378
441#define H_REGISTER_PROC_TBL 0x37C
442#define H_SIGNAL_SYS_RESET 0x380
443#define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET
444
445
446
447
448
449
450
451
452#define KVMPPC_HCALL_BASE 0xf000
453#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
454#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
455
456#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
457#define KVMPPC_HCALL_MAX KVMPPC_H_CAS
458
459typedef struct sPAPRDeviceTreeUpdateHeader {
460 uint32_t version_id;
461} sPAPRDeviceTreeUpdateHeader;
462
463#define hcall_dprintf(fmt, ...) \
464 do { \
465 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
466 } while (0)
467
468typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
469 target_ulong opcode,
470 target_ulong *args);
471
472void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
473target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
474 target_ulong *args);
475
476
477#define RTAS_EEH_DISABLE 0
478#define RTAS_EEH_ENABLE 1
479#define RTAS_EEH_THAW_IO 2
480#define RTAS_EEH_THAW_DMA 3
481
482
483#define RTAS_GET_PE_ADDR 0
484#define RTAS_GET_PE_MODE 1
485#define RTAS_PE_MODE_NONE 0
486#define RTAS_PE_MODE_NOT_SHARED 1
487#define RTAS_PE_MODE_SHARED 2
488
489
490#define RTAS_EEH_PE_STATE_NORMAL 0
491#define RTAS_EEH_PE_STATE_RESET 1
492#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
493#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
494#define RTAS_EEH_PE_STATE_UNAVAIL 5
495#define RTAS_EEH_NOT_SUPPORT 0
496#define RTAS_EEH_SUPPORT 1
497#define RTAS_EEH_PE_UNAVAIL_INFO 1000
498#define RTAS_EEH_PE_RECOVER_INFO 0
499
500
501#define RTAS_SLOT_RESET_DEACTIVATE 0
502#define RTAS_SLOT_RESET_HOT 1
503#define RTAS_SLOT_RESET_FUNDAMENTAL 3
504
505
506#define RTAS_SLOT_TEMP_ERR_LOG 1
507#define RTAS_SLOT_PERM_ERR_LOG 2
508
509
510#define RTAS_OUT_SUCCESS 0
511#define RTAS_OUT_NO_ERRORS_FOUND 1
512#define RTAS_OUT_HW_ERROR -1
513#define RTAS_OUT_BUSY -2
514#define RTAS_OUT_PARAM_ERROR -3
515#define RTAS_OUT_NOT_SUPPORTED -3
516#define RTAS_OUT_NO_SUCH_INDICATOR -3
517#define RTAS_OUT_NOT_AUTHORIZED -9002
518#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
519
520
521#define RTAS_DDW_PGSIZE_4K 0x01
522#define RTAS_DDW_PGSIZE_64K 0x02
523#define RTAS_DDW_PGSIZE_16M 0x04
524#define RTAS_DDW_PGSIZE_32M 0x08
525#define RTAS_DDW_PGSIZE_64M 0x10
526#define RTAS_DDW_PGSIZE_128M 0x20
527#define RTAS_DDW_PGSIZE_256M 0x40
528#define RTAS_DDW_PGSIZE_16G 0x80
529
530
531#define RTAS_TOKEN_BASE 0x2000
532
533#define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
534#define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
535#define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
536#define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
537#define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
538#define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
539#define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
540#define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
541#define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
542#define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
543#define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
544#define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
545#define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
546#define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
547#define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
548#define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
549#define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
550#define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
551#define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
552#define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
553#define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
554#define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
555#define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
556#define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
557#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
558#define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
559#define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
560#define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
561#define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
562#define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
563#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
564#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
565#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
566#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
567#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
568#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
569#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
570#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
571#define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
572#define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
573#define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
574#define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
575
576#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A)
577
578
579#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
580#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
581#define RTAS_SYSPARM_UUID 48
582
583
584
585
586
587
588
589#define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
590#define RTAS_SENSOR_TYPE_DR 9002
591#define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
592#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
593
594
595
596
597#define DIAGNOSTICS_RUN_MODE_DISABLED 0
598#define DIAGNOSTICS_RUN_MODE_STAGGERED 1
599#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
600#define DIAGNOSTICS_RUN_MODE_PERIODIC 3
601
602static inline uint64_t ppc64_phys_to_real(uint64_t addr)
603{
604 return addr & ~0xF000000000000000ULL;
605}
606
607static inline uint32_t rtas_ld(target_ulong phys, int n)
608{
609 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
610}
611
612static inline uint64_t rtas_ldq(target_ulong phys, int n)
613{
614 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
615}
616
617static inline void rtas_st(target_ulong phys, int n, uint32_t val)
618{
619 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
620}
621
622typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
623 uint32_t token,
624 uint32_t nargs, target_ulong args,
625 uint32_t nret, target_ulong rets);
626void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
627target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
628 uint32_t token, uint32_t nargs, target_ulong args,
629 uint32_t nret, target_ulong rets);
630void spapr_dt_rtas_tokens(void *fdt, int rtas);
631void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
632
633#define SPAPR_TCE_PAGE_SHIFT 12
634#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
635#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
636
637#define SPAPR_VIO_BASE_LIOBN 0x00000000
638#define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
639#define SPAPR_PCI_LIOBN(phb_index, window_num) \
640 (0x80000000 | ((phb_index) << 8) | (window_num))
641#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
642#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
643
644#define RTAS_ERROR_LOG_MAX 2048
645
646#define RTAS_EVENT_SCAN_RATE 1
647
648
649
650
651
652static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi)
653{
654 intspec[0] = cpu_to_be32(irq);
655 intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
656}
657
658typedef struct sPAPRTCETable sPAPRTCETable;
659
660#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
661#define SPAPR_TCE_TABLE(obj) \
662 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
663
664#define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
665#define SPAPR_IOMMU_MEMORY_REGION(obj) \
666 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
667
668struct sPAPRTCETable {
669 DeviceState parent;
670 uint32_t liobn;
671 uint32_t nb_table;
672 uint64_t bus_offset;
673 uint32_t page_shift;
674 uint64_t *table;
675 uint32_t mig_nb_table;
676 uint64_t *mig_table;
677 bool bypass;
678 bool need_vfio;
679 int fd;
680 MemoryRegion root;
681 IOMMUMemoryRegion iommu;
682 struct VIOsPAPRDevice *vdev;
683 QLIST_ENTRY(sPAPRTCETable) list;
684};
685
686sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
687
688struct sPAPREventLogEntry {
689 uint32_t summary;
690 uint32_t extended_length;
691 void *extended_log;
692 QTAILQ_ENTRY(sPAPREventLogEntry) next;
693};
694
695void spapr_events_init(sPAPRMachineState *sm);
696void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
697int spapr_h_cas_compose_response(sPAPRMachineState *sm,
698 target_ulong addr, target_ulong size,
699 sPAPROptionVector *ov5_updates);
700void close_htab_fd(sPAPRMachineState *spapr);
701void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr);
702void spapr_free_hpt(sPAPRMachineState *spapr);
703sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
704void spapr_tce_table_enable(sPAPRTCETable *tcet,
705 uint32_t page_shift, uint64_t bus_offset,
706 uint32_t nb_table);
707void spapr_tce_table_disable(sPAPRTCETable *tcet);
708void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
709
710MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
711int spapr_dma_dt(void *fdt, int node_off, const char *propname,
712 uint32_t liobn, uint64_t window, uint32_t size);
713int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
714 sPAPRTCETable *tcet);
715void spapr_pci_switch_vga(bool big_endian);
716void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
717void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
718void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
719 uint32_t count);
720void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
721 uint32_t count);
722void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
723 uint32_t count, uint32_t index);
724void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
725 uint32_t count, uint32_t index);
726int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
727void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
728 Error **errp);
729void spapr_clear_pending_events(sPAPRMachineState *spapr);
730
731
732void spapr_core_release(DeviceState *dev);
733void spapr_lmb_release(DeviceState *dev);
734
735void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
736int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
737
738#define TYPE_SPAPR_RNG "spapr-rng"
739
740int spapr_rng_populate_dt(void *fdt);
741
742#define SPAPR_MEMORY_BLOCK_SIZE (1 << 28)
743
744
745
746
747
748
749#define SPAPR_MAX_RAM_SLOTS 32
750
751
752#define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
753
754
755
756
757
758#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
759
760
761
762
763
764#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
765#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
766#define SPAPR_LMB_FLAGS_RESERVED 0x00000080
767
768void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
769
770#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
771
772int spapr_get_vcpu_id(PowerPCCPU *cpu);
773void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
774PowerPCCPU *spapr_find_cpu(int vcpu_id);
775
776int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
777 Error **errp);
778int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
779 bool align, Error **errp);
780void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
781qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
782
783
784int spapr_caps_pre_load(void *opaque);
785int spapr_caps_pre_save(void *opaque);
786
787
788
789
790extern const VMStateDescription vmstate_spapr_cap_htm;
791extern const VMStateDescription vmstate_spapr_cap_vsx;
792extern const VMStateDescription vmstate_spapr_cap_dfp;
793extern const VMStateDescription vmstate_spapr_cap_cfpc;
794extern const VMStateDescription vmstate_spapr_cap_sbbc;
795extern const VMStateDescription vmstate_spapr_cap_ibs;
796
797static inline uint8_t spapr_get_cap(sPAPRMachineState *spapr, int cap)
798{
799 return spapr->eff.caps[cap];
800}
801
802void spapr_caps_reset(sPAPRMachineState *spapr);
803void spapr_caps_add_properties(sPAPRMachineClass *smc, Error **errp);
804int spapr_caps_post_migration(sPAPRMachineState *spapr);
805
806#endif
807