LXR qemu/include/hw/ssi/xilinx

   1/*
   2 * Header file for the Xilinx Zynq SPI controller
   3 *
   4 * Copyright (C) 2015 Xilinx Inc
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef XILINX_SPIPS_H
  26#define XILINX_SPIPS_H
  27
  28#include "hw/ssi/ssi.h"
  29#include "qemu/fifo32.h"
  30#include "hw/stream.h"
  31
  32typedef struct XilinxSPIPS XilinxSPIPS;
  33
  34#define XLNX_SPIPS_R_MAX        (0x100 / 4)
  35#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4)
  36
  37/* Bite off 4k chunks at a time */
  38#define LQSPI_CACHE_SIZE 1024
  39
  40typedef enum {
  41    READ = 0x3,         READ_4 = 0x13,
  42    FAST_READ = 0xb,    FAST_READ_4 = 0x0c,
  43    DOR = 0x3b,         DOR_4 = 0x3c,
  44    QOR = 0x6b,         QOR_4 = 0x6c,
  45    DIOR = 0xbb,        DIOR_4 = 0xbc,
  46    QIOR = 0xeb,        QIOR_4 = 0xec,
  47
  48    PP = 0x2,           PP_4 = 0x12,
  49    DPP = 0xa2,
  50    QPP = 0x32,         QPP_4 = 0x34,
  51} FlashCMD;
  52
  53struct XilinxSPIPS {
  54    SysBusDevice parent_obj;
  55
  56    MemoryRegion iomem;
  57    MemoryRegion mmlqspi;
  58
  59    qemu_irq irq;
  60    int irqline;
  61
  62    uint8_t num_cs;
  63    uint8_t num_busses;
  64
  65    uint8_t snoop_state;
  66    int cmd_dummies;
  67    uint8_t link_state;
  68    uint8_t link_state_next;
  69    uint8_t link_state_next_when;
  70    qemu_irq *cs_lines;
  71    bool *cs_lines_state;
  72    SSIBus **spi;
  73
  74    Fifo8 rx_fifo;
  75    Fifo8 tx_fifo;
  76
  77    uint8_t num_txrx_bytes;
  78    uint32_t rx_discard;
  79
  80    uint32_t regs[XLNX_SPIPS_R_MAX];
  81
  82    bool man_start_com;
  83};
  84
  85typedef struct {
  86    XilinxSPIPS parent_obj;
  87
  88    uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
  89    hwaddr lqspi_cached_addr;
  90    Error *migration_blocker;
  91    bool mmio_execution_enabled;
  92} XilinxQSPIPS;
  93
  94typedef struct {
  95    XilinxQSPIPS parent_obj;
  96
  97    StreamSlave *dma;
  98    uint8_t dma_buf[4];
  99    int gqspi_irqline;
 100
 101    uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
 102
 103    /* GQSPI has seperate tx/rx fifos */
 104    Fifo8 rx_fifo_g;
 105    Fifo8 tx_fifo_g;
 106    Fifo32 fifo_g;
 107    /*
 108     * At the end of each generic command, misaligned extra bytes are discard
 109     * or padded to tx and rx respectively to round it out (and avoid need for
 110     * individual byte access. Since we use byte fifos, keep track of the
 111     * alignment WRT to word access.
 112     */
 113    uint8_t rx_fifo_g_align;
 114    uint8_t tx_fifo_g_align;
 115    bool man_start_com_g;
 116} XlnxZynqMPQSPIPS;
 117
 118typedef struct XilinxSPIPSClass {
 119    SysBusDeviceClass parent_class;
 120
 121    const MemoryRegionOps *reg_ops;
 122
 123    uint32_t rx_fifo_size;
 124    uint32_t tx_fifo_size;
 125} XilinxSPIPSClass;
 126
 127#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
 128#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
 129#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi"
 130
 131#define XILINX_SPIPS(obj) \
 132     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
 133#define XILINX_SPIPS_CLASS(klass) \
 134     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
 135#define XILINX_SPIPS_GET_CLASS(obj) \
 136     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
 137
 138#define XILINX_QSPIPS(obj) \
 139     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
 140
 141#define XLNX_ZYNQMP_QSPIPS(obj) \
 142     OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS)
 143
 144#endif /* XILINX_SPIPS_H */
 145