1/* 2 * QEMU CPU model 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20#ifndef QEMU_CPU_H 21#define QEMU_CPU_H 22 23#include "hw/qdev-core.h" 24#include "disas/bfd.h" 25#include "exec/hwaddr.h" 26#include "exec/memattrs.h" 27#include "qapi/qapi-types-run-state.h" 28#include "qemu/bitmap.h" 29#include "qemu/queue.h" 30#include "qemu/thread.h" 31 32typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, 33 void *opaque); 34 35/** 36 * vaddr: 37 * Type wide enough to contain any #target_ulong virtual address. 38 */ 39typedef uint64_t vaddr; 40#define VADDR_PRId PRId64 41#define VADDR_PRIu PRIu64 42#define VADDR_PRIo PRIo64 43#define VADDR_PRIx PRIx64 44#define VADDR_PRIX PRIX64 45#define VADDR_MAX UINT64_MAX 46 47/** 48 * SECTION:cpu 49 * @section_id: QEMU-cpu 50 * @title: CPU Class 51 * @short_description: Base class for all CPUs 52 */ 53 54#define TYPE_CPU "cpu" 55 56/* Since this macro is used a lot in hot code paths and in conjunction with 57 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using 58 * an unchecked cast. 59 */ 60#define CPU(obj) ((CPUState *)(obj)) 61 62#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) 63#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) 64 65typedef enum MMUAccessType { 66 MMU_DATA_LOAD = 0, 67 MMU_DATA_STORE = 1, 68 MMU_INST_FETCH = 2 69} MMUAccessType; 70 71typedef struct CPUWatchpoint CPUWatchpoint; 72 73typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, 74 bool is_write, bool is_exec, int opaque, 75 unsigned size); 76 77struct TranslationBlock; 78 79/** 80 * CPUClass: 81 * @class_by_name: Callback to map -cpu command line model name to an 82 * instantiatable CPU type. 83 * @parse_features: Callback to parse command line arguments. 84 * @reset: Callback to reset the #CPUState to its initial state. 85 * @reset_dump_flags: #CPUDumpFlags to use for reset logging. 86 * @has_work: Callback for checking if there is work to do. 87 * @do_interrupt: Callback for interrupt handling. 88 * @do_unassigned_access: Callback for unassigned access handling. 89 * (this is deprecated: new targets should use do_transaction_failed instead) 90 * @do_unaligned_access: Callback for unaligned access handling, if 91 * the target defines #ALIGNED_ONLY. 92 * @do_transaction_failed: Callback for handling failed memory transactions 93 * (ie bus faults or external aborts; not MMU faults) 94 * @virtio_is_big_endian: Callback to return %true if a CPU which supports 95 * runtime configurable endianness is currently big-endian. Non-configurable 96 * CPUs can use the default implementation of this method. This method should 97 * not be used by any callers other than the pre-1.0 virtio devices. 98 * @memory_rw_debug: Callback for GDB memory access. 99 * @dump_state: Callback for dumping state. 100 * @dump_statistics: Callback for dumping statistics. 101 * @get_arch_id: Callback for getting architecture-dependent CPU ID. 102 * @get_paging_enabled: Callback for inquiring whether paging is enabled. 103 * @get_memory_mapping: Callback for obtaining the memory mappings. 104 * @set_pc: Callback for setting the Program Counter register. 105 * @synchronize_from_tb: Callback for synchronizing state from a TCG 106 * #TranslationBlock. 107 * @handle_mmu_fault: Callback for handling an MMU fault. 108 * @get_phys_page_debug: Callback for obtaining a physical address. 109 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the 110 * associated memory transaction attributes to use for the access. 111 * CPUs which use memory transaction attributes should implement this 112 * instead of get_phys_page_debug. 113 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for 114 * a memory access with the specified memory transaction attributes. 115 * @gdb_read_register: Callback for letting GDB read a register. 116 * @gdb_write_register: Callback for letting GDB write a register. 117 * @debug_check_watchpoint: Callback: return true if the architectural 118 * watchpoint whose address has matched should really fire. 119 * @debug_excp_handler: Callback for handling debug exceptions. 120 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a 121 * 64-bit VM coredump. 122 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF 123 * note to a 32-bit VM coredump. 124 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a 125 * 32-bit VM coredump. 126 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF 127 * note to a 32-bit VM coredump. 128 * @vmsd: State description for migration. 129 * @gdb_num_core_regs: Number of core registers accessible to GDB. 130 * @gdb_core_xml_file: File name for core registers GDB XML description. 131 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop 132 * before the insn which triggers a watchpoint rather than after it. 133 * @gdb_arch_name: Optional callback that returns the architecture name known 134 * to GDB. The caller must free the returned string with g_free. 135 * @cpu_exec_enter: Callback for cpu_exec preparation. 136 * @cpu_exec_exit: Callback for cpu_exec cleanup. 137 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. 138 * @disas_set_info: Setup architecture specific components of disassembly info 139 * @adjust_watchpoint_address: Perform a target-specific adjustment to an 140 * address before attempting to match it against watchpoints. 141 * 142 * Represents a CPU family or model. 143 */ 144typedef struct CPUClass { 145 /*< private >*/ 146 DeviceClass parent_class; 147 /*< public >*/ 148 149 ObjectClass *(*class_by_name)(const char *cpu_model); 150 void (*parse_features)(const char *typename, char *str, Error **errp); 151 152 void (*reset)(CPUState *cpu); 153 int reset_dump_flags; 154 bool (*has_work)(CPUState *cpu); 155 void (*do_interrupt)(CPUState *cpu); 156 CPUUnassignedAccess do_unassigned_access; 157 void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 158 MMUAccessType access_type, 159 int mmu_idx, uintptr_t retaddr); 160 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 161 unsigned size, MMUAccessType access_type, 162 int mmu_idx, MemTxAttrs attrs, 163 MemTxResult response, uintptr_t retaddr); 164 bool (*virtio_is_big_endian)(CPUState *cpu); 165 int (*memory_rw_debug)(CPUState *cpu, vaddr addr, 166 uint8_t *buf, int len, bool is_write); 167 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 168 int flags); 169 GuestPanicInformation* (*get_crash_info)(CPUState *cpu); 170 void (*dump_statistics)(CPUState *cpu, FILE *f, 171 fprintf_function cpu_fprintf, int flags); 172 int64_t (*get_arch_id)(CPUState *cpu); 173 bool (*get_paging_enabled)(const CPUState *cpu); 174 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, 175 Error **errp); 176 void (*set_pc)(CPUState *cpu, vaddr value); 177 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); 178 int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int size, int rw, 179 int mmu_index); 180 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); 181 hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, 182 MemTxAttrs *attrs); 183 int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); 184 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); 185 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); 186 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 187 void (*debug_excp_handler)(CPUState *cpu); 188 189 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, 190 int cpuid, void *opaque); 191 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, 192 void *opaque); 193 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, 194 int cpuid, void *opaque); 195 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, 196 void *opaque); 197 198 const struct VMStateDescription *vmsd; 199 const char *gdb_core_xml_file; 200 gchar * (*gdb_arch_name)(CPUState *cpu); 201 202 void (*cpu_exec_enter)(CPUState *cpu); 203 void (*cpu_exec_exit)(CPUState *cpu); 204 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 205 206 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); 207 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 208 void (*tcg_initialize)(void); 209 210 /* Keep non-pointer data at the end to minimize holes. */ 211 int gdb_num_core_regs; 212 bool gdb_stop_before_watchpoint; 213} CPUClass; 214 215#ifdef HOST_WORDS_BIGENDIAN 216typedef struct icount_decr_u16 { 217 uint16_t high; 218 uint16_t low; 219} icount_decr_u16; 220#else 221typedef struct icount_decr_u16 { 222 uint16_t low; 223 uint16_t high; 224} icount_decr_u16; 225#endif 226 227typedef struct CPUBreakpoint { 228 vaddr pc; 229 int flags; /* BP_* */ 230 QTAILQ_ENTRY(CPUBreakpoint) entry; 231} CPUBreakpoint; 232 233struct CPUWatchpoint { 234 vaddr vaddr; 235 vaddr len; 236 vaddr hitaddr; 237 MemTxAttrs hitattrs; 238 int flags; /* BP_* */ 239 QTAILQ_ENTRY(CPUWatchpoint) entry; 240}; 241 242struct KVMState; 243struct kvm_run; 244 245struct hax_vcpu_state; 246 247#define TB_JMP_CACHE_BITS 12 248#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) 249 250/* work queue */ 251 252/* The union type allows passing of 64 bit target pointers on 32 bit 253 * hosts in a single parameter 254 */ 255typedef union { 256 int host_int; 257 unsigned long host_ulong; 258 void *host_ptr; 259 vaddr target_ptr; 260} run_on_cpu_data; 261 262#define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) 263#define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) 264#define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) 265#define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) 266#define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) 267 268typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); 269 270struct qemu_work_item; 271 272#define CPU_UNSET_NUMA_NODE_ID -1 273#define CPU_TRACE_DSTATE_MAX_EVENTS 32 274 275/** 276 * CPUState: 277 * @cpu_index: CPU index (informative). 278 * @nr_cores: Number of cores within this CPU package. 279 * @nr_threads: Number of threads within this CPU. 280 * @running: #true if CPU is currently running (lockless). 281 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; 282 * valid under cpu_list_lock. 283 * @created: Indicates whether the CPU thread has been successfully created. 284 * @interrupt_request: Indicates a pending interrupt request. 285 * @halted: Nonzero if the CPU is in suspended state. 286 * @stop: Indicates a pending stop request. 287 * @stopped: Indicates the CPU has been artificially stopped. 288 * @unplug: Indicates a pending CPU unplug request. 289 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU 290 * @singlestep_enabled: Flags for single-stepping. 291 * @icount_extra: Instructions until next timer event. 292 * @icount_decr: Low 16 bits: number of cycles left, only used in icount mode. 293 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs for this 294 * CPU and return to its top level loop (even in non-icount mode). 295 * This allows a single read-compare-cbranch-write sequence to test 296 * for both decrementer underflow and exceptions. 297 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution 298 * requires that IO only be performed on the last instruction of a TB 299 * so that interrupts take effect immediately. 300 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the 301 * AddressSpaces this CPU has) 302 * @num_ases: number of CPUAddressSpaces in @cpu_ases 303 * @as: Pointer to the first AddressSpace, for the convenience of targets which 304 * only have a single AddressSpace 305 * @env_ptr: Pointer to subclass-specific CPUArchState field. 306 * @gdb_regs: Additional GDB registers. 307 * @gdb_num_regs: Number of total registers accessible to GDB. 308 * @gdb_num_g_regs: Number of registers in GDB 'g' packets. 309 * @next_cpu: Next CPU sharing TB cache. 310 * @opaque: User data. 311 * @mem_io_pc: Host Program Counter at which the memory was accessed. 312 * @mem_io_vaddr: Target virtual address at which the memory was accessed. 313 * @kvm_fd: vCPU file descriptor for KVM. 314 * @work_mutex: Lock to prevent multiple access to queued_work_*. 315 * @queued_work_first: First asynchronous work pending. 316 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes 317 * to @trace_dstate). 318 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). 319 * @ignore_memory_transaction_failures: Cached copy of the MachineState 320 * flag of the same name: allows the board to suppress calling of the 321 * CPU do_transaction_failed hook function. 322 * 323 * State of one CPU core or thread. 324 */ 325struct CPUState { 326 /*< private >*/ 327 DeviceState parent_obj; 328 /*< public >*/ 329 330 int nr_cores; 331 int nr_threads; 332 333 struct QemuThread *thread; 334#ifdef _WIN32 335 HANDLE hThread; 336#endif 337 int thread_id; 338 bool running, has_waiter; 339 struct QemuCond *halt_cond; 340 bool thread_kicked; 341 bool created; 342 bool stop; 343 bool stopped; 344 bool unplug; 345 bool crash_occurred; 346 bool exit_request; 347 uint32_t cflags_next_tb; 348 /* updates protected by BQL */ 349 uint32_t interrupt_request; 350 int singlestep_enabled; 351 int64_t icount_budget; 352 int64_t icount_extra; 353 sigjmp_buf jmp_env; 354 355 QemuMutex work_mutex; 356 struct qemu_work_item *queued_work_first, *queued_work_last; 357 358 CPUAddressSpace *cpu_ases; 359 int num_ases; 360 AddressSpace *as; 361 MemoryRegion *memory; 362 363 void *env_ptr; /* CPUArchState */ 364 365 /* Accessed in parallel; all accesses must be atomic */ 366 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; 367 368 struct GDBRegisterState *gdb_regs; 369 int gdb_num_regs; 370 int gdb_num_g_regs; 371 QTAILQ_ENTRY(CPUState) node; 372 373 /* ice debug support */ 374 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; 375 376 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; 377 CPUWatchpoint *watchpoint_hit; 378 379 void *opaque; 380 381 /* In order to avoid passing too many arguments to the MMIO helpers, 382 * we store some rarely used information in the CPU context. 383 */ 384 uintptr_t mem_io_pc; 385 vaddr mem_io_vaddr; 386 387 int kvm_fd; 388 struct KVMState *kvm_state; 389 struct kvm_run *kvm_run; 390 391 /* Used for events with 'vcpu' and *without* the 'disabled' properties */ 392 DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS); 393 DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS); 394 395 /* TODO Move common fields from CPUArchState here. */ 396 int cpu_index; 397 uint32_t halted; 398 uint32_t can_do_io; 399 int32_t exception_index; 400 401 /* shared by kvm, hax and hvf */ 402 bool vcpu_dirty; 403 404 /* Used to keep track of an outstanding cpu throttle thread for migration 405 * autoconverge 406 */ 407 bool throttle_thread_scheduled; 408 409 bool ignore_memory_transaction_failures; 410 411 /* Note that this is accessed at the start of every TB via a negative 412 offset from AREG0. Leave this field at the end so as to make the 413 (absolute value) offset as small as possible. This reduces code 414 size, especially for hosts without large memory offsets. */ 415 union { 416 uint32_t u32; 417 icount_decr_u16 u16; 418 } icount_decr; 419 420 struct hax_vcpu_state *hax_vcpu; 421 422 /* The pending_tlb_flush flag is set and cleared atomically to 423 * avoid potential races. The aim of the flag is to avoid 424 * unnecessary flushes. 425 */ 426 uint16_t pending_tlb_flush; 427 428 int hvf_fd; 429}; 430 431QTAILQ_HEAD(CPUTailQ, CPUState); 432extern struct CPUTailQ cpus; 433#define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) 434#define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) 435#define CPU_FOREACH_SAFE(cpu, next_cpu) \ 436 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) 437#define CPU_FOREACH_REVERSE(cpu) \ 438 QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node) 439#define first_cpu QTAILQ_FIRST(&cpus) 440 441extern __thread CPUState *current_cpu; 442 443static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) 444{ 445 unsigned int i; 446 447 for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { 448 atomic_set(&cpu->tb_jmp_cache[i], NULL); 449 } 450} 451 452/** 453 * qemu_tcg_mttcg_enabled: 454 * Check whether we are running MultiThread TCG or not. 455 * 456 * Returns: %true if we are in MTTCG mode %false otherwise. 457 */ 458extern bool mttcg_enabled; 459#define qemu_tcg_mttcg_enabled() (mttcg_enabled) 460 461/** 462 * cpu_paging_enabled: 463 * @cpu: The CPU whose state is to be inspected. 464 * 465 * Returns: %true if paging is enabled, %false otherwise. 466 */ 467bool cpu_paging_enabled(const CPUState *cpu); 468 469/** 470 * cpu_get_memory_mapping: 471 * @cpu: The CPU whose memory mappings are to be obtained. 472 * @list: Where to write the memory mappings to. 473 * @errp: Pointer for reporting an #Error. 474 */ 475void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 476 Error **errp); 477 478/** 479 * cpu_write_elf64_note: 480 * @f: pointer to a function that writes memory to a file 481 * @cpu: The CPU whose memory is to be dumped 482 * @cpuid: ID number of the CPU 483 * @opaque: pointer to the CPUState struct 484 */ 485int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 486 int cpuid, void *opaque); 487 488/** 489 * cpu_write_elf64_qemunote: 490 * @f: pointer to a function that writes memory to a file 491 * @cpu: The CPU whose memory is to be dumped 492 * @cpuid: ID number of the CPU 493 * @opaque: pointer to the CPUState struct 494 */ 495int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 496 void *opaque); 497 498/** 499 * cpu_write_elf32_note: 500 * @f: pointer to a function that writes memory to a file 501 * @cpu: The CPU whose memory is to be dumped 502 * @cpuid: ID number of the CPU 503 * @opaque: pointer to the CPUState struct 504 */ 505int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 506 int cpuid, void *opaque); 507 508/** 509 * cpu_write_elf32_qemunote: 510 * @f: pointer to a function that writes memory to a file 511 * @cpu: The CPU whose memory is to be dumped 512 * @cpuid: ID number of the CPU 513 * @opaque: pointer to the CPUState struct 514 */ 515int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 516 void *opaque); 517 518/** 519 * cpu_get_crash_info: 520 * @cpu: The CPU to get crash information for 521 * 522 * Gets the previously saved crash information. 523 * Caller is responsible for freeing the data. 524 */ 525GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); 526 527/** 528 * CPUDumpFlags: 529 * @CPU_DUMP_CODE: 530 * @CPU_DUMP_FPU: dump FPU register state, not just integer 531 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state 532 */ 533enum CPUDumpFlags { 534 CPU_DUMP_CODE = 0x00010000, 535 CPU_DUMP_FPU = 0x00020000, 536 CPU_DUMP_CCOP = 0x00040000, 537}; 538 539/** 540 * cpu_dump_state: 541 * @cpu: The CPU whose state is to be dumped. 542 * @f: File to dump to. 543 * @cpu_fprintf: Function to dump with. 544 * @flags: Flags what to dump. 545 * 546 * Dumps CPU state. 547 */ 548void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 549 int flags); 550 551/** 552 * cpu_dump_statistics: 553 * @cpu: The CPU whose state is to be dumped. 554 * @f: File to dump to. 555 * @cpu_fprintf: Function to dump with. 556 * @flags: Flags what to dump. 557 * 558 * Dumps CPU statistics. 559 */ 560void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 561 int flags); 562 563#ifndef CONFIG_USER_ONLY 564/** 565 * cpu_get_phys_page_attrs_debug: 566 * @cpu: The CPU to obtain the physical page address for. 567 * @addr: The virtual address. 568 * @attrs: Updated on return with the memory transaction attributes to use 569 * for this access. 570 * 571 * Obtains the physical page corresponding to a virtual one, together 572 * with the corresponding memory transaction attributes to use for the access. 573 * Use it only for debugging because no protection checks are done. 574 * 575 * Returns: Corresponding physical page address or -1 if no page found. 576 */ 577static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 578 MemTxAttrs *attrs) 579{ 580 CPUClass *cc = CPU_GET_CLASS(cpu); 581 582 if (cc->get_phys_page_attrs_debug) { 583 return cc->get_phys_page_attrs_debug(cpu, addr, attrs); 584 } 585 /* Fallback for CPUs which don't implement the _attrs_ hook */ 586 *attrs = MEMTXATTRS_UNSPECIFIED; 587 return cc->get_phys_page_debug(cpu, addr); 588} 589 590/** 591 * cpu_get_phys_page_debug: 592 * @cpu: The CPU to obtain the physical page address for. 593 * @addr: The virtual address. 594 * 595 * Obtains the physical page corresponding to a virtual one. 596 * Use it only for debugging because no protection checks are done. 597 * 598 * Returns: Corresponding physical page address or -1 if no page found. 599 */ 600static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) 601{ 602 MemTxAttrs attrs = {}; 603 604 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); 605} 606 607/** cpu_asidx_from_attrs: 608 * @cpu: CPU 609 * @attrs: memory transaction attributes 610 * 611 * Returns the address space index specifying the CPU AddressSpace 612 * to use for a memory access with the given transaction attributes. 613 */ 614static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) 615{ 616 CPUClass *cc = CPU_GET_CLASS(cpu); 617 618 if (cc->asidx_from_attrs) { 619 return cc->asidx_from_attrs(cpu, attrs); 620 } 621 return 0; 622} 623#endif 624 625/** 626 * cpu_list_add: 627 * @cpu: The CPU to be added to the list of CPUs. 628 */ 629void cpu_list_add(CPUState *cpu); 630 631/** 632 * cpu_list_remove: 633 * @cpu: The CPU to be removed from the list of CPUs. 634 */ 635void cpu_list_remove(CPUState *cpu); 636 637/** 638 * cpu_reset: 639 * @cpu: The CPU whose state is to be reset. 640 */ 641void cpu_reset(CPUState *cpu); 642 643/** 644 * cpu_class_by_name: 645 * @typename: The CPU base type. 646 * @cpu_model: The model string without any parameters. 647 * 648 * Looks up a CPU #ObjectClass matching name @cpu_model. 649 * 650 * Returns: A #CPUClass or %NULL if not matching class is found. 651 */ 652ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); 653 654/** 655 * cpu_create: 656 * @typename: The CPU type. 657 * 658 * Instantiates a CPU and realizes the CPU. 659 * 660 * Returns: A #CPUState or %NULL if an error occurred. 661 */ 662CPUState *cpu_create(const char *typename); 663 664/** 665 * parse_cpu_model: 666 * @cpu_model: The model string including optional parameters. 667 * 668 * processes optional parameters and registers them as global properties 669 * 670 * Returns: type of CPU to create or prints error and terminates process 671 * if an error occurred. 672 */ 673const char *parse_cpu_model(const char *cpu_model); 674 675/** 676 * cpu_has_work: 677 * @cpu: The vCPU to check. 678 * 679 * Checks whether the CPU has work to do. 680 * 681 * Returns: %true if the CPU has work, %false otherwise. 682 */ 683static inline bool cpu_has_work(CPUState *cpu) 684{ 685 CPUClass *cc = CPU_GET_CLASS(cpu); 686 687 g_assert(cc->has_work); 688 return cc->has_work(cpu); 689} 690 691/** 692 * qemu_cpu_is_self: 693 * @cpu: The vCPU to check against. 694 * 695 * Checks whether the caller is executing on the vCPU thread. 696 * 697 * Returns: %true if called from @cpu's thread, %false otherwise. 698 */ 699bool qemu_cpu_is_self(CPUState *cpu); 700 701/** 702 * qemu_cpu_kick: 703 * @cpu: The vCPU to kick. 704 * 705 * Kicks @cpu's thread. 706 */ 707void qemu_cpu_kick(CPUState *cpu); 708 709/** 710 * cpu_is_stopped: 711 * @cpu: The CPU to check. 712 * 713 * Checks whether the CPU is stopped. 714 * 715 * Returns: %true if run state is not running or if artificially stopped; 716 * %false otherwise. 717 */ 718bool cpu_is_stopped(CPUState *cpu); 719 720/** 721 * do_run_on_cpu: 722 * @cpu: The vCPU to run on. 723 * @func: The function to be executed. 724 * @data: Data to pass to the function. 725 * @mutex: Mutex to release while waiting for @func to run. 726 * 727 * Used internally in the implementation of run_on_cpu. 728 */ 729void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, 730 QemuMutex *mutex); 731 732/** 733 * run_on_cpu: 734 * @cpu: The vCPU to run on. 735 * @func: The function to be executed. 736 * @data: Data to pass to the function. 737 * 738 * Schedules the function @func for execution on the vCPU @cpu. 739 */ 740void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 741 742/** 743 * async_run_on_cpu: 744 * @cpu: The vCPU to run on. 745 * @func: The function to be executed. 746 * @data: Data to pass to the function. 747 * 748 * Schedules the function @func for execution on the vCPU @cpu asynchronously. 749 */ 750void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 751 752/** 753 * async_safe_run_on_cpu: 754 * @cpu: The vCPU to run on. 755 * @func: The function to be executed. 756 * @data: Data to pass to the function. 757 * 758 * Schedules the function @func for execution on the vCPU @cpu asynchronously, 759 * while all other vCPUs are sleeping. 760 * 761 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the 762 * BQL. 763 */ 764void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 765 766/** 767 * qemu_get_cpu: 768 * @index: The CPUState@cpu_index value of the CPU to obtain. 769 * 770 * Gets a CPU matching @index. 771 * 772 * Returns: The CPU or %NULL if there is no matching CPU. 773 */ 774CPUState *qemu_get_cpu(int index); 775 776/** 777 * cpu_exists: 778 * @id: Guest-exposed CPU ID to lookup. 779 * 780 * Search for CPU with specified ID. 781 * 782 * Returns: %true - CPU is found, %false - CPU isn't found. 783 */ 784bool cpu_exists(int64_t id); 785 786/** 787 * cpu_by_arch_id: 788 * @id: Guest-exposed CPU ID of the CPU to obtain. 789 * 790 * Get a CPU with matching @id. 791 * 792 * Returns: The CPU or %NULL if there is no matching CPU. 793 */ 794CPUState *cpu_by_arch_id(int64_t id); 795 796/** 797 * cpu_throttle_set: 798 * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99. 799 * 800 * Throttles all vcpus by forcing them to sleep for the given percentage of 801 * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly. 802 * (example: 10ms sleep for every 30ms awake). 803 * 804 * cpu_throttle_set can be called as needed to adjust new_throttle_pct. 805 * Once the throttling starts, it will remain in effect until cpu_throttle_stop 806 * is called. 807 */ 808void cpu_throttle_set(int new_throttle_pct); 809 810/** 811 * cpu_throttle_stop: 812 * 813 * Stops the vcpu throttling started by cpu_throttle_set. 814 */ 815void cpu_throttle_stop(void); 816 817/** 818 * cpu_throttle_active: 819 * 820 * Returns: %true if the vcpus are currently being throttled, %false otherwise. 821 */ 822bool cpu_throttle_active(void); 823 824/** 825 * cpu_throttle_get_percentage: 826 * 827 * Returns the vcpu throttle percentage. See cpu_throttle_set for details. 828 * 829 * Returns: The throttle percentage in range 1 to 99. 830 */ 831int cpu_throttle_get_percentage(void); 832 833#ifndef CONFIG_USER_ONLY 834 835typedef void (*CPUInterruptHandler)(CPUState *, int); 836 837extern CPUInterruptHandler cpu_interrupt_handler; 838 839/** 840 * cpu_interrupt: 841 * @cpu: The CPU to set an interrupt on. 842 * @mask: The interupts to set. 843 * 844 * Invokes the interrupt handler. 845 */ 846static inline void cpu_interrupt(CPUState *cpu, int mask) 847{ 848 cpu_interrupt_handler(cpu, mask); 849} 850 851#else /* USER_ONLY */ 852 853void cpu_interrupt(CPUState *cpu, int mask); 854 855#endif /* USER_ONLY */ 856 857#ifdef NEED_CPU_H 858 859#ifdef CONFIG_SOFTMMU 860static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, 861 bool is_write, bool is_exec, 862 int opaque, unsigned size) 863{ 864 CPUClass *cc = CPU_GET_CLASS(cpu); 865 866 if (cc->do_unassigned_access) { 867 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); 868 } 869} 870 871static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, 872 MMUAccessType access_type, 873 int mmu_idx, uintptr_t retaddr) 874{ 875 CPUClass *cc = CPU_GET_CLASS(cpu); 876 877 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); 878} 879 880static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, 881 vaddr addr, unsigned size, 882 MMUAccessType access_type, 883 int mmu_idx, MemTxAttrs attrs, 884 MemTxResult response, 885 uintptr_t retaddr) 886{ 887 CPUClass *cc = CPU_GET_CLASS(cpu); 888 889 if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) { 890 cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, 891 mmu_idx, attrs, response, retaddr); 892 } 893} 894#endif 895 896#endif /* NEED_CPU_H */ 897 898/** 899 * cpu_set_pc: 900 * @cpu: The CPU to set the program counter for. 901 * @addr: Program counter value. 902 * 903 * Sets the program counter for a CPU. 904 */ 905static inline void cpu_set_pc(CPUState *cpu, vaddr addr) 906{ 907 CPUClass *cc = CPU_GET_CLASS(cpu); 908 909 cc->set_pc(cpu, addr); 910} 911 912/** 913 * cpu_reset_interrupt: 914 * @cpu: The CPU to clear the interrupt on. 915 * @mask: The interrupt mask to clear. 916 * 917 * Resets interrupts on the vCPU @cpu. 918 */ 919void cpu_reset_interrupt(CPUState *cpu, int mask); 920 921/** 922 * cpu_exit: 923 * @cpu: The CPU to exit. 924 * 925 * Requests the CPU @cpu to exit execution. 926 */ 927void cpu_exit(CPUState *cpu); 928 929/** 930 * cpu_resume: 931 * @cpu: The CPU to resume. 932 * 933 * Resumes CPU, i.e. puts CPU into runnable state. 934 */ 935void cpu_resume(CPUState *cpu); 936 937/** 938 * cpu_remove: 939 * @cpu: The CPU to remove. 940 * 941 * Requests the CPU to be removed. 942 */ 943void cpu_remove(CPUState *cpu); 944 945 /** 946 * cpu_remove_sync: 947 * @cpu: The CPU to remove. 948 * 949 * Requests the CPU to be removed and waits till it is removed. 950 */ 951void cpu_remove_sync(CPUState *cpu); 952 953/** 954 * process_queued_cpu_work() - process all items on CPU work queue 955 * @cpu: The CPU which work queue to process. 956 */ 957void process_queued_cpu_work(CPUState *cpu); 958 959/** 960 * cpu_exec_start: 961 * @cpu: The CPU for the current thread. 962 * 963 * Record that a CPU has started execution and can be interrupted with 964 * cpu_exit. 965 */ 966void cpu_exec_start(CPUState *cpu); 967 968/** 969 * cpu_exec_end: 970 * @cpu: The CPU for the current thread. 971 * 972 * Record that a CPU has stopped execution and exclusive sections 973 * can be executed without interrupting it. 974 */ 975void cpu_exec_end(CPUState *cpu); 976 977/** 978 * start_exclusive: 979 * 980 * Wait for a concurrent exclusive section to end, and then start 981 * a section of work that is run while other CPUs are not running 982 * between cpu_exec_start and cpu_exec_end. CPUs that are running 983 * cpu_exec are exited immediately. CPUs that call cpu_exec_start 984 * during the exclusive section go to sleep until this CPU calls 985 * end_exclusive. 986 */ 987void start_exclusive(void); 988 989/** 990 * end_exclusive: 991 * 992 * Concludes an exclusive execution section started by start_exclusive. 993 */ 994void end_exclusive(void); 995 996/** 997 * qemu_init_vcpu: 998 * @cpu: The vCPU to initialize. 999 * 1000 * Initializes a vCPU.
1001 */ 1002void qemu_init_vcpu(CPUState *cpu); 1003 1004#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ 1005#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ 1006#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ 1007 1008/** 1009 * cpu_single_step: 1010 * @cpu: CPU to the flags for. 1011 * @enabled: Flags to enable. 1012 * 1013 * Enables or disables single-stepping for @cpu. 1014 */ 1015void cpu_single_step(CPUState *cpu, int enabled); 1016 1017/* Breakpoint/watchpoint flags */ 1018#define BP_MEM_READ 0x01 1019#define BP_MEM_WRITE 0x02 1020#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) 1021#define BP_STOP_BEFORE_ACCESS 0x04 1022/* 0x08 currently unused */ 1023#define BP_GDB 0x10 1024#define BP_CPU 0x20 1025#define BP_ANY (BP_GDB | BP_CPU) 1026#define BP_WATCHPOINT_HIT_READ 0x40 1027#define BP_WATCHPOINT_HIT_WRITE 0x80 1028#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) 1029 1030int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, 1031 CPUBreakpoint **breakpoint); 1032int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); 1033void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); 1034void cpu_breakpoint_remove_all(CPUState *cpu, int mask); 1035 1036/* Return true if PC matches an installed breakpoint. */ 1037static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) 1038{ 1039 CPUBreakpoint *bp; 1040 1041 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { 1042 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 1043 if (bp->pc == pc && (bp->flags & mask)) { 1044 return true; 1045 } 1046 } 1047 } 1048 return false; 1049} 1050 1051int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 1052 int flags, CPUWatchpoint **watchpoint); 1053int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, 1054 vaddr len, int flags); 1055void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); 1056void cpu_watchpoint_remove_all(CPUState *cpu, int mask); 1057 1058/** 1059 * cpu_get_address_space: 1060 * @cpu: CPU to get address space from 1061 * @asidx: index identifying which address space to get 1062 * 1063 * Return the requested address space of this CPU. @asidx 1064 * specifies which address space to read. 1065 */ 1066AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); 1067 1068void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) 1069 GCC_FMT_ATTR(2, 3); 1070extern Property cpu_common_props[]; 1071void cpu_exec_initfn(CPUState *cpu); 1072void cpu_exec_realizefn(CPUState *cpu, Error **errp); 1073void cpu_exec_unrealizefn(CPUState *cpu); 1074 1075#ifdef NEED_CPU_H 1076 1077#ifdef CONFIG_SOFTMMU 1078extern const struct VMStateDescription vmstate_cpu_common; 1079#else 1080#define vmstate_cpu_common vmstate_dummy 1081#endif 1082 1083#define VMSTATE_CPU() { \ 1084 .name = "parent_obj", \ 1085 .size = sizeof(CPUState), \ 1086 .vmsd = &vmstate_cpu_common, \ 1087 .flags = VMS_STRUCT, \ 1088 .offset = 0, \ 1089} 1090 1091#endif /* NEED_CPU_H */ 1092 1093#define UNASSIGNED_CPU_INDEX -1 1094 1095#endif 1096