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20#ifndef QEMU_ARM_CPU_QOM_H
21#define QEMU_ARM_CPU_QOM_H
22
23#include "qom/cpu.h"
24
25struct arm_boot_info;
26
27#define TYPE_ARM_CPU "arm-cpu"
28
29#define ARM_CPU_CLASS(klass) \
30 OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
31#define ARM_CPU(obj) \
32 OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
33#define ARM_CPU_GET_CLASS(obj) \
34 OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
35
36#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
37
38
39
40
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42
43
44
45typedef struct ARMCPUClass {
46
47 CPUClass parent_class;
48
49
50 DeviceRealize parent_realize;
51 void (*parent_reset)(CPUState *cpu);
52} ARMCPUClass;
53
54typedef struct ARMCPU ARMCPU;
55
56#define TYPE_AARCH64_CPU "aarch64-cpu"
57#define AARCH64_CPU_CLASS(klass) \
58 OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
59#define AARCH64_CPU_GET_CLASS(obj) \
60 OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
61
62typedef struct AArch64CPUClass {
63
64 ARMCPUClass parent_class;
65
66} AArch64CPUClass;
67
68void register_cp_regs_for_features(ARMCPU *cpu);
69void init_cpreg_list(ARMCPU *cpu);
70
71
72void arm_gt_ptimer_cb(void *opaque);
73void arm_gt_vtimer_cb(void *opaque);
74void arm_gt_htimer_cb(void *opaque);
75void arm_gt_stimer_cb(void *opaque);
76
77#define ARM_AFF0_SHIFT 0
78#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
79#define ARM_AFF1_SHIFT 8
80#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
81#define ARM_AFF2_SHIFT 16
82#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
83#define ARM_AFF3_SHIFT 32
84#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
85#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
86
87#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
88#define ARM64_AFFINITY_MASK \
89 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
90#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
91
92#endif
93