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21#ifndef I386_CPU_H
22#define I386_CPU_H
23
24#include "qemu-common.h"
25#include "cpu-qom.h"
26#include "hyperv-proto.h"
27
28#ifdef TARGET_X86_64
29#define TARGET_LONG_BITS 64
30#else
31#define TARGET_LONG_BITS 32
32#endif
33
34#include "exec/cpu-defs.h"
35
36
37#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
38
39
40#define TARGET_MAX_INSN_SIZE 16
41
42
43
44#define TARGET_HAS_PRECISE_SMC
45
46#ifdef TARGET_X86_64
47#define I386_ELF_MACHINE EM_X86_64
48#define ELF_MACHINE_UNAME "x86_64"
49#else
50#define I386_ELF_MACHINE EM_386
51#define ELF_MACHINE_UNAME "i686"
52#endif
53
54#define CPUArchState struct CPUX86State
55
56enum {
57 R_EAX = 0,
58 R_ECX = 1,
59 R_EDX = 2,
60 R_EBX = 3,
61 R_ESP = 4,
62 R_EBP = 5,
63 R_ESI = 6,
64 R_EDI = 7,
65 R_R8 = 8,
66 R_R9 = 9,
67 R_R10 = 10,
68 R_R11 = 11,
69 R_R12 = 12,
70 R_R13 = 13,
71 R_R14 = 14,
72 R_R15 = 15,
73
74 R_AL = 0,
75 R_CL = 1,
76 R_DL = 2,
77 R_BL = 3,
78 R_AH = 4,
79 R_CH = 5,
80 R_DH = 6,
81 R_BH = 7,
82};
83
84typedef enum X86Seg {
85 R_ES = 0,
86 R_CS = 1,
87 R_SS = 2,
88 R_DS = 3,
89 R_FS = 4,
90 R_GS = 5,
91 R_LDTR = 6,
92 R_TR = 7,
93} X86Seg;
94
95
96#define DESC_G_SHIFT 23
97#define DESC_G_MASK (1 << DESC_G_SHIFT)
98#define DESC_B_SHIFT 22
99#define DESC_B_MASK (1 << DESC_B_SHIFT)
100#define DESC_L_SHIFT 21
101#define DESC_L_MASK (1 << DESC_L_SHIFT)
102#define DESC_AVL_SHIFT 20
103#define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
104#define DESC_P_SHIFT 15
105#define DESC_P_MASK (1 << DESC_P_SHIFT)
106#define DESC_DPL_SHIFT 13
107#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
108#define DESC_S_SHIFT 12
109#define DESC_S_MASK (1 << DESC_S_SHIFT)
110#define DESC_TYPE_SHIFT 8
111#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
112#define DESC_A_MASK (1 << 8)
113
114#define DESC_CS_MASK (1 << 11)
115#define DESC_C_MASK (1 << 10)
116#define DESC_R_MASK (1 << 9)
117
118#define DESC_E_MASK (1 << 10)
119#define DESC_W_MASK (1 << 9)
120
121#define DESC_TSS_BUSY_MASK (1 << 9)
122
123
124#define CC_C 0x0001
125#define CC_P 0x0004
126#define CC_A 0x0010
127#define CC_Z 0x0040
128#define CC_S 0x0080
129#define CC_O 0x0800
130
131#define TF_SHIFT 8
132#define IOPL_SHIFT 12
133#define VM_SHIFT 17
134
135#define TF_MASK 0x00000100
136#define IF_MASK 0x00000200
137#define DF_MASK 0x00000400
138#define IOPL_MASK 0x00003000
139#define NT_MASK 0x00004000
140#define RF_MASK 0x00010000
141#define VM_MASK 0x00020000
142#define AC_MASK 0x00040000
143#define VIF_MASK 0x00080000
144#define VIP_MASK 0x00100000
145#define ID_MASK 0x00200000
146
147
148
149
150
151
152#define HF_CPL_SHIFT 0
153
154#define HF_INHIBIT_IRQ_SHIFT 3
155
156#define HF_CS32_SHIFT 4
157#define HF_SS32_SHIFT 5
158
159#define HF_ADDSEG_SHIFT 6
160
161#define HF_PE_SHIFT 7
162#define HF_TF_SHIFT 8
163#define HF_MP_SHIFT 9
164#define HF_EM_SHIFT 10
165#define HF_TS_SHIFT 11
166#define HF_IOPL_SHIFT 12
167#define HF_LMA_SHIFT 14
168#define HF_CS64_SHIFT 15
169#define HF_RF_SHIFT 16
170#define HF_VM_SHIFT 17
171#define HF_AC_SHIFT 18
172#define HF_SMM_SHIFT 19
173#define HF_SVME_SHIFT 20
174#define HF_SVMI_SHIFT 21
175#define HF_OSFXSR_SHIFT 22
176#define HF_SMAP_SHIFT 23
177#define HF_IOBPT_SHIFT 24
178#define HF_MPX_EN_SHIFT 25
179#define HF_MPX_IU_SHIFT 26
180
181#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
182#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
183#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
184#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
185#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
186#define HF_PE_MASK (1 << HF_PE_SHIFT)
187#define HF_TF_MASK (1 << HF_TF_SHIFT)
188#define HF_MP_MASK (1 << HF_MP_SHIFT)
189#define HF_EM_MASK (1 << HF_EM_SHIFT)
190#define HF_TS_MASK (1 << HF_TS_SHIFT)
191#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
192#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
193#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
194#define HF_RF_MASK (1 << HF_RF_SHIFT)
195#define HF_VM_MASK (1 << HF_VM_SHIFT)
196#define HF_AC_MASK (1 << HF_AC_SHIFT)
197#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
198#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
199#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
200#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
201#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
202#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
203#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
204#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
205
206
207
208#define HF2_GIF_SHIFT 0
209#define HF2_HIF_SHIFT 1
210#define HF2_NMI_SHIFT 2
211#define HF2_VINTR_SHIFT 3
212#define HF2_SMM_INSIDE_NMI_SHIFT 4
213#define HF2_MPX_PR_SHIFT 5
214
215#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
216#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
217#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
218#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
219#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
220#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
221
222#define CR0_PE_SHIFT 0
223#define CR0_MP_SHIFT 1
224
225#define CR0_PE_MASK (1U << 0)
226#define CR0_MP_MASK (1U << 1)
227#define CR0_EM_MASK (1U << 2)
228#define CR0_TS_MASK (1U << 3)
229#define CR0_ET_MASK (1U << 4)
230#define CR0_NE_MASK (1U << 5)
231#define CR0_WP_MASK (1U << 16)
232#define CR0_AM_MASK (1U << 18)
233#define CR0_PG_MASK (1U << 31)
234
235#define CR4_VME_MASK (1U << 0)
236#define CR4_PVI_MASK (1U << 1)
237#define CR4_TSD_MASK (1U << 2)
238#define CR4_DE_MASK (1U << 3)
239#define CR4_PSE_MASK (1U << 4)
240#define CR4_PAE_MASK (1U << 5)
241#define CR4_MCE_MASK (1U << 6)
242#define CR4_PGE_MASK (1U << 7)
243#define CR4_PCE_MASK (1U << 8)
244#define CR4_OSFXSR_SHIFT 9
245#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
246#define CR4_OSXMMEXCPT_MASK (1U << 10)
247#define CR4_LA57_MASK (1U << 12)
248#define CR4_VMXE_MASK (1U << 13)
249#define CR4_SMXE_MASK (1U << 14)
250#define CR4_FSGSBASE_MASK (1U << 16)
251#define CR4_PCIDE_MASK (1U << 17)
252#define CR4_OSXSAVE_MASK (1U << 18)
253#define CR4_SMEP_MASK (1U << 20)
254#define CR4_SMAP_MASK (1U << 21)
255#define CR4_PKE_MASK (1U << 22)
256
257#define DR6_BD (1 << 13)
258#define DR6_BS (1 << 14)
259#define DR6_BT (1 << 15)
260#define DR6_FIXED_1 0xffff0ff0
261
262#define DR7_GD (1 << 13)
263#define DR7_TYPE_SHIFT 16
264#define DR7_LEN_SHIFT 18
265#define DR7_FIXED_1 0x00000400
266#define DR7_GLOBAL_BP_MASK 0xaa
267#define DR7_LOCAL_BP_MASK 0x55
268#define DR7_MAX_BP 4
269#define DR7_TYPE_BP_INST 0x0
270#define DR7_TYPE_DATA_WR 0x1
271#define DR7_TYPE_IO_RW 0x2
272#define DR7_TYPE_DATA_RW 0x3
273
274#define PG_PRESENT_BIT 0
275#define PG_RW_BIT 1
276#define PG_USER_BIT 2
277#define PG_PWT_BIT 3
278#define PG_PCD_BIT 4
279#define PG_ACCESSED_BIT 5
280#define PG_DIRTY_BIT 6
281#define PG_PSE_BIT 7
282#define PG_GLOBAL_BIT 8
283#define PG_PSE_PAT_BIT 12
284#define PG_PKRU_BIT 59
285#define PG_NX_BIT 63
286
287#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
288#define PG_RW_MASK (1 << PG_RW_BIT)
289#define PG_USER_MASK (1 << PG_USER_BIT)
290#define PG_PWT_MASK (1 << PG_PWT_BIT)
291#define PG_PCD_MASK (1 << PG_PCD_BIT)
292#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
293#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
294#define PG_PSE_MASK (1 << PG_PSE_BIT)
295#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
296#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
297#define PG_ADDRESS_MASK 0x000ffffffffff000LL
298#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
299#define PG_HI_USER_MASK 0x7ff0000000000000LL
300#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
301#define PG_NX_MASK (1ULL << PG_NX_BIT)
302
303#define PG_ERROR_W_BIT 1
304
305#define PG_ERROR_P_MASK 0x01
306#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
307#define PG_ERROR_U_MASK 0x04
308#define PG_ERROR_RSVD_MASK 0x08
309#define PG_ERROR_I_D_MASK 0x10
310#define PG_ERROR_PK_MASK 0x20
311
312#define MCG_CTL_P (1ULL<<8)
313#define MCG_SER_P (1ULL<<24)
314#define MCG_LMCE_P (1ULL<<27)
315
316#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
317#define MCE_BANKS_DEF 10
318
319#define MCG_CAP_BANKS_MASK 0xff
320
321#define MCG_STATUS_RIPV (1ULL<<0)
322#define MCG_STATUS_EIPV (1ULL<<1)
323#define MCG_STATUS_MCIP (1ULL<<2)
324#define MCG_STATUS_LMCE (1ULL<<3)
325
326#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
327
328#define MCI_STATUS_VAL (1ULL<<63)
329#define MCI_STATUS_OVER (1ULL<<62)
330#define MCI_STATUS_UC (1ULL<<61)
331#define MCI_STATUS_EN (1ULL<<60)
332#define MCI_STATUS_MISCV (1ULL<<59)
333#define MCI_STATUS_ADDRV (1ULL<<58)
334#define MCI_STATUS_PCC (1ULL<<57)
335#define MCI_STATUS_S (1ULL<<56)
336#define MCI_STATUS_AR (1ULL<<55)
337
338
339#define MCM_ADDR_SEGOFF 0
340#define MCM_ADDR_LINEAR 1
341#define MCM_ADDR_PHYS 2
342#define MCM_ADDR_MEM 3
343#define MCM_ADDR_GENERIC 7
344
345#define MSR_IA32_TSC 0x10
346#define MSR_IA32_APICBASE 0x1b
347#define MSR_IA32_APICBASE_BSP (1<<8)
348#define MSR_IA32_APICBASE_ENABLE (1<<11)
349#define MSR_IA32_APICBASE_EXTD (1 << 10)
350#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
351#define MSR_IA32_FEATURE_CONTROL 0x0000003a
352#define MSR_TSC_ADJUST 0x0000003b
353#define MSR_IA32_SPEC_CTRL 0x48
354#define MSR_IA32_TSCDEADLINE 0x6e0
355
356#define FEATURE_CONTROL_LOCKED (1<<0)
357#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
358#define FEATURE_CONTROL_LMCE (1<<20)
359
360#define MSR_P6_PERFCTR0 0xc1
361
362#define MSR_IA32_SMBASE 0x9e
363#define MSR_SMI_COUNT 0x34
364#define MSR_MTRRcap 0xfe
365#define MSR_MTRRcap_VCNT 8
366#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
367#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
368
369#define MSR_IA32_SYSENTER_CS 0x174
370#define MSR_IA32_SYSENTER_ESP 0x175
371#define MSR_IA32_SYSENTER_EIP 0x176
372
373#define MSR_MCG_CAP 0x179
374#define MSR_MCG_STATUS 0x17a
375#define MSR_MCG_CTL 0x17b
376#define MSR_MCG_EXT_CTL 0x4d0
377
378#define MSR_P6_EVNTSEL0 0x186
379
380#define MSR_IA32_PERF_STATUS 0x198
381
382#define MSR_IA32_MISC_ENABLE 0x1a0
383
384#define MSR_IA32_MISC_ENABLE_DEFAULT 1
385
386#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
387#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
388
389#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
390
391#define MSR_MTRRfix64K_00000 0x250
392#define MSR_MTRRfix16K_80000 0x258
393#define MSR_MTRRfix16K_A0000 0x259
394#define MSR_MTRRfix4K_C0000 0x268
395#define MSR_MTRRfix4K_C8000 0x269
396#define MSR_MTRRfix4K_D0000 0x26a
397#define MSR_MTRRfix4K_D8000 0x26b
398#define MSR_MTRRfix4K_E0000 0x26c
399#define MSR_MTRRfix4K_E8000 0x26d
400#define MSR_MTRRfix4K_F0000 0x26e
401#define MSR_MTRRfix4K_F8000 0x26f
402
403#define MSR_PAT 0x277
404
405#define MSR_MTRRdefType 0x2ff
406
407#define MSR_CORE_PERF_FIXED_CTR0 0x309
408#define MSR_CORE_PERF_FIXED_CTR1 0x30a
409#define MSR_CORE_PERF_FIXED_CTR2 0x30b
410#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
411#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
412#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
413#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
414
415#define MSR_MC0_CTL 0x400
416#define MSR_MC0_STATUS 0x401
417#define MSR_MC0_ADDR 0x402
418#define MSR_MC0_MISC 0x403
419
420#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
421#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
422#define MSR_IA32_RTIT_CTL 0x570
423#define MSR_IA32_RTIT_STATUS 0x571
424#define MSR_IA32_RTIT_CR3_MATCH 0x572
425#define MSR_IA32_RTIT_ADDR0_A 0x580
426#define MSR_IA32_RTIT_ADDR0_B 0x581
427#define MSR_IA32_RTIT_ADDR1_A 0x582
428#define MSR_IA32_RTIT_ADDR1_B 0x583
429#define MSR_IA32_RTIT_ADDR2_A 0x584
430#define MSR_IA32_RTIT_ADDR2_B 0x585
431#define MSR_IA32_RTIT_ADDR3_A 0x586
432#define MSR_IA32_RTIT_ADDR3_B 0x587
433#define MAX_RTIT_ADDRS 8
434
435#define MSR_EFER 0xc0000080
436
437#define MSR_EFER_SCE (1 << 0)
438#define MSR_EFER_LME (1 << 8)
439#define MSR_EFER_LMA (1 << 10)
440#define MSR_EFER_NXE (1 << 11)
441#define MSR_EFER_SVME (1 << 12)
442#define MSR_EFER_FFXSR (1 << 14)
443
444#define MSR_STAR 0xc0000081
445#define MSR_LSTAR 0xc0000082
446#define MSR_CSTAR 0xc0000083
447#define MSR_FMASK 0xc0000084
448#define MSR_FSBASE 0xc0000100
449#define MSR_GSBASE 0xc0000101
450#define MSR_KERNELGSBASE 0xc0000102
451#define MSR_TSC_AUX 0xc0000103
452
453#define MSR_VM_HSAVE_PA 0xc0010117
454
455#define MSR_IA32_BNDCFGS 0x00000d90
456#define MSR_IA32_XSS 0x00000da0
457
458#define XSTATE_FP_BIT 0
459#define XSTATE_SSE_BIT 1
460#define XSTATE_YMM_BIT 2
461#define XSTATE_BNDREGS_BIT 3
462#define XSTATE_BNDCSR_BIT 4
463#define XSTATE_OPMASK_BIT 5
464#define XSTATE_ZMM_Hi256_BIT 6
465#define XSTATE_Hi16_ZMM_BIT 7
466#define XSTATE_PKRU_BIT 9
467
468#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
469#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
470#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
471#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
472#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
473#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
474#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
475#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
476#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
477
478
479typedef enum FeatureWord {
480 FEAT_1_EDX,
481 FEAT_1_ECX,
482 FEAT_7_0_EBX,
483 FEAT_7_0_ECX,
484 FEAT_7_0_EDX,
485 FEAT_8000_0001_EDX,
486 FEAT_8000_0001_ECX,
487 FEAT_8000_0007_EDX,
488 FEAT_8000_0008_EBX,
489 FEAT_C000_0001_EDX,
490 FEAT_KVM,
491 FEAT_KVM_HINTS,
492 FEAT_HYPERV_EAX,
493 FEAT_HYPERV_EBX,
494 FEAT_HYPERV_EDX,
495 FEAT_SVM,
496 FEAT_XSAVE,
497 FEAT_6_EAX,
498 FEAT_XSAVE_COMP_LO,
499 FEAT_XSAVE_COMP_HI,
500 FEATURE_WORDS,
501} FeatureWord;
502
503typedef uint32_t FeatureWordArray[FEATURE_WORDS];
504
505
506#define CPUID_FP87 (1U << 0)
507#define CPUID_VME (1U << 1)
508#define CPUID_DE (1U << 2)
509#define CPUID_PSE (1U << 3)
510#define CPUID_TSC (1U << 4)
511#define CPUID_MSR (1U << 5)
512#define CPUID_PAE (1U << 6)
513#define CPUID_MCE (1U << 7)
514#define CPUID_CX8 (1U << 8)
515#define CPUID_APIC (1U << 9)
516#define CPUID_SEP (1U << 11)
517#define CPUID_MTRR (1U << 12)
518#define CPUID_PGE (1U << 13)
519#define CPUID_MCA (1U << 14)
520#define CPUID_CMOV (1U << 15)
521#define CPUID_PAT (1U << 16)
522#define CPUID_PSE36 (1U << 17)
523#define CPUID_PN (1U << 18)
524#define CPUID_CLFLUSH (1U << 19)
525#define CPUID_DTS (1U << 21)
526#define CPUID_ACPI (1U << 22)
527#define CPUID_MMX (1U << 23)
528#define CPUID_FXSR (1U << 24)
529#define CPUID_SSE (1U << 25)
530#define CPUID_SSE2 (1U << 26)
531#define CPUID_SS (1U << 27)
532#define CPUID_HT (1U << 28)
533#define CPUID_TM (1U << 29)
534#define CPUID_IA64 (1U << 30)
535#define CPUID_PBE (1U << 31)
536
537#define CPUID_EXT_SSE3 (1U << 0)
538#define CPUID_EXT_PCLMULQDQ (1U << 1)
539#define CPUID_EXT_DTES64 (1U << 2)
540#define CPUID_EXT_MONITOR (1U << 3)
541#define CPUID_EXT_DSCPL (1U << 4)
542#define CPUID_EXT_VMX (1U << 5)
543#define CPUID_EXT_SMX (1U << 6)
544#define CPUID_EXT_EST (1U << 7)
545#define CPUID_EXT_TM2 (1U << 8)
546#define CPUID_EXT_SSSE3 (1U << 9)
547#define CPUID_EXT_CID (1U << 10)
548#define CPUID_EXT_FMA (1U << 12)
549#define CPUID_EXT_CX16 (1U << 13)
550#define CPUID_EXT_XTPR (1U << 14)
551#define CPUID_EXT_PDCM (1U << 15)
552#define CPUID_EXT_PCID (1U << 17)
553#define CPUID_EXT_DCA (1U << 18)
554#define CPUID_EXT_SSE41 (1U << 19)
555#define CPUID_EXT_SSE42 (1U << 20)
556#define CPUID_EXT_X2APIC (1U << 21)
557#define CPUID_EXT_MOVBE (1U << 22)
558#define CPUID_EXT_POPCNT (1U << 23)
559#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
560#define CPUID_EXT_AES (1U << 25)
561#define CPUID_EXT_XSAVE (1U << 26)
562#define CPUID_EXT_OSXSAVE (1U << 27)
563#define CPUID_EXT_AVX (1U << 28)
564#define CPUID_EXT_F16C (1U << 29)
565#define CPUID_EXT_RDRAND (1U << 30)
566#define CPUID_EXT_HYPERVISOR (1U << 31)
567
568#define CPUID_EXT2_FPU (1U << 0)
569#define CPUID_EXT2_VME (1U << 1)
570#define CPUID_EXT2_DE (1U << 2)
571#define CPUID_EXT2_PSE (1U << 3)
572#define CPUID_EXT2_TSC (1U << 4)
573#define CPUID_EXT2_MSR (1U << 5)
574#define CPUID_EXT2_PAE (1U << 6)
575#define CPUID_EXT2_MCE (1U << 7)
576#define CPUID_EXT2_CX8 (1U << 8)
577#define CPUID_EXT2_APIC (1U << 9)
578#define CPUID_EXT2_SYSCALL (1U << 11)
579#define CPUID_EXT2_MTRR (1U << 12)
580#define CPUID_EXT2_PGE (1U << 13)
581#define CPUID_EXT2_MCA (1U << 14)
582#define CPUID_EXT2_CMOV (1U << 15)
583#define CPUID_EXT2_PAT (1U << 16)
584#define CPUID_EXT2_PSE36 (1U << 17)
585#define CPUID_EXT2_MP (1U << 19)
586#define CPUID_EXT2_NX (1U << 20)
587#define CPUID_EXT2_MMXEXT (1U << 22)
588#define CPUID_EXT2_MMX (1U << 23)
589#define CPUID_EXT2_FXSR (1U << 24)
590#define CPUID_EXT2_FFXSR (1U << 25)
591#define CPUID_EXT2_PDPE1GB (1U << 26)
592#define CPUID_EXT2_RDTSCP (1U << 27)
593#define CPUID_EXT2_LM (1U << 29)
594#define CPUID_EXT2_3DNOWEXT (1U << 30)
595#define CPUID_EXT2_3DNOW (1U << 31)
596
597
598#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
599 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
600 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
601 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
602 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
603 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
604 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
605 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
606 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
607
608#define CPUID_EXT3_LAHF_LM (1U << 0)
609#define CPUID_EXT3_CMP_LEG (1U << 1)
610#define CPUID_EXT3_SVM (1U << 2)
611#define CPUID_EXT3_EXTAPIC (1U << 3)
612#define CPUID_EXT3_CR8LEG (1U << 4)
613#define CPUID_EXT3_ABM (1U << 5)
614#define CPUID_EXT3_SSE4A (1U << 6)
615#define CPUID_EXT3_MISALIGNSSE (1U << 7)
616#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
617#define CPUID_EXT3_OSVW (1U << 9)
618#define CPUID_EXT3_IBS (1U << 10)
619#define CPUID_EXT3_XOP (1U << 11)
620#define CPUID_EXT3_SKINIT (1U << 12)
621#define CPUID_EXT3_WDT (1U << 13)
622#define CPUID_EXT3_LWP (1U << 15)
623#define CPUID_EXT3_FMA4 (1U << 16)
624#define CPUID_EXT3_TCE (1U << 17)
625#define CPUID_EXT3_NODEID (1U << 19)
626#define CPUID_EXT3_TBM (1U << 21)
627#define CPUID_EXT3_TOPOEXT (1U << 22)
628#define CPUID_EXT3_PERFCORE (1U << 23)
629#define CPUID_EXT3_PERFNB (1U << 24)
630
631#define CPUID_SVM_NPT (1U << 0)
632#define CPUID_SVM_LBRV (1U << 1)
633#define CPUID_SVM_SVMLOCK (1U << 2)
634#define CPUID_SVM_NRIPSAVE (1U << 3)
635#define CPUID_SVM_TSCSCALE (1U << 4)
636#define CPUID_SVM_VMCBCLEAN (1U << 5)
637#define CPUID_SVM_FLUSHASID (1U << 6)
638#define CPUID_SVM_DECODEASSIST (1U << 7)
639#define CPUID_SVM_PAUSEFILTER (1U << 10)
640#define CPUID_SVM_PFTHRESHOLD (1U << 12)
641
642#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
643#define CPUID_7_0_EBX_BMI1 (1U << 3)
644#define CPUID_7_0_EBX_HLE (1U << 4)
645#define CPUID_7_0_EBX_AVX2 (1U << 5)
646#define CPUID_7_0_EBX_SMEP (1U << 7)
647#define CPUID_7_0_EBX_BMI2 (1U << 8)
648#define CPUID_7_0_EBX_ERMS (1U << 9)
649#define CPUID_7_0_EBX_INVPCID (1U << 10)
650#define CPUID_7_0_EBX_RTM (1U << 11)
651#define CPUID_7_0_EBX_MPX (1U << 14)
652#define CPUID_7_0_EBX_AVX512F (1U << 16)
653#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
654#define CPUID_7_0_EBX_RDSEED (1U << 18)
655#define CPUID_7_0_EBX_ADX (1U << 19)
656#define CPUID_7_0_EBX_SMAP (1U << 20)
657#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
658#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
659#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
660#define CPUID_7_0_EBX_CLWB (1U << 24)
661#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
662#define CPUID_7_0_EBX_AVX512PF (1U << 26)
663#define CPUID_7_0_EBX_AVX512ER (1U << 27)
664#define CPUID_7_0_EBX_AVX512CD (1U << 28)
665#define CPUID_7_0_EBX_SHA_NI (1U << 29)
666#define CPUID_7_0_EBX_AVX512BW (1U << 30)
667#define CPUID_7_0_EBX_AVX512VL (1U << 31)
668
669#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
670#define CPUID_7_0_ECX_VBMI (1U << 1)
671#define CPUID_7_0_ECX_UMIP (1U << 2)
672#define CPUID_7_0_ECX_PKU (1U << 3)
673#define CPUID_7_0_ECX_OSPKE (1U << 4)
674#define CPUID_7_0_ECX_VBMI2 (1U << 6)
675#define CPUID_7_0_ECX_GFNI (1U << 8)
676#define CPUID_7_0_ECX_VAES (1U << 9)
677#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
678#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
679#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
680#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
681#define CPUID_7_0_ECX_LA57 (1U << 16)
682#define CPUID_7_0_ECX_RDPID (1U << 22)
683
684#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
685#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
686#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
687
688#define KVM_HINTS_DEDICATED (1U << 0)
689
690#define CPUID_8000_0008_EBX_IBPB (1U << 12)
691
692#define CPUID_XSAVE_XSAVEOPT (1U << 0)
693#define CPUID_XSAVE_XSAVEC (1U << 1)
694#define CPUID_XSAVE_XGETBV1 (1U << 2)
695#define CPUID_XSAVE_XSAVES (1U << 3)
696
697#define CPUID_6_EAX_ARAT (1U << 2)
698
699
700#define CPUID_APM_INVTSC (1U << 8)
701
702#define CPUID_VENDOR_SZ 12
703
704#define CPUID_VENDOR_INTEL_1 0x756e6547
705#define CPUID_VENDOR_INTEL_2 0x49656e69
706#define CPUID_VENDOR_INTEL_3 0x6c65746e
707#define CPUID_VENDOR_INTEL "GenuineIntel"
708
709#define CPUID_VENDOR_AMD_1 0x68747541
710#define CPUID_VENDOR_AMD_2 0x69746e65
711#define CPUID_VENDOR_AMD_3 0x444d4163
712#define CPUID_VENDOR_AMD "AuthenticAMD"
713
714#define CPUID_VENDOR_VIA "CentaurHauls"
715
716#define CPUID_MWAIT_IBE (1U << 1)
717#define CPUID_MWAIT_EMX (1U << 0)
718
719
720#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
721#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
722#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
723
724#ifndef HYPERV_SPINLOCK_NEVER_RETRY
725#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
726#endif
727
728#define EXCP00_DIVZ 0
729#define EXCP01_DB 1
730#define EXCP02_NMI 2
731#define EXCP03_INT3 3
732#define EXCP04_INTO 4
733#define EXCP05_BOUND 5
734#define EXCP06_ILLOP 6
735#define EXCP07_PREX 7
736#define EXCP08_DBLE 8
737#define EXCP09_XERR 9
738#define EXCP0A_TSS 10
739#define EXCP0B_NOSEG 11
740#define EXCP0C_STACK 12
741#define EXCP0D_GPF 13
742#define EXCP0E_PAGE 14
743#define EXCP10_COPR 16
744#define EXCP11_ALGN 17
745#define EXCP12_MCHK 18
746
747#define EXCP_SYSCALL 0x100
748
749#define EXCP_VMEXIT 0x100
750
751
752#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
753#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
754#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
755#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
756#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
757#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
758#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
759
760
761#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
762
763
764
765
766
767
768
769
770typedef enum {
771 CC_OP_DYNAMIC,
772 CC_OP_EFLAGS,
773
774 CC_OP_MULB,
775 CC_OP_MULW,
776 CC_OP_MULL,
777 CC_OP_MULQ,
778
779 CC_OP_ADDB,
780 CC_OP_ADDW,
781 CC_OP_ADDL,
782 CC_OP_ADDQ,
783
784 CC_OP_ADCB,
785 CC_OP_ADCW,
786 CC_OP_ADCL,
787 CC_OP_ADCQ,
788
789 CC_OP_SUBB,
790 CC_OP_SUBW,
791 CC_OP_SUBL,
792 CC_OP_SUBQ,
793
794 CC_OP_SBBB,
795 CC_OP_SBBW,
796 CC_OP_SBBL,
797 CC_OP_SBBQ,
798
799 CC_OP_LOGICB,
800 CC_OP_LOGICW,
801 CC_OP_LOGICL,
802 CC_OP_LOGICQ,
803
804 CC_OP_INCB,
805 CC_OP_INCW,
806 CC_OP_INCL,
807 CC_OP_INCQ,
808
809 CC_OP_DECB,
810 CC_OP_DECW,
811 CC_OP_DECL,
812 CC_OP_DECQ,
813
814 CC_OP_SHLB,
815 CC_OP_SHLW,
816 CC_OP_SHLL,
817 CC_OP_SHLQ,
818
819 CC_OP_SARB,
820 CC_OP_SARW,
821 CC_OP_SARL,
822 CC_OP_SARQ,
823
824 CC_OP_BMILGB,
825 CC_OP_BMILGW,
826 CC_OP_BMILGL,
827 CC_OP_BMILGQ,
828
829 CC_OP_ADCX,
830 CC_OP_ADOX,
831 CC_OP_ADCOX,
832
833 CC_OP_CLR,
834 CC_OP_POPCNT,
835
836 CC_OP_NB,
837} CCOp;
838
839typedef struct SegmentCache {
840 uint32_t selector;
841 target_ulong base;
842 uint32_t limit;
843 uint32_t flags;
844} SegmentCache;
845
846#define MMREG_UNION(n, bits) \
847 union n { \
848 uint8_t _b_##n[(bits)/8]; \
849 uint16_t _w_##n[(bits)/16]; \
850 uint32_t _l_##n[(bits)/32]; \
851 uint64_t _q_##n[(bits)/64]; \
852 float32 _s_##n[(bits)/32]; \
853 float64 _d_##n[(bits)/64]; \
854 }
855
856typedef union {
857 uint8_t _b[16];
858 uint16_t _w[8];
859 uint32_t _l[4];
860 uint64_t _q[2];
861} XMMReg;
862
863typedef union {
864 uint8_t _b[32];
865 uint16_t _w[16];
866 uint32_t _l[8];
867 uint64_t _q[4];
868} YMMReg;
869
870typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
871typedef MMREG_UNION(MMXReg, 64) MMXReg;
872
873typedef struct BNDReg {
874 uint64_t lb;
875 uint64_t ub;
876} BNDReg;
877
878typedef struct BNDCSReg {
879 uint64_t cfgu;
880 uint64_t sts;
881} BNDCSReg;
882
883#define BNDCFG_ENABLE 1ULL
884#define BNDCFG_BNDPRESERVE 2ULL
885#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
886
887#ifdef HOST_WORDS_BIGENDIAN
888#define ZMM_B(n) _b_ZMMReg[63 - (n)]
889#define ZMM_W(n) _w_ZMMReg[31 - (n)]
890#define ZMM_L(n) _l_ZMMReg[15 - (n)]
891#define ZMM_S(n) _s_ZMMReg[15 - (n)]
892#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
893#define ZMM_D(n) _d_ZMMReg[7 - (n)]
894
895#define MMX_B(n) _b_MMXReg[7 - (n)]
896#define MMX_W(n) _w_MMXReg[3 - (n)]
897#define MMX_L(n) _l_MMXReg[1 - (n)]
898#define MMX_S(n) _s_MMXReg[1 - (n)]
899#else
900#define ZMM_B(n) _b_ZMMReg[n]
901#define ZMM_W(n) _w_ZMMReg[n]
902#define ZMM_L(n) _l_ZMMReg[n]
903#define ZMM_S(n) _s_ZMMReg[n]
904#define ZMM_Q(n) _q_ZMMReg[n]
905#define ZMM_D(n) _d_ZMMReg[n]
906
907#define MMX_B(n) _b_MMXReg[n]
908#define MMX_W(n) _w_MMXReg[n]
909#define MMX_L(n) _l_MMXReg[n]
910#define MMX_S(n) _s_MMXReg[n]
911#endif
912#define MMX_Q(n) _q_MMXReg[n]
913
914typedef union {
915 floatx80 d __attribute__((aligned(16)));
916 MMXReg mmx;
917} FPReg;
918
919typedef struct {
920 uint64_t base;
921 uint64_t mask;
922} MTRRVar;
923
924#define CPU_NB_REGS64 16
925#define CPU_NB_REGS32 8
926
927#ifdef TARGET_X86_64
928#define CPU_NB_REGS CPU_NB_REGS64
929#else
930#define CPU_NB_REGS CPU_NB_REGS32
931#endif
932
933#define MAX_FIXED_COUNTERS 3
934#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
935
936#define NB_MMU_MODES 3
937#define TARGET_INSN_START_EXTRA_WORDS 1
938
939#define NB_OPMASK_REGS 8
940
941
942
943
944#define UNASSIGNED_APIC_ID 0xFFFFFFFF
945
946typedef union X86LegacyXSaveArea {
947 struct {
948 uint16_t fcw;
949 uint16_t fsw;
950 uint8_t ftw;
951 uint8_t reserved;
952 uint16_t fpop;
953 uint64_t fpip;
954 uint64_t fpdp;
955 uint32_t mxcsr;
956 uint32_t mxcsr_mask;
957 FPReg fpregs[8];
958 uint8_t xmm_regs[16][16];
959 };
960 uint8_t data[512];
961} X86LegacyXSaveArea;
962
963typedef struct X86XSaveHeader {
964 uint64_t xstate_bv;
965 uint64_t xcomp_bv;
966 uint64_t reserve0;
967 uint8_t reserved[40];
968} X86XSaveHeader;
969
970
971typedef struct XSaveAVX {
972 uint8_t ymmh[16][16];
973} XSaveAVX;
974
975
976typedef struct XSaveBNDREG {
977 BNDReg bnd_regs[4];
978} XSaveBNDREG;
979
980
981typedef union XSaveBNDCSR {
982 BNDCSReg bndcsr;
983 uint8_t data[64];
984} XSaveBNDCSR;
985
986
987typedef struct XSaveOpmask {
988 uint64_t opmask_regs[NB_OPMASK_REGS];
989} XSaveOpmask;
990
991
992typedef struct XSaveZMM_Hi256 {
993 uint8_t zmm_hi256[16][32];
994} XSaveZMM_Hi256;
995
996
997typedef struct XSaveHi16_ZMM {
998 uint8_t hi16_zmm[16][64];
999} XSaveHi16_ZMM;
1000
1001
1002typedef struct XSavePKRU {
1003 uint32_t pkru;
1004 uint32_t padding;
1005} XSavePKRU;
1006
1007typedef struct X86XSaveArea {
1008 X86LegacyXSaveArea legacy;
1009 X86XSaveHeader header;
1010
1011
1012
1013
1014 XSaveAVX avx_state;
1015 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1016
1017 XSaveBNDREG bndreg_state;
1018 XSaveBNDCSR bndcsr_state;
1019
1020 XSaveOpmask opmask_state;
1021 XSaveZMM_Hi256 zmm_hi256_state;
1022 XSaveHi16_ZMM hi16_zmm_state;
1023
1024 XSavePKRU pkru_state;
1025} X86XSaveArea;
1026
1027QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1028QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1029QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1030QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1031QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1032QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1033QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1034QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1035QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1036QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1037QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1038QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1039QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1040QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1041
1042typedef enum TPRAccess {
1043 TPR_ACCESS_READ,
1044 TPR_ACCESS_WRITE,
1045} TPRAccess;
1046
1047typedef struct CPUX86State {
1048
1049 target_ulong regs[CPU_NB_REGS];
1050 target_ulong eip;
1051 target_ulong eflags;
1052
1053
1054
1055
1056 target_ulong cc_dst;
1057 target_ulong cc_src;
1058 target_ulong cc_src2;
1059 uint32_t cc_op;
1060 int32_t df;
1061 uint32_t hflags;
1062
1063 uint32_t hflags2;
1064
1065
1066 SegmentCache segs[6];
1067 SegmentCache ldt;
1068 SegmentCache tr;
1069 SegmentCache gdt;
1070 SegmentCache idt;
1071
1072 target_ulong cr[5];
1073 int32_t a20_mask;
1074
1075 BNDReg bnd_regs[4];
1076 BNDCSReg bndcs_regs;
1077 uint64_t msr_bndcfgs;
1078 uint64_t efer;
1079
1080
1081 struct {} start_init_save;
1082
1083
1084 unsigned int fpstt;
1085 uint16_t fpus;
1086 uint16_t fpuc;
1087 uint8_t fptags[8];
1088 FPReg fpregs[8];
1089
1090 uint16_t fpop;
1091 uint64_t fpip;
1092 uint64_t fpdp;
1093
1094
1095 float_status fp_status;
1096 floatx80 ft0;
1097
1098 float_status mmx_status;
1099 float_status sse_status;
1100 uint32_t mxcsr;
1101 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1102 ZMMReg xmm_t0;
1103 MMXReg mmx_t0;
1104
1105 XMMReg ymmh_regs[CPU_NB_REGS];
1106
1107 uint64_t opmask_regs[NB_OPMASK_REGS];
1108 YMMReg zmmh_regs[CPU_NB_REGS];
1109 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1110
1111
1112 uint32_t sysenter_cs;
1113 target_ulong sysenter_esp;
1114 target_ulong sysenter_eip;
1115 uint64_t star;
1116
1117 uint64_t vm_hsave;
1118
1119#ifdef TARGET_X86_64
1120 target_ulong lstar;
1121 target_ulong cstar;
1122 target_ulong fmask;
1123 target_ulong kernelgsbase;
1124#endif
1125
1126 uint64_t tsc;
1127 uint64_t tsc_adjust;
1128 uint64_t tsc_deadline;
1129 uint64_t tsc_aux;
1130
1131 uint64_t xcr0;
1132
1133 uint64_t mcg_status;
1134 uint64_t msr_ia32_misc_enable;
1135 uint64_t msr_ia32_feature_control;
1136
1137 uint64_t msr_fixed_ctr_ctrl;
1138 uint64_t msr_global_ctrl;
1139 uint64_t msr_global_status;
1140 uint64_t msr_global_ovf_ctrl;
1141 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1142 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1143 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1144
1145 uint64_t pat;
1146 uint32_t smbase;
1147 uint64_t msr_smi_count;
1148
1149 uint32_t pkru;
1150
1151 uint64_t spec_ctrl;
1152
1153
1154 struct {} end_init_save;
1155
1156 uint64_t system_time_msr;
1157 uint64_t wall_clock_msr;
1158 uint64_t steal_time_msr;
1159 uint64_t async_pf_en_msr;
1160 uint64_t pv_eoi_en_msr;
1161
1162
1163 uint64_t msr_hv_hypercall;
1164 uint64_t msr_hv_guest_os_id;
1165 uint64_t msr_hv_tsc;
1166
1167
1168 uint64_t msr_hv_vapic;
1169 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1170 uint64_t msr_hv_runtime;
1171 uint64_t msr_hv_synic_control;
1172 uint64_t msr_hv_synic_evt_page;
1173 uint64_t msr_hv_synic_msg_page;
1174 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1175 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1176 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1177
1178 uint64_t msr_rtit_ctrl;
1179 uint64_t msr_rtit_status;
1180 uint64_t msr_rtit_output_base;
1181 uint64_t msr_rtit_output_mask;
1182 uint64_t msr_rtit_cr3_match;
1183 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1184
1185
1186 int error_code;
1187 int exception_is_int;
1188 target_ulong exception_next_eip;
1189 target_ulong dr[8];
1190 union {
1191 struct CPUBreakpoint *cpu_breakpoint[4];
1192 struct CPUWatchpoint *cpu_watchpoint[4];
1193 };
1194 int old_exception;
1195
1196 uint64_t vm_vmcb;
1197 uint64_t tsc_offset;
1198 uint64_t intercept;
1199 uint16_t intercept_cr_read;
1200 uint16_t intercept_cr_write;
1201 uint16_t intercept_dr_read;
1202 uint16_t intercept_dr_write;
1203 uint32_t intercept_exceptions;
1204 uint8_t v_tpr;
1205
1206
1207 uint8_t nmi_injected;
1208 uint8_t nmi_pending;
1209
1210
1211 struct {} end_reset_fields;
1212
1213 CPU_COMMON
1214
1215
1216
1217
1218
1219 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1220
1221 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1222
1223 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1224 uint32_t cpuid_vendor1;
1225 uint32_t cpuid_vendor2;
1226 uint32_t cpuid_vendor3;
1227 uint32_t cpuid_version;
1228 FeatureWordArray features;
1229
1230 FeatureWordArray user_features;
1231 uint32_t cpuid_model[12];
1232
1233
1234 uint64_t mtrr_fixed[11];
1235 uint64_t mtrr_deftype;
1236 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1237
1238
1239 uint32_t mp_state;
1240 int32_t exception_injected;
1241 int32_t interrupt_injected;
1242 uint8_t soft_interrupt;
1243 uint8_t has_error_code;
1244 uint32_t ins_len;
1245 uint32_t sipi_vector;
1246 bool tsc_valid;
1247 int64_t tsc_khz;
1248 int64_t user_tsc_khz;
1249 void *kvm_xsave_buf;
1250#if defined(CONFIG_HVF)
1251 HVFX86EmulatorState *hvf_emul;
1252#endif
1253
1254 uint64_t mcg_cap;
1255 uint64_t mcg_ctl;
1256 uint64_t mcg_ext_ctl;
1257 uint64_t mce_banks[MCE_BANKS_DEF*4];
1258 uint64_t xstate_bv;
1259
1260
1261 uint16_t fpus_vmstate;
1262 uint16_t fptag_vmstate;
1263 uint16_t fpregs_format_vmstate;
1264
1265 uint64_t xss;
1266
1267 TPRAccess tpr_access_type;
1268} CPUX86State;
1269
1270struct kvm_msrs;
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281struct X86CPU {
1282
1283 CPUState parent_obj;
1284
1285
1286 CPUX86State env;
1287
1288 bool hyperv_vapic;
1289 bool hyperv_relaxed_timing;
1290 int hyperv_spinlock_attempts;
1291 char *hyperv_vendor_id;
1292 bool hyperv_time;
1293 bool hyperv_crash;
1294 bool hyperv_reset;
1295 bool hyperv_vpindex;
1296 bool hyperv_runtime;
1297 bool hyperv_synic;
1298 bool hyperv_stimer;
1299 bool hyperv_frequencies;
1300 bool check_cpuid;
1301 bool enforce_cpuid;
1302 bool expose_kvm;
1303 bool expose_tcg;
1304 bool migratable;
1305 bool max_features;
1306 uint32_t apic_id;
1307
1308
1309
1310 bool vmware_cpuid_freq;
1311
1312
1313 bool cache_info_passthrough;
1314
1315
1316 uint32_t filtered_features[FEATURE_WORDS];
1317
1318
1319
1320
1321
1322
1323 bool enable_pmu;
1324
1325
1326
1327
1328
1329 bool enable_lmce;
1330
1331
1332
1333
1334
1335 bool enable_l3_cache;
1336
1337
1338 bool enable_cpuid_0xb;
1339
1340
1341 bool full_cpuid_auto_level;
1342
1343
1344 bool fill_mtrr_mask;
1345
1346
1347 bool host_phys_bits;
1348
1349
1350 bool kvm_no_smi_migration;
1351
1352
1353 uint32_t phys_bits;
1354
1355
1356
1357 struct DeviceState *apic_state;
1358 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1359 Notifier machine_done;
1360
1361 struct kvm_msrs *kvm_msr_buf;
1362
1363 int32_t node_id;
1364 int32_t socket_id;
1365 int32_t core_id;
1366 int32_t thread_id;
1367
1368 int32_t hv_max_vps;
1369};
1370
1371static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1372{
1373 return container_of(env, X86CPU, env);
1374}
1375
1376#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1377
1378#define ENV_OFFSET offsetof(X86CPU, env)
1379
1380#ifndef CONFIG_USER_ONLY
1381extern struct VMStateDescription vmstate_x86_cpu;
1382#endif
1383
1384
1385
1386
1387
1388void x86_cpu_do_interrupt(CPUState *cpu);
1389bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1390
1391int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1392 int cpuid, void *opaque);
1393int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1394 int cpuid, void *opaque);
1395int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1396 void *opaque);
1397int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1398 void *opaque);
1399
1400void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1401 Error **errp);
1402
1403void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1404 int flags);
1405
1406hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1407
1408int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1409int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1410
1411void x86_cpu_exec_enter(CPUState *cpu);
1412void x86_cpu_exec_exit(CPUState *cpu);
1413
1414void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1415int cpu_x86_support_mca_broadcast(CPUX86State *env);
1416
1417int cpu_get_pic_interrupt(CPUX86State *s);
1418
1419void cpu_set_ferr(CPUX86State *s);
1420
1421
1422
1423static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1424 int seg_reg, unsigned int selector,
1425 target_ulong base,
1426 unsigned int limit,
1427 unsigned int flags)
1428{
1429 SegmentCache *sc;
1430 unsigned int new_hflags;
1431
1432 sc = &env->segs[seg_reg];
1433 sc->selector = selector;
1434 sc->base = base;
1435 sc->limit = limit;
1436 sc->flags = flags;
1437
1438
1439 {
1440 if (seg_reg == R_CS) {
1441#ifdef TARGET_X86_64
1442 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1443
1444 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1445 env->hflags &= ~(HF_ADDSEG_MASK);
1446 } else
1447#endif
1448 {
1449
1450 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1451 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1452 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1453 new_hflags;
1454 }
1455 }
1456 if (seg_reg == R_SS) {
1457 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1458#if HF_CPL_MASK != 3
1459#error HF_CPL_MASK is hardcoded
1460#endif
1461 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1462 }
1463 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1464 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1465 if (env->hflags & HF_CS64_MASK) {
1466
1467 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1468 (env->eflags & VM_MASK) ||
1469 !(env->hflags & HF_CS32_MASK)) {
1470
1471
1472
1473
1474
1475 new_hflags |= HF_ADDSEG_MASK;
1476 } else {
1477 new_hflags |= ((env->segs[R_DS].base |
1478 env->segs[R_ES].base |
1479 env->segs[R_SS].base) != 0) <<
1480 HF_ADDSEG_SHIFT;
1481 }
1482 env->hflags = (env->hflags &
1483 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1484 }
1485}
1486
1487static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1488 uint8_t sipi_vector)
1489{
1490 CPUState *cs = CPU(cpu);
1491 CPUX86State *env = &cpu->env;
1492
1493 env->eip = 0;
1494 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1495 sipi_vector << 12,
1496 env->segs[R_CS].limit,
1497 env->segs[R_CS].flags);
1498 cs->halted = 0;
1499}
1500
1501int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1502 target_ulong *base, unsigned int *limit,
1503 unsigned int *flags);
1504
1505
1506
1507
1508
1509
1510
1511void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1512void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1513void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1514void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1515void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1516
1517
1518
1519
1520int cpu_x86_signal_handler(int host_signum, void *pinfo,
1521 void *puc);
1522
1523
1524void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1525 uint32_t *eax, uint32_t *ebx,
1526 uint32_t *ecx, uint32_t *edx);
1527void cpu_clear_apic_feature(CPUX86State *env);
1528void host_cpuid(uint32_t function, uint32_t count,
1529 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1530void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1531
1532
1533int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size,
1534 int is_write, int mmu_idx);
1535void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1536
1537#ifndef CONFIG_USER_ONLY
1538static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1539{
1540 return !!attrs.secure;
1541}
1542
1543static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1544{
1545 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1546}
1547
1548uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1549uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1550uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1551uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1552void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1553void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1554void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1555void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1556void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1557#endif
1558
1559void breakpoint_handler(CPUState *cs);
1560
1561
1562void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1563void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1564void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1565void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1566
1567
1568uint64_t cpu_get_tsc(CPUX86State *env);
1569
1570#define TARGET_PAGE_BITS 12
1571
1572#ifdef TARGET_X86_64
1573#define TARGET_PHYS_ADDR_SPACE_BITS 52
1574
1575
1576
1577#define TARGET_VIRT_ADDR_SPACE_BITS 47
1578#else
1579#define TARGET_PHYS_ADDR_SPACE_BITS 36
1580#define TARGET_VIRT_ADDR_SPACE_BITS 32
1581#endif
1582
1583
1584
1585# if defined(TARGET_X86_64)
1586# define TCG_PHYS_ADDR_BITS 40
1587# else
1588# define TCG_PHYS_ADDR_BITS 36
1589# endif
1590
1591#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1592
1593#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1594#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1595#define CPU_RESOLVING_TYPE TYPE_X86_CPU
1596
1597#ifdef TARGET_X86_64
1598#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1599#else
1600#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1601#endif
1602
1603#define cpu_signal_handler cpu_x86_signal_handler
1604#define cpu_list x86_cpu_list
1605
1606
1607#define MMU_MODE0_SUFFIX _ksmap
1608#define MMU_MODE1_SUFFIX _user
1609#define MMU_MODE2_SUFFIX _knosmap
1610#define MMU_KSMAP_IDX 0
1611#define MMU_USER_IDX 1
1612#define MMU_KNOSMAP_IDX 2
1613static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1614{
1615 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1616 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1617 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1618}
1619
1620static inline int cpu_mmu_index_kernel(CPUX86State *env)
1621{
1622 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1623 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1624 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1625}
1626
1627#define CC_DST (env->cc_dst)
1628#define CC_SRC (env->cc_src)
1629#define CC_SRC2 (env->cc_src2)
1630#define CC_OP (env->cc_op)
1631
1632
1633static inline target_long lshift(target_long x, int n)
1634{
1635 if (n >= 0) {
1636 return x << n;
1637 } else {
1638 return x >> (-n);
1639 }
1640}
1641
1642
1643#define FT0 (env->ft0)
1644#define ST0 (env->fpregs[env->fpstt].d)
1645#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1646#define ST1 ST(1)
1647
1648
1649void tcg_x86_init(void);
1650
1651#include "exec/cpu-all.h"
1652#include "svm.h"
1653
1654#if !defined(CONFIG_USER_ONLY)
1655#include "hw/i386/apic.h"
1656#endif
1657
1658static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1659 target_ulong *cs_base, uint32_t *flags)
1660{
1661 *cs_base = env->segs[R_CS].base;
1662 *pc = *cs_base + env->eip;
1663 *flags = env->hflags |
1664 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1665}
1666
1667void do_cpu_init(X86CPU *cpu);
1668void do_cpu_sipi(X86CPU *cpu);
1669
1670#define MCE_INJECT_BROADCAST 1
1671#define MCE_INJECT_UNCOND_AO 2
1672
1673void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1674 uint64_t status, uint64_t mcg_status, uint64_t addr,
1675 uint64_t misc, int flags);
1676
1677
1678void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1679void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1680 uintptr_t retaddr);
1681void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1682 int error_code);
1683void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1684 int error_code, uintptr_t retaddr);
1685void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1686 int error_code, int next_eip_addend);
1687
1688
1689extern const uint8_t parity_table[256];
1690uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1691
1692static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1693{
1694 uint32_t eflags = env->eflags;
1695 if (tcg_enabled()) {
1696 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1697 }
1698 return eflags;
1699}
1700
1701
1702
1703
1704static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1705 int update_mask)
1706{
1707 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1708 CC_OP = CC_OP_EFLAGS;
1709 env->df = 1 - (2 * ((eflags >> 10) & 1));
1710 env->eflags = (env->eflags & ~update_mask) |
1711 (eflags & update_mask) | 0x2;
1712}
1713
1714
1715
1716static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1717{
1718 env->efer = val;
1719 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1720 if (env->efer & MSR_EFER_LMA) {
1721 env->hflags |= HF_LMA_MASK;
1722 }
1723 if (env->efer & MSR_EFER_SVME) {
1724 env->hflags |= HF_SVME_MASK;
1725 }
1726}
1727
1728static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1729{
1730 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1731}
1732
1733static inline int32_t x86_get_a20_mask(CPUX86State *env)
1734{
1735 if (env->hflags & HF_SMM_MASK) {
1736 return -1;
1737 } else {
1738 return env->a20_mask;
1739 }
1740}
1741
1742
1743void update_fp_status(CPUX86State *env);
1744void update_mxcsr_status(CPUX86State *env);
1745
1746static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1747{
1748 env->mxcsr = mxcsr;
1749 if (tcg_enabled()) {
1750 update_mxcsr_status(env);
1751 }
1752}
1753
1754static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
1755{
1756 env->fpuc = fpuc;
1757 if (tcg_enabled()) {
1758 update_fp_status(env);
1759 }
1760}
1761
1762
1763void helper_lock_init(void);
1764
1765
1766void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1767 uint64_t param, uintptr_t retaddr);
1768void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1,
1769 uintptr_t retaddr);
1770void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
1771
1772
1773void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1774
1775
1776void do_smm_enter(X86CPU *cpu);
1777
1778
1779void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1780void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1781 TPRAccess access);
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792void x86_cpu_change_kvm_default(const char *prop, const char *value);
1793
1794
1795void cpu_sync_bndcs_hflags(CPUX86State *env);
1796
1797
1798const char *get_register_name_32(unsigned int reg);
1799
1800void enable_compat_apic_id_mode(void);
1801
1802#define APIC_DEFAULT_ADDRESS 0xfee00000
1803#define APIC_SPACE_SIZE 0x100000
1804
1805void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1806 fprintf_function cpu_fprintf, int flags);
1807
1808
1809bool cpu_is_bsp(X86CPU *cpu);
1810
1811void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
1812void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
1813void x86_update_hflags(CPUX86State* env);
1814
1815#endif
1816