1LatticeMico32 target 2-------------------- 3 4General 5------- 6All opcodes including the JUART CSRs are supported. 7 8 9JTAG UART 10--------- 11JTAG UART is routed to a serial console device. For the current boards it 12is the second one. Ie to enable it in the qemu virtual console window use 13the following command line parameters: 14 -serial vc -serial vc 15This will make serial0 (the lm32_uart) and serial1 (the JTAG UART) 16available as virtual consoles. 17 18 19Semihosting 20----------- 21Semihosting on this target is supported. Some system calls like read, write 22and exit are executed on the host if semihosting is enabled. See 23target/lm32-semi.c for all supported system calls. Emulation aware programs 24can use this mechanism to shut down the virtual machine and print to the 25host console. See the tcg tests for an example. 26 27 28Special instructions 29-------------------- 30The translation recognizes one special instruction to halt the cpu: 31 and r0, r0, r0 32On real hardware this instruction is a nop. It is not used by GCC and 33should (hopefully) not be used within hand-crafted assembly. 34Insert this instruction in your idle loop to reduce the cpu load on the 35host. 36 37 38Ignoring the MSB of the address bus 39----------------------------------- 40Some SoC ignores the MSB on the address bus. Thus creating a shadow memory 41area. As a general rule, 0x00000000-0x7fffffff is cached, whereas 420x80000000-0xffffffff is not cached and used to access IO devices. This 43behaviour can be enabled with: 44 cpu_lm32_set_phys_msb_ignore(env, 1); 45 46