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19#include "qemu/osdep.h"
20#include "cpu.h"
21#include "exec/exec-all.h"
22#include "exec/helper-proto.h"
23
24#include "helper_regs.h"
25
26
27
28void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
29{
30 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
31 env->spr[sprn]);
32}
33
34void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
35{
36 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
37 env->spr[sprn]);
38}
39
40#ifdef TARGET_PPC64
41static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
42 uint32_t sprn, uint32_t cause,
43 uintptr_t raddr)
44{
45 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
46
47 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
48 cause &= FSCR_IC_MASK;
49 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
50
51 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
52}
53#endif
54
55void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
56 uint32_t sprn, uint32_t cause)
57{
58#ifdef TARGET_PPC64
59 if (env->spr[SPR_FSCR] & (1ULL << bit)) {
60
61 return;
62 }
63 raise_fu_exception(env, bit, sprn, cause, GETPC());
64#endif
65}
66
67void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
68 uint32_t sprn, uint32_t cause)
69{
70#ifdef TARGET_PPC64
71 if (env->msr & (1ULL << bit)) {
72
73 return;
74 }
75 raise_fu_exception(env, bit, sprn, cause, GETPC());
76#endif
77}
78
79#if !defined(CONFIG_USER_ONLY)
80
81void helper_store_sdr1(CPUPPCState *env, target_ulong val)
82{
83 PowerPCCPU *cpu = ppc_env_get_cpu(env);
84
85 if (env->spr[SPR_SDR1] != val) {
86 ppc_store_sdr1(env, val);
87 tlb_flush(CPU(cpu));
88 }
89}
90
91void helper_store_pidr(CPUPPCState *env, target_ulong val)
92{
93 PowerPCCPU *cpu = ppc_env_get_cpu(env);
94
95 env->spr[SPR_BOOKS_PID] = val;
96 tlb_flush(CPU(cpu));
97}
98
99void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
100{
101 target_ulong hid0;
102
103 hid0 = env->spr[SPR_HID0];
104 if ((val ^ hid0) & 0x00000008) {
105
106 env->hflags &= ~(1 << MSR_LE);
107 env->hflags_nmsr &= ~(1 << MSR_LE);
108 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
109 env->hflags |= env->hflags_nmsr;
110 qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
111 val & 0x8 ? 'l' : 'b', env->hflags);
112 }
113 env->spr[SPR_HID0] = (uint32_t)val;
114}
115
116void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
117{
118 PowerPCCPU *cpu = ppc_env_get_cpu(env);
119
120 if (likely(env->pb[num] != value)) {
121 env->pb[num] = value;
122
123 tlb_flush(CPU(cpu));
124 }
125}
126
127void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
128{
129 store_40x_dbcr0(env, val);
130}
131
132void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
133{
134 store_40x_sler(env, val);
135}
136#endif
137
138
139
140target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
141{
142 switch (arg) {
143 case 0x0CUL:
144
145 return env->icache_line_size;
146 break;
147 case 0x0DUL:
148
149 return env->dcache_line_size;
150 break;
151 case 0x0EUL:
152
153 return (env->icache_line_size < env->dcache_line_size) ?
154 env->icache_line_size : env->dcache_line_size;
155 break;
156 case 0x0FUL:
157
158 return (env->icache_line_size > env->dcache_line_size) ?
159 env->icache_line_size : env->dcache_line_size;
160 break;
161 default:
162
163 return 0;
164 break;
165 }
166}
167
168
169
170
171
172void ppc_store_msr(CPUPPCState *env, target_ulong value)
173{
174 hreg_store_msr(env, value, 0);
175}
176
177
178
179
180
181
182void helper_fixup_thrm(CPUPPCState *env)
183{
184 target_ulong v, t;
185 int i;
186
187#define THRM1_TIN (1 << 31)
188#define THRM1_TIV (1 << 30)
189#define THRM1_THRES(x) (((x) & 0x7f) << 23)
190#define THRM1_TID (1 << 2)
191#define THRM1_TIE (1 << 1)
192#define THRM1_V (1 << 0)
193#define THRM3_E (1 << 0)
194
195 if (!(env->spr[SPR_THRM3] & THRM3_E)) {
196 return;
197 }
198
199
200 for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
201 v = env->spr[i];
202 if (!(v & THRM1_V)) {
203 continue;
204 }
205 v |= THRM1_TIV;
206 v &= ~THRM1_TIN;
207 t = v & THRM1_THRES(127);
208 if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
209 v |= THRM1_TIN;
210 }
211 if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
212 v |= THRM1_TIN;
213 }
214 env->spr[i] = v;
215 }
216}
217