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28#ifndef XTENSA_CPU_H
29#define XTENSA_CPU_H
30
31#define ALIGNED_ONLY
32#define TARGET_LONG_BITS 32
33
34
35#define TCG_GUEST_DEFAULT_MO (0)
36
37#define CPUArchState struct CPUXtensaState
38
39#include "qemu-common.h"
40#include "cpu-qom.h"
41#include "exec/cpu-defs.h"
42#include "xtensa-isa.h"
43
44#define NB_MMU_MODES 4
45
46#define TARGET_PHYS_ADDR_SPACE_BITS 32
47#ifdef CONFIG_USER_ONLY
48#define TARGET_VIRT_ADDR_SPACE_BITS 30
49#else
50#define TARGET_VIRT_ADDR_SPACE_BITS 32
51#endif
52#define TARGET_PAGE_BITS 12
53
54enum {
55
56 XTENSA_OPTION_CODE_DENSITY,
57 XTENSA_OPTION_LOOP,
58 XTENSA_OPTION_EXTENDED_L32R,
59 XTENSA_OPTION_16_BIT_IMUL,
60 XTENSA_OPTION_32_BIT_IMUL,
61 XTENSA_OPTION_32_BIT_IMUL_HIGH,
62 XTENSA_OPTION_32_BIT_IDIV,
63 XTENSA_OPTION_MAC16,
64 XTENSA_OPTION_MISC_OP_NSA,
65 XTENSA_OPTION_MISC_OP_MINMAX,
66 XTENSA_OPTION_MISC_OP_SEXT,
67 XTENSA_OPTION_MISC_OP_CLAMPS,
68 XTENSA_OPTION_COPROCESSOR,
69 XTENSA_OPTION_BOOLEAN,
70 XTENSA_OPTION_FP_COPROCESSOR,
71 XTENSA_OPTION_MP_SYNCHRO,
72 XTENSA_OPTION_CONDITIONAL_STORE,
73 XTENSA_OPTION_ATOMCTL,
74 XTENSA_OPTION_DEPBITS,
75
76
77 XTENSA_OPTION_EXCEPTION,
78 XTENSA_OPTION_RELOCATABLE_VECTOR,
79 XTENSA_OPTION_UNALIGNED_EXCEPTION,
80 XTENSA_OPTION_INTERRUPT,
81 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
82 XTENSA_OPTION_TIMER_INTERRUPT,
83
84
85 XTENSA_OPTION_ICACHE,
86 XTENSA_OPTION_ICACHE_TEST,
87 XTENSA_OPTION_ICACHE_INDEX_LOCK,
88 XTENSA_OPTION_DCACHE,
89 XTENSA_OPTION_DCACHE_TEST,
90 XTENSA_OPTION_DCACHE_INDEX_LOCK,
91 XTENSA_OPTION_IRAM,
92 XTENSA_OPTION_IROM,
93 XTENSA_OPTION_DRAM,
94 XTENSA_OPTION_DROM,
95 XTENSA_OPTION_XLMI,
96 XTENSA_OPTION_HW_ALIGNMENT,
97 XTENSA_OPTION_MEMORY_ECC_PARITY,
98
99
100 XTENSA_OPTION_REGION_PROTECTION,
101 XTENSA_OPTION_REGION_TRANSLATION,
102 XTENSA_OPTION_MMU,
103 XTENSA_OPTION_CACHEATTR,
104
105
106 XTENSA_OPTION_WINDOWED_REGISTER,
107 XTENSA_OPTION_PROCESSOR_INTERFACE,
108 XTENSA_OPTION_MISC_SR,
109 XTENSA_OPTION_THREAD_POINTER,
110 XTENSA_OPTION_PROCESSOR_ID,
111 XTENSA_OPTION_DEBUG,
112 XTENSA_OPTION_TRACE_PORT,
113 XTENSA_OPTION_EXTERN_REGS,
114};
115
116enum {
117 EXPSTATE = 230,
118 THREADPTR = 231,
119 FCR = 232,
120 FSR = 233,
121};
122
123enum {
124 LBEG = 0,
125 LEND = 1,
126 LCOUNT = 2,
127 SAR = 3,
128 BR = 4,
129 LITBASE = 5,
130 SCOMPARE1 = 12,
131 ACCLO = 16,
132 ACCHI = 17,
133 MR = 32,
134 WINDOW_BASE = 72,
135 WINDOW_START = 73,
136 PTEVADDR = 83,
137 MMID = 89,
138 RASID = 90,
139 ITLBCFG = 91,
140 DTLBCFG = 92,
141 IBREAKENABLE = 96,
142 MEMCTL = 97,
143 CACHEATTR = 98,
144 ATOMCTL = 99,
145 DDR = 104,
146 IBREAKA = 128,
147 DBREAKA = 144,
148 DBREAKC = 160,
149 CONFIGID0 = 176,
150 EPC1 = 177,
151 DEPC = 192,
152 EPS2 = 194,
153 CONFIGID1 = 208,
154 EXCSAVE1 = 209,
155 CPENABLE = 224,
156 INTSET = 226,
157 INTCLEAR = 227,
158 INTENABLE = 228,
159 PS = 230,
160 VECBASE = 231,
161 EXCCAUSE = 232,
162 DEBUGCAUSE = 233,
163 CCOUNT = 234,
164 PRID = 235,
165 ICOUNT = 236,
166 ICOUNTLEVEL = 237,
167 EXCVADDR = 238,
168 CCOMPARE = 240,
169 MISC = 244,
170};
171
172#define PS_INTLEVEL 0xf
173#define PS_INTLEVEL_SHIFT 0
174
175#define PS_EXCM 0x10
176#define PS_UM 0x20
177
178#define PS_RING 0xc0
179#define PS_RING_SHIFT 6
180
181#define PS_OWB 0xf00
182#define PS_OWB_SHIFT 8
183#define PS_OWB_LEN 4
184
185#define PS_CALLINC 0x30000
186#define PS_CALLINC_SHIFT 16
187#define PS_CALLINC_LEN 2
188
189#define PS_WOE 0x40000
190
191#define DEBUGCAUSE_IC 0x1
192#define DEBUGCAUSE_IB 0x2
193#define DEBUGCAUSE_DB 0x4
194#define DEBUGCAUSE_BI 0x8
195#define DEBUGCAUSE_BN 0x10
196#define DEBUGCAUSE_DI 0x20
197#define DEBUGCAUSE_DBNUM 0xf00
198#define DEBUGCAUSE_DBNUM_SHIFT 8
199
200#define DBREAKC_SB 0x80000000
201#define DBREAKC_LB 0x40000000
202#define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
203#define DBREAKC_MASK 0x3f
204
205#define MEMCTL_INIT 0x00800000
206#define MEMCTL_IUSEWAYS_SHIFT 18
207#define MEMCTL_IUSEWAYS_LEN 5
208#define MEMCTL_IUSEWAYS_MASK 0x007c0000
209#define MEMCTL_DALLOCWAYS_SHIFT 13
210#define MEMCTL_DALLOCWAYS_LEN 5
211#define MEMCTL_DALLOCWAYS_MASK 0x0003e000
212#define MEMCTL_DUSEWAYS_SHIFT 8
213#define MEMCTL_DUSEWAYS_LEN 5
214#define MEMCTL_DUSEWAYS_MASK 0x00001f00
215#define MEMCTL_ISNP 0x4
216#define MEMCTL_DSNP 0x2
217#define MEMCTL_IL0EN 0x1
218
219#define MAX_INSN_LENGTH 64
220#define MAX_OPCODE_ARGS 16
221#define MAX_NAREG 64
222#define MAX_NINTERRUPT 32
223#define MAX_NLEVEL 6
224#define MAX_NNMI 1
225#define MAX_NCCOMPARE 3
226#define MAX_TLB_WAY_SIZE 8
227#define MAX_NDBREAK 2
228#define MAX_NMEMORY 4
229
230#define REGION_PAGE_MASK 0xe0000000
231
232#define PAGE_CACHE_MASK 0x700
233#define PAGE_CACHE_SHIFT 8
234#define PAGE_CACHE_INVALID 0x000
235#define PAGE_CACHE_BYPASS 0x100
236#define PAGE_CACHE_WT 0x200
237#define PAGE_CACHE_WB 0x400
238#define PAGE_CACHE_ISOLATE 0x600
239
240enum {
241
242 EXC_RESET0,
243 EXC_RESET1,
244 EXC_MEMORY_ERROR,
245
246
247 EXC_WINDOW_OVERFLOW4,
248 EXC_WINDOW_UNDERFLOW4,
249 EXC_WINDOW_OVERFLOW8,
250 EXC_WINDOW_UNDERFLOW8,
251 EXC_WINDOW_OVERFLOW12,
252 EXC_WINDOW_UNDERFLOW12,
253 EXC_IRQ,
254 EXC_KERNEL,
255 EXC_USER,
256 EXC_DOUBLE,
257 EXC_DEBUG,
258 EXC_MAX
259};
260
261enum {
262 ILLEGAL_INSTRUCTION_CAUSE = 0,
263 SYSCALL_CAUSE,
264 INSTRUCTION_FETCH_ERROR_CAUSE,
265 LOAD_STORE_ERROR_CAUSE,
266 LEVEL1_INTERRUPT_CAUSE,
267 ALLOCA_CAUSE,
268 INTEGER_DIVIDE_BY_ZERO_CAUSE,
269 PRIVILEGED_CAUSE = 8,
270 LOAD_STORE_ALIGNMENT_CAUSE,
271
272 INSTR_PIF_DATA_ERROR_CAUSE = 12,
273 LOAD_STORE_PIF_DATA_ERROR_CAUSE,
274 INSTR_PIF_ADDR_ERROR_CAUSE,
275 LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
276
277 INST_TLB_MISS_CAUSE,
278 INST_TLB_MULTI_HIT_CAUSE,
279 INST_FETCH_PRIVILEGE_CAUSE,
280 INST_FETCH_PROHIBITED_CAUSE = 20,
281 LOAD_STORE_TLB_MISS_CAUSE = 24,
282 LOAD_STORE_TLB_MULTI_HIT_CAUSE,
283 LOAD_STORE_PRIVILEGE_CAUSE,
284 LOAD_PROHIBITED_CAUSE = 28,
285 STORE_PROHIBITED_CAUSE,
286
287 COPROCESSOR0_DISABLED = 32,
288};
289
290typedef enum {
291 INTTYPE_LEVEL,
292 INTTYPE_EDGE,
293 INTTYPE_NMI,
294 INTTYPE_SOFTWARE,
295 INTTYPE_TIMER,
296 INTTYPE_DEBUG,
297 INTTYPE_WRITE_ERR,
298 INTTYPE_PROFILING,
299 INTTYPE_MAX
300} interrupt_type;
301
302struct CPUXtensaState;
303
304typedef struct xtensa_tlb_entry {
305 uint32_t vaddr;
306 uint32_t paddr;
307 uint8_t asid;
308 uint8_t attr;
309 bool variable;
310} xtensa_tlb_entry;
311
312typedef struct xtensa_tlb {
313 unsigned nways;
314 const unsigned way_size[10];
315 bool varway56;
316 unsigned nrefillentries;
317} xtensa_tlb;
318
319typedef struct XtensaGdbReg {
320 int targno;
321 unsigned flags;
322 int type;
323 int group;
324 unsigned size;
325} XtensaGdbReg;
326
327typedef struct XtensaGdbRegmap {
328 int num_regs;
329 int num_core_regs;
330
331 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
332} XtensaGdbRegmap;
333
334typedef struct XtensaCcompareTimer {
335 struct CPUXtensaState *env;
336 QEMUTimer *timer;
337} XtensaCcompareTimer;
338
339typedef struct XtensaMemory {
340 unsigned num;
341 struct XtensaMemoryRegion {
342 uint32_t addr;
343 uint32_t size;
344 } location[MAX_NMEMORY];
345} XtensaMemory;
346
347typedef struct DisasContext DisasContext;
348typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
349 const uint32_t par[]);
350
351typedef struct XtensaOpcodeOps {
352 const char *name;
353 XtensaOpcodeOp translate;
354 const uint32_t *par;
355} XtensaOpcodeOps;
356
357typedef struct XtensaOpcodeTranslators {
358 unsigned num_opcodes;
359 const XtensaOpcodeOps *opcode;
360} XtensaOpcodeTranslators;
361
362extern const XtensaOpcodeTranslators xtensa_core_opcodes;
363extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
364
365struct XtensaConfig {
366 const char *name;
367 uint64_t options;
368 XtensaGdbRegmap gdb_regmap;
369 unsigned nareg;
370 int excm_level;
371 int ndepc;
372 uint32_t vecbase;
373 uint32_t exception_vector[EXC_MAX];
374 unsigned ninterrupt;
375 unsigned nlevel;
376 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
377 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
378 uint32_t inttype_mask[INTTYPE_MAX];
379 struct {
380 uint32_t level;
381 interrupt_type inttype;
382 } interrupt[MAX_NINTERRUPT];
383 unsigned nccompare;
384 uint32_t timerint[MAX_NCCOMPARE];
385 unsigned nextint;
386 unsigned extint[MAX_NINTERRUPT];
387
388 unsigned debug_level;
389 unsigned nibreak;
390 unsigned ndbreak;
391
392 unsigned icache_ways;
393 unsigned dcache_ways;
394 uint32_t memctl_mask;
395
396 XtensaMemory instrom;
397 XtensaMemory instram;
398 XtensaMemory datarom;
399 XtensaMemory dataram;
400 XtensaMemory sysrom;
401 XtensaMemory sysram;
402
403 uint32_t configid[2];
404
405 void *isa_internal;
406 xtensa_isa isa;
407 XtensaOpcodeOps **opcode_ops;
408 const XtensaOpcodeTranslators **opcode_translators;
409
410 uint32_t clock_freq_khz;
411
412 xtensa_tlb itlb;
413 xtensa_tlb dtlb;
414};
415
416typedef struct XtensaConfigList {
417 const XtensaConfig *config;
418 struct XtensaConfigList *next;
419} XtensaConfigList;
420
421#ifdef HOST_WORDS_BIGENDIAN
422enum {
423 FP_F32_HIGH,
424 FP_F32_LOW,
425};
426#else
427enum {
428 FP_F32_LOW,
429 FP_F32_HIGH,
430};
431#endif
432
433typedef struct CPUXtensaState {
434 const XtensaConfig *config;
435 uint32_t regs[16];
436 uint32_t pc;
437 uint32_t sregs[256];
438 uint32_t uregs[256];
439 uint32_t phys_regs[MAX_NAREG];
440 union {
441 float32 f32[2];
442 float64 f64;
443 } fregs[16];
444 float_status fp_status;
445
446#ifndef CONFIG_USER_ONLY
447 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
448 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
449 unsigned autorefill_idx;
450 bool runstall;
451 AddressSpace *address_space_er;
452 MemoryRegion *system_er;
453 int pending_irq_level;
454 void **irq_inputs;
455 XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
456 uint64_t time_base;
457 uint64_t ccount_time;
458 uint32_t ccount_base;
459#endif
460
461 int exception_taken;
462 int yield_needed;
463 unsigned static_vectors;
464
465
466 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
467
468 CPU_COMMON
469} CPUXtensaState;
470
471
472
473
474
475
476
477struct XtensaCPU {
478
479 CPUState parent_obj;
480
481
482 CPUXtensaState env;
483};
484
485static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
486{
487 return container_of(env, XtensaCPU, env);
488}
489
490#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
491
492#define ENV_OFFSET offsetof(XtensaCPU, env)
493
494
495int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
496 int mmu_idx);
497void xtensa_cpu_do_interrupt(CPUState *cpu);
498bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
499void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
500 bool is_write, bool is_exec, int opaque,
501 unsigned size);
502void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
503 fprintf_function cpu_fprintf, int flags);
504hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
505int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
506int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
507void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
508 MMUAccessType access_type,
509 int mmu_idx, uintptr_t retaddr);
510
511#define cpu_signal_handler cpu_xtensa_signal_handler
512#define cpu_list xtensa_cpu_list
513
514#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
515#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
516#define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
517
518#ifdef TARGET_WORDS_BIGENDIAN
519#define XTENSA_DEFAULT_CPU_MODEL "fsf"
520#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
521#else
522#define XTENSA_DEFAULT_CPU_MODEL "dc232b"
523#define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
524#endif
525#define XTENSA_DEFAULT_CPU_TYPE \
526 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
527#define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
528 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
529
530void xtensa_translate_init(void);
531void xtensa_breakpoint_handler(CPUState *cs);
532void xtensa_finalize_config(XtensaConfig *config);
533void xtensa_register_core(XtensaConfigList *node);
534void xtensa_sim_open_console(Chardev *chr);
535void check_interrupts(CPUXtensaState *s);
536void xtensa_irq_init(CPUXtensaState *env);
537void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
538void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
539int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
540void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
541void xtensa_sync_window_from_phys(CPUXtensaState *env);
542void xtensa_sync_phys_from_window(CPUXtensaState *env);
543void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta);
544void xtensa_restore_owb(CPUXtensaState *env);
545void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
546
547static inline void xtensa_select_static_vectors(CPUXtensaState *env,
548 unsigned n)
549{
550 assert(n < 2);
551 env->static_vectors = n;
552}
553void xtensa_runstall(CPUXtensaState *env, bool runstall);
554XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
555 const char *opcode);
556
557#define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
558#define XTENSA_OPTION_ALL (~(uint64_t)0)
559
560static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
561 uint64_t opt)
562{
563 return (config->options & opt) != 0;
564}
565
566static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
567{
568 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
569}
570
571static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
572{
573 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
574 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
575 level = env->config->excm_level;
576 }
577 return level;
578}
579
580static inline int xtensa_get_ring(const CPUXtensaState *env)
581{
582 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
583 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
584 } else {
585 return 0;
586 }
587}
588
589static inline int xtensa_get_cring(const CPUXtensaState *env)
590{
591 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
592 (env->sregs[PS] & PS_EXCM) == 0) {
593 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
594 } else {
595 return 0;
596 }
597}
598
599#ifndef CONFIG_USER_ONLY
600uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env,
601 bool dtlb, uint32_t way);
602void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
603 uint32_t *vpn, uint32_t wi, uint32_t *ei);
604int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
605 uint32_t *pwi, uint32_t *pei, uint8_t *pring);
606void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
607 xtensa_tlb_entry *entry, bool dtlb,
608 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
609void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
610 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
611int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
612 uint32_t vaddr, int is_write, int mmu_idx,
613 uint32_t *paddr, uint32_t *page_size, unsigned *access);
614void reset_mmu(CPUXtensaState *env);
615void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
616
617static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
618{
619 return env->system_er;
620}
621
622static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
623 bool dtlb, unsigned wi, unsigned ei)
624{
625 return dtlb ?
626 env->dtlb[wi] + ei :
627 env->itlb[wi] + ei;
628}
629#endif
630
631static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
632{
633 return env->sregs[WINDOW_START] |
634 (env->sregs[WINDOW_START] << env->config->nareg / 4);
635}
636
637
638#define MMU_MODE0_SUFFIX _ring0
639#define MMU_MODE1_SUFFIX _ring1
640#define MMU_MODE2_SUFFIX _ring2
641#define MMU_MODE3_SUFFIX _ring3
642#define MMU_USER_IDX 3
643
644static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
645{
646 return xtensa_get_cring(env);
647}
648
649#define XTENSA_TBFLAG_RING_MASK 0x3
650#define XTENSA_TBFLAG_EXCM 0x4
651#define XTENSA_TBFLAG_LITBASE 0x8
652#define XTENSA_TBFLAG_DEBUG 0x10
653#define XTENSA_TBFLAG_ICOUNT 0x20
654#define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
655#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
656#define XTENSA_TBFLAG_EXCEPTION 0x4000
657#define XTENSA_TBFLAG_WINDOW_MASK 0x18000
658#define XTENSA_TBFLAG_WINDOW_SHIFT 15
659#define XTENSA_TBFLAG_YIELD 0x20000
660
661static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
662 target_ulong *cs_base, uint32_t *flags)
663{
664 CPUState *cs = CPU(xtensa_env_get_cpu(env));
665
666 *pc = env->pc;
667 *cs_base = 0;
668 *flags = 0;
669 *flags |= xtensa_get_ring(env);
670 if (env->sregs[PS] & PS_EXCM) {
671 *flags |= XTENSA_TBFLAG_EXCM;
672 }
673 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
674 (env->sregs[LITBASE] & 1)) {
675 *flags |= XTENSA_TBFLAG_LITBASE;
676 }
677 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
678 if (xtensa_get_cintlevel(env) < env->config->debug_level) {
679 *flags |= XTENSA_TBFLAG_DEBUG;
680 }
681 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
682 *flags |= XTENSA_TBFLAG_ICOUNT;
683 }
684 }
685 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
686 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
687 }
688 if (cs->singlestep_enabled && env->exception_taken) {
689 *flags |= XTENSA_TBFLAG_EXCEPTION;
690 }
691 if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
692 (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
693 uint32_t windowstart = xtensa_replicate_windowstart(env) >>
694 (env->sregs[WINDOW_BASE] + 1);
695 uint32_t w = ctz32(windowstart | 0x8);
696
697 *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
698 } else {
699 *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
700 }
701 if (env->yield_needed) {
702 *flags |= XTENSA_TBFLAG_YIELD;
703 }
704}
705
706#include "exec/cpu-all.h"
707
708#endif
709
