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10#include "qemu/osdep.h"
11#include "qemu/error-report.h"
12#include "qapi/error.h"
13#include <libfdt.h>
14#include "hw/hw.h"
15#include "hw/arm/arm.h"
16#include "hw/arm/linux-boot-if.h"
17#include "sysemu/kvm.h"
18#include "sysemu/sysemu.h"
19#include "sysemu/numa.h"
20#include "hw/boards.h"
21#include "hw/loader.h"
22#include "elf.h"
23#include "sysemu/device_tree.h"
24#include "qemu/config-file.h"
25#include "qemu/option.h"
26#include "exec/address-spaces.h"
27
28
29
30
31
32#define KERNEL_ARGS_ADDR 0x100
33#define KERNEL_LOAD_ADDR 0x00010000
34#define KERNEL64_LOAD_ADDR 0x00080000
35
36#define ARM64_TEXT_OFFSET_OFFSET 8
37#define ARM64_MAGIC_OFFSET 56
38
39static AddressSpace *arm_boot_address_space(ARMCPU *cpu,
40 const struct arm_boot_info *info)
41{
42
43
44
45
46 int asidx;
47 CPUState *cs = CPU(cpu);
48
49 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) {
50 asidx = ARMASIdx_S;
51 } else {
52 asidx = ARMASIdx_NS;
53 }
54
55 return cpu_get_address_space(cs, asidx);
56}
57
58typedef enum {
59 FIXUP_NONE = 0,
60 FIXUP_TERMINATOR,
61 FIXUP_BOARDID,
62 FIXUP_BOARD_SETUP,
63 FIXUP_ARGPTR,
64 FIXUP_ENTRYPOINT,
65 FIXUP_GIC_CPU_IF,
66 FIXUP_BOOTREG,
67 FIXUP_DSB,
68 FIXUP_MAX,
69} FixupType;
70
71typedef struct ARMInsnFixup {
72 uint32_t insn;
73 FixupType fixup;
74} ARMInsnFixup;
75
76static const ARMInsnFixup bootloader_aarch64[] = {
77 { 0x580000c0 },
78 { 0xaa1f03e1 },
79 { 0xaa1f03e2 },
80 { 0xaa1f03e3 },
81 { 0x58000084 },
82 { 0xd61f0080 },
83 { 0, FIXUP_ARGPTR },
84 { 0 },
85 { 0, FIXUP_ENTRYPOINT },
86 { 0 },
87 { 0, FIXUP_TERMINATOR }
88};
89
90
91
92
93
94
95
96static const ARMInsnFixup bootloader[] = {
97 { 0xe28fe004 },
98 { 0xe51ff004 },
99 { 0, FIXUP_BOARD_SETUP },
100#define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
101 { 0xe3a00000 },
102 { 0xe59f1004 },
103 { 0xe59f2004 },
104 { 0xe59ff004 },
105 { 0, FIXUP_BOARDID },
106 { 0, FIXUP_ARGPTR },
107 { 0, FIXUP_ENTRYPOINT },
108 { 0, FIXUP_TERMINATOR }
109};
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125#define DSB_INSN 0xf57ff04f
126#define CP15_DSB_INSN 0xee070f9a
127
128static const ARMInsnFixup smpboot[] = {
129 { 0xe59f2028 },
130 { 0xe59f0028 },
131 { 0xe3a01001 },
132 { 0xe5821000 },
133 { 0xe3a010ff },
134 { 0xe5821004 },
135 { 0, FIXUP_DSB },
136 { 0xe320f003 },
137 { 0xe5901000 },
138 { 0xe1110001 },
139 { 0x0afffffb },
140 { 0xe12fff11 },
141 { 0, FIXUP_GIC_CPU_IF },
142 { 0, FIXUP_BOOTREG },
143 { 0, FIXUP_TERMINATOR }
144};
145
146static void write_bootloader(const char *name, hwaddr addr,
147 const ARMInsnFixup *insns, uint32_t *fixupcontext,
148 AddressSpace *as)
149{
150
151
152
153
154
155 int i, len;
156 uint32_t *code;
157
158 len = 0;
159 while (insns[len].fixup != FIXUP_TERMINATOR) {
160 len++;
161 }
162
163 code = g_new0(uint32_t, len);
164
165 for (i = 0; i < len; i++) {
166 uint32_t insn = insns[i].insn;
167 FixupType fixup = insns[i].fixup;
168
169 switch (fixup) {
170 case FIXUP_NONE:
171 break;
172 case FIXUP_BOARDID:
173 case FIXUP_BOARD_SETUP:
174 case FIXUP_ARGPTR:
175 case FIXUP_ENTRYPOINT:
176 case FIXUP_GIC_CPU_IF:
177 case FIXUP_BOOTREG:
178 case FIXUP_DSB:
179 insn = fixupcontext[fixup];
180 break;
181 default:
182 abort();
183 }
184 code[i] = tswap32(insn);
185 }
186
187 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
188
189 g_free(code);
190}
191
192static void default_write_secondary(ARMCPU *cpu,
193 const struct arm_boot_info *info)
194{
195 uint32_t fixupcontext[FIXUP_MAX];
196 AddressSpace *as = arm_boot_address_space(cpu, info);
197
198 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
199 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
200 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
201 fixupcontext[FIXUP_DSB] = DSB_INSN;
202 } else {
203 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
204 }
205
206 write_bootloader("smpboot", info->smp_loader_start,
207 smpboot, fixupcontext, as);
208}
209
210void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
211 const struct arm_boot_info *info,
212 hwaddr mvbar_addr)
213{
214 AddressSpace *as = arm_boot_address_space(cpu, info);
215 int n;
216 uint32_t mvbar_blob[] = {
217
218
219
220
221 0xeafffffe,
222 0xeafffffe,
223 0xe1b0f00e,
224 0xeafffffe,
225 0xeafffffe,
226 0xeafffffe,
227 0xeafffffe,
228 0xeafffffe,
229 };
230 uint32_t board_setup_blob[] = {
231
232 0xe3a00e00 + (mvbar_addr >> 4),
233 0xee0c0f30,
234 0xee110f11,
235 0xe3800031,
236 0xee010f11,
237 0xe1a0100e,
238 0xe1600070,
239 0xe1a0f001,
240 };
241
242
243 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100);
244
245
246 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr)
247 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr));
248
249 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {
250 mvbar_blob[n] = tswap32(mvbar_blob[n]);
251 }
252 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),
253 mvbar_addr, as);
254
255 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
256 board_setup_blob[n] = tswap32(board_setup_blob[n]);
257 }
258 rom_add_blob_fixed_as("board-setup", board_setup_blob,
259 sizeof(board_setup_blob), info->board_setup_addr, as);
260}
261
262static void default_reset_secondary(ARMCPU *cpu,
263 const struct arm_boot_info *info)
264{
265 AddressSpace *as = arm_boot_address_space(cpu, info);
266 CPUState *cs = CPU(cpu);
267
268 address_space_stl_notdirty(as, info->smp_bootreg_addr,
269 0, MEMTXATTRS_UNSPECIFIED, NULL);
270 cpu_set_pc(cs, info->smp_loader_start);
271}
272
273static inline bool have_dtb(const struct arm_boot_info *info)
274{
275 return info->dtb_filename || info->get_dtb;
276}
277
278#define WRITE_WORD(p, value) do { \
279 address_space_stl_notdirty(as, p, value, \
280 MEMTXATTRS_UNSPECIFIED, NULL); \
281 p += 4; \
282} while (0)
283
284static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
285{
286 int initrd_size = info->initrd_size;
287 hwaddr base = info->loader_start;
288 hwaddr p;
289
290 p = base + KERNEL_ARGS_ADDR;
291
292 WRITE_WORD(p, 5);
293 WRITE_WORD(p, 0x54410001);
294 WRITE_WORD(p, 1);
295 WRITE_WORD(p, 0x1000);
296 WRITE_WORD(p, 0);
297
298
299 WRITE_WORD(p, 4);
300 WRITE_WORD(p, 0x54410002);
301 WRITE_WORD(p, info->ram_size);
302 WRITE_WORD(p, info->loader_start);
303 if (initrd_size) {
304
305 WRITE_WORD(p, 4);
306 WRITE_WORD(p, 0x54420005);
307 WRITE_WORD(p, info->initrd_start);
308 WRITE_WORD(p, initrd_size);
309 }
310 if (info->kernel_cmdline && *info->kernel_cmdline) {
311
312 int cmdline_size;
313
314 cmdline_size = strlen(info->kernel_cmdline);
315 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
316 (const uint8_t *)info->kernel_cmdline,
317 cmdline_size + 1);
318 cmdline_size = (cmdline_size >> 2) + 1;
319 WRITE_WORD(p, cmdline_size + 2);
320 WRITE_WORD(p, 0x54410009);
321 p += cmdline_size * 4;
322 }
323 if (info->atag_board) {
324
325 int atag_board_len;
326 uint8_t atag_board_buf[0x1000];
327
328 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
329 WRITE_WORD(p, (atag_board_len + 8) >> 2);
330 WRITE_WORD(p, 0x414f4d50);
331 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
332 atag_board_buf, atag_board_len);
333 p += atag_board_len;
334 }
335
336 WRITE_WORD(p, 0);
337 WRITE_WORD(p, 0);
338}
339
340static void set_kernel_args_old(const struct arm_boot_info *info,
341 AddressSpace *as)
342{
343 hwaddr p;
344 const char *s;
345 int initrd_size = info->initrd_size;
346 hwaddr base = info->loader_start;
347
348
349 p = base + KERNEL_ARGS_ADDR;
350
351 WRITE_WORD(p, 4096);
352
353 WRITE_WORD(p, info->ram_size / 4096);
354
355 WRITE_WORD(p, 0);
356#define FLAG_READONLY 1
357#define FLAG_RDLOAD 4
358#define FLAG_RDPROMPT 8
359
360 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
361
362 WRITE_WORD(p, (31 << 8) | 0);
363
364 WRITE_WORD(p, 0);
365
366 WRITE_WORD(p, 0);
367
368 WRITE_WORD(p, 0);
369
370 WRITE_WORD(p, 0);
371
372 WRITE_WORD(p, 0);
373
374
375
376
377 WRITE_WORD(p, 0);
378
379 WRITE_WORD(p, 0);
380 WRITE_WORD(p, 0);
381 WRITE_WORD(p, 0);
382 WRITE_WORD(p, 0);
383
384 WRITE_WORD(p, 0);
385
386 if (initrd_size) {
387 WRITE_WORD(p, info->initrd_start);
388 } else {
389 WRITE_WORD(p, 0);
390 }
391
392 WRITE_WORD(p, initrd_size);
393
394 WRITE_WORD(p, 0);
395
396 WRITE_WORD(p, 0);
397
398 WRITE_WORD(p, 0);
399
400 WRITE_WORD(p, 0);
401
402 WRITE_WORD(p, 0);
403
404 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
405 WRITE_WORD(p, 0);
406 }
407 s = info->kernel_cmdline;
408 if (s) {
409 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
410 (const uint8_t *)s, strlen(s) + 1);
411 } else {
412 WRITE_WORD(p, 0);
413 }
414}
415
416static void fdt_add_psci_node(void *fdt)
417{
418 uint32_t cpu_suspend_fn;
419 uint32_t cpu_off_fn;
420 uint32_t cpu_on_fn;
421 uint32_t migrate_fn;
422 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
423 const char *psci_method;
424 int64_t psci_conduit;
425 int rc;
426
427 psci_conduit = object_property_get_int(OBJECT(armcpu),
428 "psci-conduit",
429 &error_abort);
430 switch (psci_conduit) {
431 case QEMU_PSCI_CONDUIT_DISABLED:
432 return;
433 case QEMU_PSCI_CONDUIT_HVC:
434 psci_method = "hvc";
435 break;
436 case QEMU_PSCI_CONDUIT_SMC:
437 psci_method = "smc";
438 break;
439 default:
440 g_assert_not_reached();
441 }
442
443
444
445
446
447 rc = fdt_path_offset(fdt, "/psci");
448 if (rc >= 0) {
449 return;
450 }
451
452 qemu_fdt_add_subnode(fdt, "/psci");
453 if (armcpu->psci_version == 2) {
454 const char comp[] = "arm,psci-0.2\0arm,psci";
455 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
456
457 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
458 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
459 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
460 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
461 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
462 } else {
463 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
464 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
465 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
466 }
467 } else {
468 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
469
470 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
471 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
472 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
473 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
474 }
475
476
477
478
479
480
481 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
482
483 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
484 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
485 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
486 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
487}
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510static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
511 hwaddr addr_limit, AddressSpace *as)
512{
513 void *fdt = NULL;
514 int size, rc;
515 uint32_t acells, scells;
516 char *nodename;
517 unsigned int i;
518 hwaddr mem_base, mem_len;
519
520 if (binfo->dtb_filename) {
521 char *filename;
522 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
523 if (!filename) {
524 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
525 goto fail;
526 }
527
528 fdt = load_device_tree(filename, &size);
529 if (!fdt) {
530 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
531 g_free(filename);
532 goto fail;
533 }
534 g_free(filename);
535 } else {
536 fdt = binfo->get_dtb(binfo, &size);
537 if (!fdt) {
538 fprintf(stderr, "Board was unable to create a dtb blob\n");
539 goto fail;
540 }
541 }
542
543 if (addr_limit > addr && size > (addr_limit - addr)) {
544
545
546
547
548 g_free(fdt);
549 return 0;
550 }
551
552 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
553 NULL, &error_fatal);
554 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
555 NULL, &error_fatal);
556 if (acells == 0 || scells == 0) {
557 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
558 goto fail;
559 }
560
561 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
562
563
564
565 fprintf(stderr, "qemu: dtb file not compatible with "
566 "RAM size > 4GB\n");
567 goto fail;
568 }
569
570 if (nb_numa_nodes > 0) {
571
572
573
574
575 qemu_fdt_nop_node(fdt, "/memory");
576 mem_base = binfo->loader_start;
577 for (i = 0; i < nb_numa_nodes; i++) {
578 mem_len = numa_info[i].node_mem;
579 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
580 qemu_fdt_add_subnode(fdt, nodename);
581 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
582 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
583 acells, mem_base,
584 scells, mem_len);
585 if (rc < 0) {
586 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename,
587 i);
588 goto fail;
589 }
590
591 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i);
592 mem_base += mem_len;
593 g_free(nodename);
594 }
595 } else {
596 Error *err = NULL;
597
598 rc = fdt_path_offset(fdt, "/memory");
599 if (rc < 0) {
600 qemu_fdt_add_subnode(fdt, "/memory");
601 }
602
603 if (!qemu_fdt_getprop(fdt, "/memory", "device_type", NULL, &err)) {
604 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
605 }
606
607 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
608 acells, binfo->loader_start,
609 scells, binfo->ram_size);
610 if (rc < 0) {
611 fprintf(stderr, "couldn't set /memory/reg\n");
612 goto fail;
613 }
614 }
615
616 rc = fdt_path_offset(fdt, "/chosen");
617 if (rc < 0) {
618 qemu_fdt_add_subnode(fdt, "/chosen");
619 }
620
621 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
622 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
623 binfo->kernel_cmdline);
624 if (rc < 0) {
625 fprintf(stderr, "couldn't set /chosen/bootargs\n");
626 goto fail;
627 }
628 }
629
630 if (binfo->initrd_size) {
631 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
632 binfo->initrd_start);
633 if (rc < 0) {
634 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
635 goto fail;
636 }
637
638 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
639 binfo->initrd_start + binfo->initrd_size);
640 if (rc < 0) {
641 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
642 goto fail;
643 }
644 }
645
646 fdt_add_psci_node(fdt);
647
648 if (binfo->modify_dtb) {
649 binfo->modify_dtb(binfo, fdt);
650 }
651
652 qemu_fdt_dumpdtb(fdt, size);
653
654
655
656
657 rom_add_blob_fixed_as("dtb", fdt, size, addr, as);
658
659 g_free(fdt);
660
661 return size;
662
663fail:
664 g_free(fdt);
665 return -1;
666}
667
668static void do_cpu_reset(void *opaque)
669{
670 ARMCPU *cpu = opaque;
671 CPUState *cs = CPU(cpu);
672 CPUARMState *env = &cpu->env;
673 const struct arm_boot_info *info = env->boot_info;
674
675 cpu_reset(cs);
676 if (info) {
677 if (!info->is_linux) {
678 int i;
679
680 uint64_t entry = info->entry;
681
682 switch (info->endianness) {
683 case ARM_ENDIANNESS_LE:
684 env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
685 for (i = 1; i < 4; ++i) {
686 env->cp15.sctlr_el[i] &= ~SCTLR_EE;
687 }
688 env->uncached_cpsr &= ~CPSR_E;
689 break;
690 case ARM_ENDIANNESS_BE8:
691 env->cp15.sctlr_el[1] |= SCTLR_E0E;
692 for (i = 1; i < 4; ++i) {
693 env->cp15.sctlr_el[i] |= SCTLR_EE;
694 }
695 env->uncached_cpsr |= CPSR_E;
696 break;
697 case ARM_ENDIANNESS_BE32:
698 env->cp15.sctlr_el[1] |= SCTLR_B;
699 break;
700 case ARM_ENDIANNESS_UNKNOWN:
701 break;
702 default:
703 g_assert_not_reached();
704 }
705
706 if (!env->aarch64) {
707 env->thumb = info->entry & 1;
708 entry &= 0xfffffffe;
709 }
710 cpu_set_pc(cs, entry);
711 } else {
712
713
714
715
716
717
718 if (arm_feature(env, ARM_FEATURE_EL3)) {
719
720
721
722
723
724
725 if (env->aarch64) {
726 env->cp15.scr_el3 |= SCR_RW;
727 if (arm_feature(env, ARM_FEATURE_EL2)) {
728 env->cp15.hcr_el2 |= HCR_RW;
729 env->pstate = PSTATE_MODE_EL2h;
730 } else {
731 env->pstate = PSTATE_MODE_EL1h;
732 }
733
734 assert(!info->secure_boot);
735
736
737
738
739 assert(!info->secure_board_setup);
740 }
741
742 if (arm_feature(env, ARM_FEATURE_EL2)) {
743
744 env->cp15.scr_el3 |= SCR_HCE;
745 }
746
747
748 if (!info->secure_boot &&
749 (cs != first_cpu || !info->secure_board_setup)) {
750
751 env->cp15.scr_el3 |= SCR_NS;
752 }
753 }
754
755 if (cs == first_cpu) {
756 AddressSpace *as = arm_boot_address_space(cpu, info);
757
758 cpu_set_pc(cs, info->loader_start);
759
760 if (!have_dtb(info)) {
761 if (old_param) {
762 set_kernel_args_old(info, as);
763 } else {
764 set_kernel_args(info, as);
765 }
766 }
767 } else {
768 info->secondary_cpu_reset_hook(cpu, info);
769 }
770 }
771 }
772}
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791static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
792 uint16_t data_key, const char *image_name,
793 bool try_decompress)
794{
795 size_t size = -1;
796 uint8_t *data;
797
798 if (image_name == NULL) {
799 return;
800 }
801
802 if (try_decompress) {
803 size = load_image_gzipped_buffer(image_name,
804 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
805 }
806
807 if (size == (size_t)-1) {
808 gchar *contents;
809 gsize length;
810
811 if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
812 error_report("failed to load \"%s\"", image_name);
813 exit(1);
814 }
815 size = length;
816 data = (uint8_t *)contents;
817 }
818
819 fw_cfg_add_i32(fw_cfg, size_key, size);
820 fw_cfg_add_bytes(fw_cfg, data_key, data, size);
821}
822
823static int do_arm_linux_init(Object *obj, void *opaque)
824{
825 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
826 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
827 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
828 struct arm_boot_info *info = opaque;
829
830 if (albifc->arm_linux_init) {
831 albifc->arm_linux_init(albif, info->secure_boot);
832 }
833 }
834 return 0;
835}
836
837static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
838 uint64_t *lowaddr, uint64_t *highaddr,
839 int elf_machine, AddressSpace *as)
840{
841 bool elf_is64;
842 union {
843 Elf32_Ehdr h32;
844 Elf64_Ehdr h64;
845 } elf_header;
846 int data_swab = 0;
847 bool big_endian;
848 uint64_t ret = -1;
849 Error *err = NULL;
850
851
852 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
853 if (err) {
854 error_free(err);
855 return ret;
856 }
857
858 if (elf_is64) {
859 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB;
860 info->endianness = big_endian ? ARM_ENDIANNESS_BE8
861 : ARM_ENDIANNESS_LE;
862 } else {
863 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB;
864 if (big_endian) {
865 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) {
866 info->endianness = ARM_ENDIANNESS_BE8;
867 } else {
868 info->endianness = ARM_ENDIANNESS_BE32;
869
870
871
872
873
874
875
876 data_swab = 2;
877 }
878 } else {
879 info->endianness = ARM_ENDIANNESS_LE;
880 }
881 }
882
883 ret = load_elf_as(info->kernel_filename, NULL, NULL,
884 pentry, lowaddr, highaddr, big_endian, elf_machine,
885 1, data_swab, as);
886 if (ret <= 0) {
887
888 exit(1);
889 }
890
891 return ret;
892}
893
894static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
895 hwaddr *entry, AddressSpace *as)
896{
897 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
898 uint8_t *buffer;
899 int size;
900
901
902 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
903 &buffer);
904
905 if (size < 0) {
906 gsize len;
907
908
909 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
910 return -1;
911 }
912 size = len;
913 }
914
915
916 if (size > ARM64_MAGIC_OFFSET + 4 &&
917 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
918 uint64_t hdrvals[2];
919
920
921
922
923
924 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
925 if (hdrvals[1] != 0) {
926 kernel_load_offset = le64_to_cpu(hdrvals[0]);
927 }
928 }
929
930 *entry = mem_base + kernel_load_offset;
931 rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
932
933 g_free(buffer);
934
935 return size;
936}
937
938static void arm_load_kernel_notify(Notifier *notifier, void *data)
939{
940 CPUState *cs;
941 int kernel_size;
942 int initrd_size;
943 int is_linux = 0;
944 uint64_t elf_entry, elf_low_addr, elf_high_addr;
945 int elf_machine;
946 hwaddr entry;
947 static const ARMInsnFixup *primary_loader;
948 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
949 notifier, notifier);
950 ARMCPU *cpu = n->cpu;
951 struct arm_boot_info *info =
952 container_of(n, struct arm_boot_info, load_kernel_notifier);
953 AddressSpace *as = arm_boot_address_space(cpu, info);
954
955
956
957
958
959 assert(!(info->secure_board_setup && kvm_enabled()));
960
961 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
962
963
964 if (!info->kernel_filename || info->firmware_loaded) {
965
966 if (have_dtb(info)) {
967
968
969
970
971 if (load_dtb(info->loader_start, info, 0, as) < 0) {
972 exit(1);
973 }
974 }
975
976 if (info->kernel_filename) {
977 FWCfgState *fw_cfg;
978 bool try_decompressing_kernel;
979
980 fw_cfg = fw_cfg_find();
981 try_decompressing_kernel = arm_feature(&cpu->env,
982 ARM_FEATURE_AARCH64);
983
984
985
986
987
988 load_image_to_fw_cfg(fw_cfg,
989 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
990 info->kernel_filename,
991 try_decompressing_kernel);
992 load_image_to_fw_cfg(fw_cfg,
993 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
994 info->initrd_filename, false);
995
996 if (info->kernel_cmdline) {
997 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
998 strlen(info->kernel_cmdline) + 1);
999 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
1000 info->kernel_cmdline);
1001 }
1002 }
1003
1004
1005
1006
1007 return;
1008 }
1009
1010 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1011 primary_loader = bootloader_aarch64;
1012 elf_machine = EM_AARCH64;
1013 } else {
1014 primary_loader = bootloader;
1015 if (!info->write_board_setup) {
1016 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
1017 }
1018 elf_machine = EM_ARM;
1019 }
1020
1021 if (!info->secondary_cpu_reset_hook) {
1022 info->secondary_cpu_reset_hook = default_reset_secondary;
1023 }
1024 if (!info->write_secondary_boot) {
1025 info->write_secondary_boot = default_write_secondary;
1026 }
1027
1028 if (info->nb_cpus == 0)
1029 info->nb_cpus = 1;
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041 info->initrd_start = info->loader_start +
1042 MIN(info->ram_size / 2, 128 * 1024 * 1024);
1043
1044
1045 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr,
1046 &elf_high_addr, elf_machine, as);
1047 if (kernel_size > 0 && have_dtb(info)) {
1048
1049
1050
1051 if (elf_low_addr > info->loader_start
1052 || elf_high_addr < info->loader_start) {
1053
1054
1055
1056 if (elf_low_addr < info->loader_start) {
1057 elf_low_addr = 0;
1058 }
1059 if (load_dtb(info->loader_start, info, elf_low_addr, as) < 0) {
1060 exit(1);
1061 }
1062 }
1063 }
1064 entry = elf_entry;
1065 if (kernel_size < 0) {
1066 kernel_size = load_uimage_as(info->kernel_filename, &entry, NULL,
1067 &is_linux, NULL, NULL, as);
1068 }
1069 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
1070 kernel_size = load_aarch64_image(info->kernel_filename,
1071 info->loader_start, &entry, as);
1072 is_linux = 1;
1073 } else if (kernel_size < 0) {
1074
1075 entry = info->loader_start + KERNEL_LOAD_ADDR;
1076 kernel_size = load_image_targphys_as(info->kernel_filename, entry,
1077 info->ram_size - KERNEL_LOAD_ADDR,
1078 as);
1079 is_linux = 1;
1080 }
1081 if (kernel_size < 0) {
1082 error_report("could not load kernel '%s'", info->kernel_filename);
1083 exit(1);
1084 }
1085 info->entry = entry;
1086 if (is_linux) {
1087 uint32_t fixupcontext[FIXUP_MAX];
1088
1089 if (info->initrd_filename) {
1090 initrd_size = load_ramdisk_as(info->initrd_filename,
1091 info->initrd_start,
1092 info->ram_size - info->initrd_start,
1093 as);
1094 if (initrd_size < 0) {
1095 initrd_size = load_image_targphys_as(info->initrd_filename,
1096 info->initrd_start,
1097 info->ram_size -
1098 info->initrd_start,
1099 as);
1100 }
1101 if (initrd_size < 0) {
1102 error_report("could not load initrd '%s'",
1103 info->initrd_filename);
1104 exit(1);
1105 }
1106 } else {
1107 initrd_size = 0;
1108 }
1109 info->initrd_size = initrd_size;
1110
1111 fixupcontext[FIXUP_BOARDID] = info->board_id;
1112 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;
1113
1114
1115
1116
1117 if (have_dtb(info)) {
1118 hwaddr align;
1119 hwaddr dtb_start;
1120
1121 if (elf_machine == EM_AARCH64) {
1122
1123
1124
1125
1126
1127
1128
1129 align = 2 * 1024 * 1024;
1130 } else {
1131
1132
1133
1134
1135 align = 4096;
1136 }
1137
1138
1139 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align);
1140 if (load_dtb(dtb_start, info, 0, as) < 0) {
1141 exit(1);
1142 }
1143 fixupcontext[FIXUP_ARGPTR] = dtb_start;
1144 } else {
1145 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR;
1146 if (info->ram_size >= (1ULL << 32)) {
1147 error_report("RAM size must be less than 4GB to boot"
1148 " Linux kernel using ATAGS (try passing a device tree"
1149 " using -dtb)");
1150 exit(1);
1151 }
1152 }
1153 fixupcontext[FIXUP_ENTRYPOINT] = entry;
1154
1155 write_bootloader("bootloader", info->loader_start,
1156 primary_loader, fixupcontext, as);
1157
1158 if (info->nb_cpus > 1) {
1159 info->write_secondary_boot(cpu, info);
1160 }
1161 if (info->write_board_setup) {
1162 info->write_board_setup(cpu, info);
1163 }
1164
1165
1166
1167
1168 object_child_foreach_recursive(object_get_root(),
1169 do_arm_linux_init, info);
1170 }
1171 info->is_linux = is_linux;
1172
1173 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
1174 ARM_CPU(cs)->env.boot_info = info;
1175 }
1176}
1177
1178void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
1179{
1180 CPUState *cs;
1181
1182 info->load_kernel_notifier.cpu = cpu;
1183 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify;
1184 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier);
1185
1186
1187
1188
1189
1190
1191 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
1192 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
1193 }
1194}
1195
1196static const TypeInfo arm_linux_boot_if_info = {
1197 .name = TYPE_ARM_LINUX_BOOT_IF,
1198 .parent = TYPE_INTERFACE,
1199 .class_size = sizeof(ARMLinuxBootIfClass),
1200};
1201
1202static void arm_linux_boot_register_types(void)
1203{
1204 type_register_static(&arm_linux_boot_if_info);
1205}
1206
1207type_init(arm_linux_boot_register_types)
1208