LXR qemu/hw/arm/mainstone.c

   1/*
   2 * PXA270-based Intel Mainstone platforms.
   3 *
   4 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
   5 *                                    <akuster@mvista.com>
   6 *
   7 * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
   8 *
   9 * This code is licensed under the GNU GPL v2.
  10 *
  11 * Contributions after 2012-01-13 are licensed under the terms of the
  12 * GNU GPL, version 2 or (at your option) any later version.
  13 */
  14#include "qemu/osdep.h"
  15#include "qemu/error-report.h"
  16#include "qapi/error.h"
  17#include "hw/hw.h"
  18#include "hw/arm/pxa.h"
  19#include "hw/arm/arm.h"
  20#include "net/net.h"
  21#include "hw/devices.h"
  22#include "hw/boards.h"
  23#include "hw/block/flash.h"
  24#include "sysemu/block-backend.h"
  25#include "hw/sysbus.h"
  26#include "exec/address-spaces.h"
  27#include "sysemu/qtest.h"
  28#include "cpu.h"
  29
  30/* Device addresses */
  31#define MST_FPGA_PHYS   0x08000000
  32#define MST_ETH_PHYS    0x10000300
  33#define MST_FLASH_0             0x00000000
  34#define MST_FLASH_1             0x04000000
  35
  36/* IRQ definitions */
  37#define MMC_IRQ       0
  38#define USIM_IRQ      1
  39#define USBC_IRQ      2
  40#define ETHERNET_IRQ  3
  41#define AC97_IRQ      4
  42#define PEN_IRQ       5
  43#define MSINS_IRQ     6
  44#define EXBRD_IRQ     7
  45#define S0_CD_IRQ     9
  46#define S0_STSCHG_IRQ 10
  47#define S0_IRQ        11
  48#define S1_CD_IRQ     13
  49#define S1_STSCHG_IRQ 14
  50#define S1_IRQ        15
  51
  52static const struct keymap map[0xE0] = {
  53    [0 ... 0xDF] = { -1, -1 },
  54    [0x1e] = {0,0}, /* a */
  55    [0x30] = {0,1}, /* b */
  56    [0x2e] = {0,2}, /* c */
  57    [0x20] = {0,3}, /* d */
  58    [0x12] = {0,4}, /* e */
  59    [0x21] = {0,5}, /* f */
  60    [0x22] = {1,0}, /* g */
  61    [0x23] = {1,1}, /* h */
  62    [0x17] = {1,2}, /* i */
  63    [0x24] = {1,3}, /* j */
  64    [0x25] = {1,4}, /* k */
  65    [0x26] = {1,5}, /* l */
  66    [0x32] = {2,0}, /* m */
  67    [0x31] = {2,1}, /* n */
  68    [0x18] = {2,2}, /* o */
  69    [0x19] = {2,3}, /* p */
  70    [0x10] = {2,4}, /* q */
  71    [0x13] = {2,5}, /* r */
  72    [0x1f] = {3,0}, /* s */
  73    [0x14] = {3,1}, /* t */
  74    [0x16] = {3,2}, /* u */
  75    [0x2f] = {3,3}, /* v */
  76    [0x11] = {3,4}, /* w */
  77    [0x2d] = {3,5}, /* x */
  78    [0x34] = {4,0}, /* . */
  79    [0x15] = {4,2}, /* y */
  80    [0x2c] = {4,3}, /* z */
  81    [0x35] = {4,4}, /* / */
  82    [0xc7] = {5,0}, /* Home */
  83    [0x2a] = {5,1}, /* shift */
  84    /*
  85     * There are two matrix positions which map to space,
  86     * but QEMU can only use one of them for the reverse
  87     * mapping, so simply use the second one.
  88     */
  89    /* [0x39] = {5,2}, space */
  90    [0x39] = {5,3}, /* space */
  91    /*
  92     * Matrix position {5,4} and other keys are missing here.
  93     * TODO: Compare with Linux code and test real hardware.
  94     */
  95    [0x1c] = {5,4}, /* enter */
  96    [0x0e] = {5,5}, /* backspace */
  97    [0xc8] = {6,0}, /* up */
  98    [0xd0] = {6,1}, /* down */
  99    [0xcb] = {6,2}, /* left */
 100    [0xcd] = {6,3}, /* right */
 101};
 102
 103enum mainstone_model_e { mainstone };
 104
 105#define MAINSTONE_RAM   0x04000000
 106#define MAINSTONE_ROM   0x00800000
 107#define MAINSTONE_FLASH 0x02000000
 108
 109static struct arm_boot_info mainstone_binfo = {
 110    .loader_start = PXA2XX_SDRAM_BASE,
 111    .ram_size = 0x04000000,
 112};
 113
 114static void mainstone_common_init(MemoryRegion *address_space_mem,
 115                                  MachineState *machine,
 116                                  enum mainstone_model_e model, int arm_id)
 117{
 118    uint32_t sector_len = 256 * 1024;
 119    hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
 120    PXA2xxState *mpu;
 121    DeviceState *mst_irq;
 122    DriveInfo *dinfo;
 123    int i;
 124    int be;
 125    MemoryRegion *rom = g_new(MemoryRegion, 1);
 126
 127    /* Setup CPU & memory */
 128    mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
 129                      machine->cpu_type);
 130    memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
 131                           &error_fatal);
 132    memory_region_set_readonly(rom, true);
 133    memory_region_add_subregion(address_space_mem, 0, rom);
 134
 135#ifdef TARGET_WORDS_BIGENDIAN
 136    be = 1;
 137#else
 138    be = 0;
 139#endif
 140    /* There are two 32MiB flash devices on the board */
 141    for (i = 0; i < 2; i ++) {
 142        dinfo = drive_get(IF_PFLASH, 0, i);
 143        if (!dinfo) {
 144            if (qtest_enabled()) {
 145                break;
 146            }
 147            error_report("Two flash images must be given with the "
 148                         "'pflash' parameter");
 149            exit(1);
 150        }
 151
 152        if (!pflash_cfi01_register(mainstone_flash_base[i], NULL,
 153                                   i ? "mainstone.flash1" : "mainstone.flash0",
 154                                   MAINSTONE_FLASH,
 155                                   blk_by_legacy_dinfo(dinfo),
 156                                   sector_len, MAINSTONE_FLASH / sector_len,
 157                                   4, 0, 0, 0, 0, be)) {
 158            error_report("Error registering flash memory");
 159            exit(1);
 160        }
 161    }
 162
 163    mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
 164                    qdev_get_gpio_in(mpu->gpio, 0));
 165
 166    /* setup keypad */
 167    pxa27x_register_keypad(mpu->kp, map, 0xe0);
 168
 169    /* MMC/SD host */
 170    pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
 171
 172    pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
 173            qdev_get_gpio_in(mst_irq, S0_IRQ),
 174            qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
 175    pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
 176            qdev_get_gpio_in(mst_irq, S1_IRQ),
 177            qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
 178
 179    smc91c111_init(&nd_table[0], MST_ETH_PHYS,
 180                    qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
 181
 182    mainstone_binfo.kernel_filename = machine->kernel_filename;
 183    mainstone_binfo.kernel_cmdline = machine->kernel_cmdline;
 184    mainstone_binfo.initrd_filename = machine->initrd_filename;
 185    mainstone_binfo.board_id = arm_id;
 186    arm_load_kernel(mpu->cpu, &mainstone_binfo);
 187}
 188
 189static void mainstone_init(MachineState *machine)
 190{
 191    mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
 192}
 193
 194static void mainstone2_machine_init(MachineClass *mc)
 195{
 196    mc->desc = "Mainstone II (PXA27x)";
 197    mc->init = mainstone_init;
 198    mc->ignore_memory_transaction_failures = true;
 199    mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
 200}
 201
 202DEFINE_MACHINE("mainstone", mainstone2_machine_init)
 203