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28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "hw/hw.h"
31#include "ui/console.h"
32#include "hw/arm/omap.h"
33#include "hw/boards.h"
34#include "hw/arm/arm.h"
35#include "hw/block/flash.h"
36#include "sysemu/block-backend.h"
37#include "sysemu/qtest.h"
38#include "exec/address-spaces.h"
39#include "cpu.h"
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66static uint64_t static_read(void *opaque, hwaddr offset,
67 unsigned size)
68{
69 uint32_t *val = (uint32_t *) opaque;
70 uint32_t mask = (4 / size) - 1;
71
72 return *val >> ((offset & mask) << 3);
73}
74
75static void static_write(void *opaque, hwaddr offset,
76 uint64_t value, unsigned size)
77{
78#ifdef SPY
79 printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n",
80 __func__, value, size, (int)offset);
81#endif
82}
83
84static const MemoryRegionOps static_ops = {
85 .read = static_read,
86 .write = static_write,
87 .endianness = DEVICE_NATIVE_ENDIAN,
88};
89
90#define sdram_size 0x02000000
91#define sector_size (128 * 1024)
92#define flash0_size (16 * 1024 * 1024)
93#define flash1_size ( 8 * 1024 * 1024)
94#define flash2_size (32 * 1024 * 1024)
95#define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
96#define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
97
98static struct arm_boot_info sx1_binfo = {
99 .loader_start = OMAP_EMIFF_BASE,
100 .ram_size = sdram_size,
101 .board_id = 0x265,
102};
103
104static void sx1_init(MachineState *machine, const int version)
105{
106 struct omap_mpu_state_s *mpu;
107 MemoryRegion *address_space = get_system_memory();
108 MemoryRegion *flash = g_new(MemoryRegion, 1);
109 MemoryRegion *cs = g_new(MemoryRegion, 4);
110 static uint32_t cs0val = 0x00213090;
111 static uint32_t cs1val = 0x00215070;
112 static uint32_t cs2val = 0x00001139;
113 static uint32_t cs3val = 0x00001139;
114 DriveInfo *dinfo;
115 int fl_idx;
116 uint32_t flash_size = flash0_size;
117 int be;
118
119 if (version == 2) {
120 flash_size = flash2_size;
121 }
122
123 mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
124 machine->cpu_type);
125
126
127 memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
128 &error_fatal);
129 memory_region_set_readonly(flash, true);
130 memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
131
132 memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,
133 "sx1.cs0", OMAP_CS0_SIZE - flash_size);
134 memory_region_add_subregion(address_space,
135 OMAP_CS0_BASE + flash_size, &cs[0]);
136
137
138 memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val,
139 "sx1.cs2", OMAP_CS2_SIZE);
140 memory_region_add_subregion(address_space,
141 OMAP_CS2_BASE, &cs[2]);
142
143 memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val,
144 "sx1.cs3", OMAP_CS3_SIZE);
145 memory_region_add_subregion(address_space,
146 OMAP_CS2_BASE, &cs[3]);
147
148 fl_idx = 0;
149#ifdef TARGET_WORDS_BIGENDIAN
150 be = 1;
151#else
152 be = 0;
153#endif
154
155 if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
156 if (!pflash_cfi01_register(OMAP_CS0_BASE, NULL,
157 "omap_sx1.flash0-1", flash_size,
158 blk_by_legacy_dinfo(dinfo),
159 sector_size, flash_size / sector_size,
160 4, 0, 0, 0, 0, be)) {
161 fprintf(stderr, "qemu: Error registering flash memory %d.\n",
162 fl_idx);
163 }
164 fl_idx++;
165 }
166
167 if ((version == 1) &&
168 (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
169 MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
170 memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0",
171 flash1_size, &error_fatal);
172 memory_region_set_readonly(flash_1, true);
173 memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
174
175 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
176 "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
177 memory_region_add_subregion(address_space,
178 OMAP_CS1_BASE + flash1_size, &cs[1]);
179
180 if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL,
181 "omap_sx1.flash1-1", flash1_size,
182 blk_by_legacy_dinfo(dinfo),
183 sector_size, flash1_size / sector_size,
184 4, 0, 0, 0, 0, be)) {
185 fprintf(stderr, "qemu: Error registering flash memory %d.\n",
186 fl_idx);
187 }
188 fl_idx++;
189 } else {
190 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
191 "sx1.cs1", OMAP_CS1_SIZE);
192 memory_region_add_subregion(address_space,
193 OMAP_CS1_BASE, &cs[1]);
194 }
195
196 if (!machine->kernel_filename && !fl_idx && !qtest_enabled()) {
197 error_report("Kernel or Flash image must be specified");
198 exit(1);
199 }
200
201
202 sx1_binfo.kernel_filename = machine->kernel_filename;
203 sx1_binfo.kernel_cmdline = machine->kernel_cmdline;
204 sx1_binfo.initrd_filename = machine->initrd_filename;
205 arm_load_kernel(mpu->cpu, &sx1_binfo);
206
207
208
209}
210
211static void sx1_init_v1(MachineState *machine)
212{
213 sx1_init(machine, 1);
214}
215
216static void sx1_init_v2(MachineState *machine)
217{
218 sx1_init(machine, 2);
219}
220
221static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
222{
223 MachineClass *mc = MACHINE_CLASS(oc);
224
225 mc->desc = "Siemens SX1 (OMAP310) V2";
226 mc->init = sx1_init_v2;
227 mc->ignore_memory_transaction_failures = true;
228 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
229}
230
231static const TypeInfo sx1_machine_v2_type = {
232 .name = MACHINE_TYPE_NAME("sx1"),
233 .parent = TYPE_MACHINE,
234 .class_init = sx1_machine_v2_class_init,
235};
236
237static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
238{
239 MachineClass *mc = MACHINE_CLASS(oc);
240
241 mc->desc = "Siemens SX1 (OMAP310) V1";
242 mc->init = sx1_init_v1;
243 mc->ignore_memory_transaction_failures = true;
244 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
245}
246
247static const TypeInfo sx1_machine_v1_type = {
248 .name = MACHINE_TYPE_NAME("sx1-v1"),
249 .parent = TYPE_MACHINE,
250 .class_init = sx1_machine_v1_class_init,
251};
252
253static void sx1_machine_init(void)
254{
255 type_register_static(&sx1_machine_v1_type);
256 type_register_static(&sx1_machine_v2_type);
257}
258
259type_init(sx1_machine_init)
260