1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu-common.h"
27#include "cpu.h"
28#include "hw/sysbus.h"
29#include "hw/arm/arm.h"
30#include "hw/arm/primecell.h"
31#include "hw/devices.h"
32#include "hw/i2c/i2c.h"
33#include "net/net.h"
34#include "sysemu/sysemu.h"
35#include "hw/boards.h"
36#include "hw/loader.h"
37#include "exec/address-spaces.h"
38#include "sysemu/block-backend.h"
39#include "hw/block/flash.h"
40#include "sysemu/device_tree.h"
41#include "qemu/error-report.h"
42#include <libfdt.h>
43#include "hw/char/pl011.h"
44#include "hw/cpu/a9mpcore.h"
45#include "hw/cpu/a15mpcore.h"
46
47#define VEXPRESS_BOARD_ID 0x8e0
48#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
49#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
50
51
52
53
54#define NUM_VIRTIO_TRANSPORTS 4
55
56
57
58
59
60
61
62
63
64enum {
65 VE_SYSREGS,
66 VE_SP810,
67 VE_SERIALPCI,
68 VE_PL041,
69 VE_MMCI,
70 VE_KMI0,
71 VE_KMI1,
72 VE_UART0,
73 VE_UART1,
74 VE_UART2,
75 VE_UART3,
76 VE_WDT,
77 VE_TIMER01,
78 VE_TIMER23,
79 VE_SERIALDVI,
80 VE_RTC,
81 VE_COMPACTFLASH,
82 VE_CLCD,
83 VE_NORFLASH0,
84 VE_NORFLASH1,
85 VE_NORFLASHALIAS,
86 VE_SRAM,
87 VE_VIDEORAM,
88 VE_ETHERNET,
89 VE_USB,
90 VE_DAPROM,
91 VE_VIRTIO,
92};
93
94static hwaddr motherboard_legacy_map[] = {
95 [VE_NORFLASHALIAS] = 0,
96
97 [VE_SYSREGS] = 0x10000000,
98 [VE_SP810] = 0x10001000,
99 [VE_SERIALPCI] = 0x10002000,
100 [VE_PL041] = 0x10004000,
101 [VE_MMCI] = 0x10005000,
102 [VE_KMI0] = 0x10006000,
103 [VE_KMI1] = 0x10007000,
104 [VE_UART0] = 0x10009000,
105 [VE_UART1] = 0x1000a000,
106 [VE_UART2] = 0x1000b000,
107 [VE_UART3] = 0x1000c000,
108 [VE_WDT] = 0x1000f000,
109 [VE_TIMER01] = 0x10011000,
110 [VE_TIMER23] = 0x10012000,
111 [VE_VIRTIO] = 0x10013000,
112 [VE_SERIALDVI] = 0x10016000,
113 [VE_RTC] = 0x10017000,
114 [VE_COMPACTFLASH] = 0x1001a000,
115 [VE_CLCD] = 0x1001f000,
116
117 [VE_NORFLASH0] = 0x40000000,
118
119 [VE_NORFLASH1] = 0x44000000,
120
121 [VE_SRAM] = 0x48000000,
122
123 [VE_VIDEORAM] = 0x4c000000,
124 [VE_ETHERNET] = 0x4e000000,
125 [VE_USB] = 0x4f000000,
126};
127
128static hwaddr motherboard_aseries_map[] = {
129 [VE_NORFLASHALIAS] = 0,
130
131 [VE_NORFLASH0] = 0x08000000,
132
133 [VE_NORFLASH1] = 0x0c000000,
134
135
136 [VE_SRAM] = 0x14000000,
137
138 [VE_VIDEORAM] = 0x18000000,
139 [VE_ETHERNET] = 0x1a000000,
140 [VE_USB] = 0x1b000000,
141
142 [VE_DAPROM] = 0x1c000000,
143 [VE_SYSREGS] = 0x1c010000,
144 [VE_SP810] = 0x1c020000,
145 [VE_SERIALPCI] = 0x1c030000,
146 [VE_PL041] = 0x1c040000,
147 [VE_MMCI] = 0x1c050000,
148 [VE_KMI0] = 0x1c060000,
149 [VE_KMI1] = 0x1c070000,
150 [VE_UART0] = 0x1c090000,
151 [VE_UART1] = 0x1c0a0000,
152 [VE_UART2] = 0x1c0b0000,
153 [VE_UART3] = 0x1c0c0000,
154 [VE_WDT] = 0x1c0f0000,
155 [VE_TIMER01] = 0x1c110000,
156 [VE_TIMER23] = 0x1c120000,
157 [VE_VIRTIO] = 0x1c130000,
158 [VE_SERIALDVI] = 0x1c160000,
159 [VE_RTC] = 0x1c170000,
160 [VE_COMPACTFLASH] = 0x1c1a0000,
161 [VE_CLCD] = 0x1c1f0000,
162};
163
164
165
166typedef struct VEDBoardInfo VEDBoardInfo;
167
168typedef struct {
169 MachineClass parent;
170 VEDBoardInfo *daughterboard;
171} VexpressMachineClass;
172
173typedef struct {
174 MachineState parent;
175 bool secure;
176} VexpressMachineState;
177
178#define TYPE_VEXPRESS_MACHINE "vexpress"
179#define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
180#define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
181#define VEXPRESS_MACHINE(obj) \
182 OBJECT_CHECK(VexpressMachineState, (obj), TYPE_VEXPRESS_MACHINE)
183#define VEXPRESS_MACHINE_GET_CLASS(obj) \
184 OBJECT_GET_CLASS(VexpressMachineClass, obj, TYPE_VEXPRESS_MACHINE)
185#define VEXPRESS_MACHINE_CLASS(klass) \
186 OBJECT_CLASS_CHECK(VexpressMachineClass, klass, TYPE_VEXPRESS_MACHINE)
187
188typedef void DBoardInitFn(const VexpressMachineState *machine,
189 ram_addr_t ram_size,
190 const char *cpu_type,
191 qemu_irq *pic);
192
193struct VEDBoardInfo {
194 struct arm_boot_info bootinfo;
195 const hwaddr *motherboard_map;
196 hwaddr loader_start;
197 const hwaddr gic_cpu_if_addr;
198 uint32_t proc_id;
199 uint32_t num_voltage_sensors;
200 const uint32_t *voltages;
201 uint32_t num_clocks;
202 const uint32_t *clocks;
203 DBoardInitFn *init;
204};
205
206static void init_cpus(const char *cpu_type, const char *privdev,
207 hwaddr periphbase, qemu_irq *pic, bool secure)
208{
209 DeviceState *dev;
210 SysBusDevice *busdev;
211 int n;
212
213
214 for (n = 0; n < smp_cpus; n++) {
215 Object *cpuobj = object_new(cpu_type);
216
217 if (!secure) {
218 object_property_set_bool(cpuobj, false, "has_el3", NULL);
219 }
220
221 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
222 object_property_set_int(cpuobj, periphbase,
223 "reset-cbar", &error_abort);
224 }
225 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
226 }
227
228
229
230
231
232 dev = qdev_create(NULL, privdev);
233 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
234 qdev_init_nofail(dev);
235 busdev = SYS_BUS_DEVICE(dev);
236 sysbus_mmio_map(busdev, 0, periphbase);
237
238
239
240
241
242
243
244 for (n = 0; n < 64; n++) {
245 pic[n] = qdev_get_gpio_in(dev, n);
246 }
247
248
249 for (n = 0; n < smp_cpus; n++) {
250 DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
251
252 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
253 sysbus_connect_irq(busdev, n + smp_cpus,
254 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
255 }
256}
257
258static void a9_daughterboard_init(const VexpressMachineState *vms,
259 ram_addr_t ram_size,
260 const char *cpu_type,
261 qemu_irq *pic)
262{
263 MemoryRegion *sysmem = get_system_memory();
264 MemoryRegion *ram = g_new(MemoryRegion, 1);
265 MemoryRegion *lowram = g_new(MemoryRegion, 1);
266 ram_addr_t low_ram_size;
267
268 if (ram_size > 0x40000000) {
269
270 error_report("vexpress-a9: cannot model more than 1GB RAM");
271 exit(1);
272 }
273
274 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
275 ram_size);
276 low_ram_size = ram_size;
277 if (low_ram_size > 0x4000000) {
278 low_ram_size = 0x4000000;
279 }
280
281
282
283
284 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size);
285 memory_region_add_subregion(sysmem, 0x0, lowram);
286 memory_region_add_subregion(sysmem, 0x60000000, ram);
287
288
289 init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);
290
291
292
293
294 sysbus_create_simple("pl111", 0x10020000, pic[44]);
295
296
297
298
299
300
301 sysbus_create_simple("sp804", 0x100e4000, pic[48]);
302
303
304
305
306
307
308
309 sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
310}
311
312
313
314
315static const uint32_t a9_voltages[] = {
316 1000000,
317 1000000,
318 1000000,
319 1800000,
320 900000,
321 3300000,
322};
323
324
325static const uint32_t a9_clocks[] = {
326 45000000,
327 23750000,
328 66670000,
329};
330
331static VEDBoardInfo a9_daughterboard = {
332 .motherboard_map = motherboard_legacy_map,
333 .loader_start = 0x60000000,
334 .gic_cpu_if_addr = 0x1e000100,
335 .proc_id = 0x0c000191,
336 .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
337 .voltages = a9_voltages,
338 .num_clocks = ARRAY_SIZE(a9_clocks),
339 .clocks = a9_clocks,
340 .init = a9_daughterboard_init,
341};
342
343static void a15_daughterboard_init(const VexpressMachineState *vms,
344 ram_addr_t ram_size,
345 const char *cpu_type,
346 qemu_irq *pic)
347{
348 MemoryRegion *sysmem = get_system_memory();
349 MemoryRegion *ram = g_new(MemoryRegion, 1);
350 MemoryRegion *sram = g_new(MemoryRegion, 1);
351
352 {
353
354
355
356
357 uint64_t rsz = ram_size;
358 if (rsz > (30ULL * 1024 * 1024 * 1024)) {
359 error_report("vexpress-a15: cannot model more than 30GB RAM");
360 exit(1);
361 }
362 }
363
364 memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem",
365 ram_size);
366
367 memory_region_add_subregion(sysmem, 0x80000000, ram);
368
369
370 init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);
371
372
373
374
375
376
377
378
379
380
381
382 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
383 &error_fatal);
384 memory_region_add_subregion(sysmem, 0x2e000000, sram);
385
386
387
388}
389
390static const uint32_t a15_voltages[] = {
391 900000,
392};
393
394static const uint32_t a15_clocks[] = {
395 60000000,
396 0,
397 0,
398 0,
399 40000000,
400 23750000,
401 50000000,
402 60000000,
403 40000000,
404};
405
406static VEDBoardInfo a15_daughterboard = {
407 .motherboard_map = motherboard_aseries_map,
408 .loader_start = 0x80000000,
409 .gic_cpu_if_addr = 0x2c002000,
410 .proc_id = 0x14000237,
411 .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
412 .voltages = a15_voltages,
413 .num_clocks = ARRAY_SIZE(a15_clocks),
414 .clocks = a15_clocks,
415 .init = a15_daughterboard_init,
416};
417
418static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
419 hwaddr addr, hwaddr size, uint32_t intc,
420 int irq)
421{
422
423
424
425
426
427
428
429
430
431
432
433 int rc;
434 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
435
436 rc = qemu_fdt_add_subnode(fdt, nodename);
437 rc |= qemu_fdt_setprop_string(fdt, nodename,
438 "compatible", "virtio,mmio");
439 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
440 acells, addr, scells, size);
441 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
442 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
443 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
444 g_free(nodename);
445 if (rc) {
446 return -1;
447 }
448 return 0;
449}
450
451static uint32_t find_int_controller(void *fdt)
452{
453
454
455
456
457
458
459 const char *compat = "arm,cortex-a9-gic";
460 int offset;
461
462 offset = fdt_node_offset_by_compatible(fdt, -1, compat);
463 if (offset >= 0) {
464 return fdt_get_phandle(fdt, offset);
465 }
466 return 0;
467}
468
469static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
470{
471 uint32_t acells, scells, intc;
472 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
473
474 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
475 NULL, &error_fatal);
476 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
477 NULL, &error_fatal);
478 intc = find_int_controller(fdt);
479 if (!intc) {
480
481
482
483 warn_report("couldn't find interrupt controller in "
484 "dtb; will not include virtio-mmio devices in the dtb");
485 } else {
486 int i;
487 const hwaddr *map = daughterboard->motherboard_map;
488
489
490
491
492 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
493 add_virtio_mmio_node(fdt, acells, scells,
494 map[VE_VIRTIO] + 0x200 * i,
495 0x200, intc, 40 + i);
496 }
497 }
498}
499
500
501
502
503
504static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name,
505 DriveInfo *di)
506{
507 DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
508
509 if (di) {
510 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di),
511 &error_abort);
512 }
513
514 qdev_prop_set_uint32(dev, "num-blocks",
515 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
516 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
517 qdev_prop_set_uint8(dev, "width", 4);
518 qdev_prop_set_uint8(dev, "device-width", 2);
519 qdev_prop_set_bit(dev, "big-endian", false);
520 qdev_prop_set_uint16(dev, "id0", 0x89);
521 qdev_prop_set_uint16(dev, "id1", 0x18);
522 qdev_prop_set_uint16(dev, "id2", 0x00);
523 qdev_prop_set_uint16(dev, "id3", 0x00);
524 qdev_prop_set_string(dev, "name", name);
525 qdev_init_nofail(dev);
526
527 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
528 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
529}
530
531static void vexpress_common_init(MachineState *machine)
532{
533 VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
534 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
535 VEDBoardInfo *daughterboard = vmc->daughterboard;
536 DeviceState *dev, *sysctl, *pl041;
537 qemu_irq pic[64];
538 uint32_t sys_id;
539 DriveInfo *dinfo;
540 pflash_t *pflash0;
541 I2CBus *i2c;
542 ram_addr_t vram_size, sram_size;
543 MemoryRegion *sysmem = get_system_memory();
544 MemoryRegion *vram = g_new(MemoryRegion, 1);
545 MemoryRegion *sram = g_new(MemoryRegion, 1);
546 MemoryRegion *flashalias = g_new(MemoryRegion, 1);
547 MemoryRegion *flash0mem;
548 const hwaddr *map = daughterboard->motherboard_map;
549 int i;
550
551 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
552
553
554
555
556 if (bios_name) {
557 char *fn;
558 int image_size;
559
560 if (drive_get(IF_PFLASH, 0, 0)) {
561 error_report("The contents of the first flash device may be "
562 "specified with -bios or with -drive if=pflash... "
563 "but you cannot use both options at once");
564 exit(1);
565 }
566 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
567 if (!fn) {
568 error_report("Could not find ROM image '%s'", bios_name);
569 exit(1);
570 }
571 image_size = load_image_targphys(fn, map[VE_NORFLASH0],
572 VEXPRESS_FLASH_SIZE);
573 g_free(fn);
574 if (image_size < 0) {
575 error_report("Could not load ROM image '%s'", bios_name);
576 exit(1);
577 }
578 }
579
580
581
582
583
584 sys_id = 0x1190f500;
585
586 sysctl = qdev_create(NULL, "realview_sysctl");
587 qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
588 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
589 qdev_prop_set_uint32(sysctl, "len-db-voltage",
590 daughterboard->num_voltage_sensors);
591 for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
592 char *propname = g_strdup_printf("db-voltage[%d]", i);
593 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
594 g_free(propname);
595 }
596 qdev_prop_set_uint32(sysctl, "len-db-clock",
597 daughterboard->num_clocks);
598 for (i = 0; i < daughterboard->num_clocks; i++) {
599 char *propname = g_strdup_printf("db-clock[%d]", i);
600 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
601 g_free(propname);
602 }
603 qdev_init_nofail(sysctl);
604 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
605
606
607
608
609 pl041 = qdev_create(NULL, "pl041");
610 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
611 qdev_init_nofail(pl041);
612 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
613 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
614
615 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
616
617 qdev_connect_gpio_out(dev, 0,
618 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
619 qdev_connect_gpio_out(dev, 1,
620 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
621
622 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
623 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
624
625 pl011_create(map[VE_UART0], pic[5], serial_hds[0]);
626 pl011_create(map[VE_UART1], pic[6], serial_hds[1]);
627 pl011_create(map[VE_UART2], pic[7], serial_hds[2]);
628 pl011_create(map[VE_UART3], pic[8], serial_hds[3]);
629
630 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
631 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
632
633 dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL);
634 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
635 i2c_create_slave(i2c, "sii9022", 0x39);
636
637 sysbus_create_simple("pl031", map[VE_RTC], pic[4]);
638
639
640
641 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
642
643 dinfo = drive_get_next(IF_PFLASH);
644 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
645 dinfo);
646 if (!pflash0) {
647 error_report("vexpress: error registering flash 0");
648 exit(1);
649 }
650
651 if (map[VE_NORFLASHALIAS] != -1) {
652
653 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
654 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
655 flash0mem, 0, VEXPRESS_FLASH_SIZE);
656 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
657 }
658
659 dinfo = drive_get_next(IF_PFLASH);
660 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
661 dinfo)) {
662 error_report("vexpress: error registering flash 1");
663 exit(1);
664 }
665
666 sram_size = 0x2000000;
667 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
668 &error_fatal);
669 memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
670
671 vram_size = 0x800000;
672 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
673 &error_fatal);
674 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
675
676
677 if (nd_table[0].used) {
678 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
679 }
680
681
682
683
684
685
686
687
688
689 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
690 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
691 pic[40 + i]);
692 }
693
694 daughterboard->bootinfo.ram_size = machine->ram_size;
695 daughterboard->bootinfo.kernel_filename = machine->kernel_filename;
696 daughterboard->bootinfo.kernel_cmdline = machine->kernel_cmdline;
697 daughterboard->bootinfo.initrd_filename = machine->initrd_filename;
698 daughterboard->bootinfo.nb_cpus = smp_cpus;
699 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
700 daughterboard->bootinfo.loader_start = daughterboard->loader_start;
701 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
702 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
703 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
704 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
705
706 daughterboard->bootinfo.secure_boot = true;
707 arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo);
708}
709
710static bool vexpress_get_secure(Object *obj, Error **errp)
711{
712 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
713
714 return vms->secure;
715}
716
717static void vexpress_set_secure(Object *obj, bool value, Error **errp)
718{
719 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
720
721 vms->secure = value;
722}
723
724static void vexpress_instance_init(Object *obj)
725{
726 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
727
728
729 vms->secure = true;
730 object_property_add_bool(obj, "secure", vexpress_get_secure,
731 vexpress_set_secure, NULL);
732 object_property_set_description(obj, "secure",
733 "Set on/off to enable/disable the ARM "
734 "Security Extensions (TrustZone)",
735 NULL);
736}
737
738static void vexpress_class_init(ObjectClass *oc, void *data)
739{
740 MachineClass *mc = MACHINE_CLASS(oc);
741
742 mc->desc = "ARM Versatile Express";
743 mc->init = vexpress_common_init;
744 mc->max_cpus = 4;
745 mc->ignore_memory_transaction_failures = true;
746}
747
748static void vexpress_a9_class_init(ObjectClass *oc, void *data)
749{
750 MachineClass *mc = MACHINE_CLASS(oc);
751 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
752
753 mc->desc = "ARM Versatile Express for Cortex-A9";
754 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
755
756 vmc->daughterboard = &a9_daughterboard;
757}
758
759static void vexpress_a15_class_init(ObjectClass *oc, void *data)
760{
761 MachineClass *mc = MACHINE_CLASS(oc);
762 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
763
764 mc->desc = "ARM Versatile Express for Cortex-A15";
765 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
766
767 vmc->daughterboard = &a15_daughterboard;
768}
769
770static const TypeInfo vexpress_info = {
771 .name = TYPE_VEXPRESS_MACHINE,
772 .parent = TYPE_MACHINE,
773 .abstract = true,
774 .instance_size = sizeof(VexpressMachineState),
775 .instance_init = vexpress_instance_init,
776 .class_size = sizeof(VexpressMachineClass),
777 .class_init = vexpress_class_init,
778};
779
780static const TypeInfo vexpress_a9_info = {
781 .name = TYPE_VEXPRESS_A9_MACHINE,
782 .parent = TYPE_VEXPRESS_MACHINE,
783 .class_init = vexpress_a9_class_init,
784};
785
786static const TypeInfo vexpress_a15_info = {
787 .name = TYPE_VEXPRESS_A15_MACHINE,
788 .parent = TYPE_VEXPRESS_MACHINE,
789 .class_init = vexpress_a15_class_init,
790};
791
792static void vexpress_machine_init(void)
793{
794 type_register_static(&vexpress_info);
795 type_register_static(&vexpress_a9_info);
796 type_register_static(&vexpress_a15_info);
797}
798
799type_init(vexpress_machine_init);
800