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18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "qemu-common.h"
21#include "cpu.h"
22#include "hw/sysbus.h"
23#include "hw/arm/arm.h"
24#include "net/net.h"
25#include "exec/address-spaces.h"
26#include "sysemu/sysemu.h"
27#include "hw/boards.h"
28#include "hw/block/flash.h"
29#include "sysemu/block-backend.h"
30#include "hw/loader.h"
31#include "hw/misc/zynq-xadc.h"
32#include "hw/ssi/ssi.h"
33#include "qemu/error-report.h"
34#include "hw/sd/sdhci.h"
35#include "hw/char/cadence_uart.h"
36#include "hw/net/cadence_gem.h"
37#include "hw/cpu/a9mpcore.h"
38
39#define NUM_SPI_FLASHES 4
40#define NUM_QSPI_FLASHES 2
41#define NUM_QSPI_BUSSES 2
42
43#define FLASH_SIZE (64 * 1024 * 1024)
44#define FLASH_SECTOR_SIZE (128 * 1024)
45
46#define IRQ_OFFSET 32
47
48#define MPCORE_PERIPHBASE 0xF8F00000
49#define ZYNQ_BOARD_MIDR 0x413FC090
50
51static const int dma_irqs[8] = {
52 46, 47, 48, 49, 72, 73, 74, 75
53};
54
55#define BOARD_SETUP_ADDR 0x100
56
57#define SLCR_LOCK_OFFSET 0x004
58#define SLCR_UNLOCK_OFFSET 0x008
59#define SLCR_ARM_PLL_OFFSET 0x100
60
61#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
62#define SLCR_XILINX_LOCK_KEY 0x767b
63
64#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080
65
66#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
67 extract32((x), 12, 4) << 16)
68
69
70
71
72
73#define SLCR_WRITE(addr, val) \
74 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), \
75 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), \
76 0xe5801000 + (addr)
77
78static void zynq_write_board_setup(ARMCPU *cpu,
79 const struct arm_boot_info *info)
80{
81 int n;
82 uint32_t board_setup_blob[] = {
83 0xe3a004f8,
84 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
85 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
86 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
87 0xe12fff1e,
88 };
89 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
90 board_setup_blob[n] = tswap32(board_setup_blob[n]);
91 }
92 rom_add_blob_fixed("board-setup", board_setup_blob,
93 sizeof(board_setup_blob), BOARD_SETUP_ADDR);
94}
95
96static struct arm_boot_info zynq_binfo = {};
97
98static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
99{
100 DeviceState *dev;
101 SysBusDevice *s;
102
103 dev = qdev_create(NULL, TYPE_CADENCE_GEM);
104 if (nd->used) {
105 qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
106 qdev_set_nic_properties(dev, nd);
107 }
108 qdev_init_nofail(dev);
109 s = SYS_BUS_DEVICE(dev);
110 sysbus_mmio_map(s, 0, base);
111 sysbus_connect_irq(s, 0, irq);
112}
113
114static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
115 bool is_qspi)
116{
117 DeviceState *dev;
118 SysBusDevice *busdev;
119 SSIBus *spi;
120 DeviceState *flash_dev;
121 int i, j;
122 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
123 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
124
125 dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
126 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
127 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
128 qdev_prop_set_uint8(dev, "num-busses", num_busses);
129 qdev_init_nofail(dev);
130 busdev = SYS_BUS_DEVICE(dev);
131 sysbus_mmio_map(busdev, 0, base_addr);
132 if (is_qspi) {
133 sysbus_mmio_map(busdev, 1, 0xFC000000);
134 }
135 sysbus_connect_irq(busdev, 0, irq);
136
137 for (i = 0; i < num_busses; ++i) {
138 char bus_name[16];
139 qemu_irq cs_line;
140
141 snprintf(bus_name, 16, "spi%d", i);
142 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
143
144 for (j = 0; j < num_ss; ++j) {
145 DriveInfo *dinfo = drive_get_next(IF_MTD);
146 flash_dev = ssi_create_slave_no_init(spi, "n25q128");
147 if (dinfo) {
148 qdev_prop_set_drive(flash_dev, "drive",
149 blk_by_legacy_dinfo(dinfo), &error_fatal);
150 }
151 qdev_init_nofail(flash_dev);
152
153 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
154 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
155 }
156 }
157
158}
159
160static void zynq_init(MachineState *machine)
161{
162 ram_addr_t ram_size = machine->ram_size;
163 const char *kernel_filename = machine->kernel_filename;
164 const char *kernel_cmdline = machine->kernel_cmdline;
165 const char *initrd_filename = machine->initrd_filename;
166 ARMCPU *cpu;
167 MemoryRegion *address_space_mem = get_system_memory();
168 MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
169 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
170 DeviceState *dev;
171 SysBusDevice *busdev;
172 qemu_irq pic[64];
173 int n;
174
175 cpu = ARM_CPU(object_new(machine->cpu_type));
176
177
178
179
180
181 if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
182 object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
183 }
184
185 object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
186 &error_fatal);
187 object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
188 &error_fatal);
189 object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
190
191
192 if (ram_size > 0x80000000) {
193 ram_size = 0x80000000;
194 }
195
196
197 memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
198 ram_size);
199 memory_region_add_subregion(address_space_mem, 0, ext_ram);
200
201
202 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
203 &error_fatal);
204 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
205
206 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
207
208
209 pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
210 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
211 FLASH_SECTOR_SIZE,
212 FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
213 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
214 0);
215
216 dev = qdev_create(NULL, "xilinx,zynq_slcr");
217 qdev_init_nofail(dev);
218 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
219
220 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
221 qdev_prop_set_uint32(dev, "num-cpu", 1);
222 qdev_init_nofail(dev);
223 busdev = SYS_BUS_DEVICE(dev);
224 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
225 sysbus_connect_irq(busdev, 0,
226 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
227
228 for (n = 0; n < 64; n++) {
229 pic[n] = qdev_get_gpio_in(dev, n);
230 }
231
232 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
233 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
234 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
235
236 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
237 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
238
239 cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hds[0]);
240 cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hds[1]);
241
242 sysbus_create_varargs("cadence_ttc", 0xF8001000,
243 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
244 sysbus_create_varargs("cadence_ttc", 0xF8002000,
245 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
246
247 gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
248 gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
249
250 for (n = 0; n < 2; n++) {
251 int hci_irq = n ? 79 : 56;
252 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
253 DriveInfo *di;
254 BlockBackend *blk;
255 DeviceState *carddev;
256
257
258
259
260
261
262 dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
263 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
264 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
265 qdev_init_nofail(dev);
266 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
267 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
268
269 di = drive_get_next(IF_SD);
270 blk = di ? blk_by_legacy_dinfo(di) : NULL;
271 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
272 qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
273 object_property_set_bool(OBJECT(carddev), true, "realized",
274 &error_fatal);
275 }
276
277 dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
278 qdev_init_nofail(dev);
279 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
280 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
281
282 dev = qdev_create(NULL, "pl330");
283 qdev_prop_set_uint8(dev, "num_chnls", 8);
284 qdev_prop_set_uint8(dev, "num_periph_req", 4);
285 qdev_prop_set_uint8(dev, "num_events", 16);
286
287 qdev_prop_set_uint8(dev, "data_width", 64);
288 qdev_prop_set_uint8(dev, "wr_cap", 8);
289 qdev_prop_set_uint8(dev, "wr_q_dep", 16);
290 qdev_prop_set_uint8(dev, "rd_cap", 8);
291 qdev_prop_set_uint8(dev, "rd_q_dep", 16);
292 qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
293
294 qdev_init_nofail(dev);
295 busdev = SYS_BUS_DEVICE(dev);
296 sysbus_mmio_map(busdev, 0, 0xF8003000);
297 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]);
298 for (n = 0; n < 8; ++n) {
299 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
300 }
301
302 dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
303 qdev_init_nofail(dev);
304 busdev = SYS_BUS_DEVICE(dev);
305 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
306 sysbus_mmio_map(busdev, 0, 0xF8007000);
307
308 zynq_binfo.ram_size = ram_size;
309 zynq_binfo.kernel_filename = kernel_filename;
310 zynq_binfo.kernel_cmdline = kernel_cmdline;
311 zynq_binfo.initrd_filename = initrd_filename;
312 zynq_binfo.nb_cpus = 1;
313 zynq_binfo.board_id = 0xd32;
314 zynq_binfo.loader_start = 0;
315 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
316 zynq_binfo.write_board_setup = zynq_write_board_setup;
317
318 arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
319}
320
321static void zynq_machine_init(MachineClass *mc)
322{
323 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
324 mc->init = zynq_init;
325 mc->max_cpus = 1;
326 mc->no_sdcard = 1;
327 mc->ignore_memory_transaction_failures = true;
328 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
329}
330
331DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
332
