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21#include "qemu/osdep.h"
22#include "hw/sysbus.h"
23#include "qemu/log.h"
24#include "hw/i2c/aspeed_i2c.h"
25
26
27
28#define I2C_CTRL_STATUS 0x00
29#define I2C_CTRL_ASSIGN 0x08
30
31
32
33
34#define I2CD_FUN_CTRL_REG 0x00
35#define I2CD_BUFF_SEL_MASK (0x7 << 20)
36#define I2CD_BUFF_SEL(x) (x << 20)
37#define I2CD_M_SDA_LOCK_EN (0x1 << 16)
38#define I2CD_MULTI_MASTER_DIS (0x1 << 15)
39#define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
40#define I2CD_MSB_STS (0x1 << 9)
41#define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
42#define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
43#define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
44#define I2CD_DEF_ADDR_EN (0x1 << 5)
45#define I2CD_DEF_ALERT_EN (0x1 << 4)
46#define I2CD_DEF_ARP_EN (0x1 << 3)
47#define I2CD_DEF_GCALL_EN (0x1 << 2)
48#define I2CD_SLAVE_EN (0x1 << 1)
49#define I2CD_MASTER_EN (0x1)
50
51#define I2CD_AC_TIMING_REG1 0x04
52#define I2CD_AC_TIMING_REG2 0x08
53#define I2CD_INTR_CTRL_REG 0x0c
54#define I2CD_INTR_STS_REG 0x10
55#define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
56#define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
57#define I2CD_INTR_SMBUS_ALERT (0x1 << 12)
58#define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11)
59#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10)
60#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9)
61#define I2CD_INTR_GCALL_ADDR (0x1 << 8)
62#define I2CD_INTR_SLAVE_MATCH (0x1 << 7)
63#define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
64#define I2CD_INTR_ABNORMAL (0x1 << 5)
65#define I2CD_INTR_NORMAL_STOP (0x1 << 4)
66#define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
67#define I2CD_INTR_RX_DONE (0x1 << 2)
68#define I2CD_INTR_TX_NAK (0x1 << 1)
69#define I2CD_INTR_TX_ACK (0x1 << 0)
70
71#define I2CD_CMD_REG 0x14
72#define I2CD_SDA_OE (0x1 << 28)
73#define I2CD_SDA_O (0x1 << 27)
74#define I2CD_SCL_OE (0x1 << 26)
75#define I2CD_SCL_O (0x1 << 25)
76#define I2CD_TX_TIMING (0x1 << 24)
77#define I2CD_TX_STATUS (0x1 << 23)
78
79#define I2CD_TX_STATE_SHIFT 19
80#define I2CD_TX_STATE_MASK 0xf
81#define I2CD_IDLE 0x0
82#define I2CD_MACTIVE 0x8
83#define I2CD_MSTART 0x9
84#define I2CD_MSTARTR 0xa
85#define I2CD_MSTOP 0xb
86#define I2CD_MTXD 0xc
87#define I2CD_MRXACK 0xd
88#define I2CD_MRXD 0xe
89#define I2CD_MTXACK 0xf
90#define I2CD_SWAIT 0x1
91#define I2CD_SRXD 0x4
92#define I2CD_STXACK 0x5
93#define I2CD_STXD 0x6
94#define I2CD_SRXACK 0x7
95#define I2CD_RECOVER 0x3
96
97#define I2CD_SCL_LINE_STS (0x1 << 18)
98#define I2CD_SDA_LINE_STS (0x1 << 17)
99#define I2CD_BUS_BUSY_STS (0x1 << 16)
100#define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
101#define I2CD_SDA_O_OUT_DIR (0x1 << 14)
102#define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
103#define I2CD_SCL_O_OUT_DIR (0x1 << 12)
104#define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11)
105#define I2CD_S_ALT_EN (0x1 << 10)
106#define I2CD_RX_DMA_ENABLE (0x1 << 9)
107#define I2CD_TX_DMA_ENABLE (0x1 << 8)
108
109
110#define I2CD_M_STOP_CMD (0x1 << 5)
111#define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
112#define I2CD_M_RX_CMD (0x1 << 3)
113#define I2CD_S_TX_CMD (0x1 << 2)
114#define I2CD_M_TX_CMD (0x1 << 1)
115#define I2CD_M_START_CMD (0x1)
116
117#define I2CD_DEV_ADDR_REG 0x18
118#define I2CD_BUF_CTRL_REG 0x1c
119#define I2CD_BYTE_BUF_REG 0x20
120#define I2CD_BYTE_BUF_TX_SHIFT 0
121#define I2CD_BYTE_BUF_TX_MASK 0xff
122#define I2CD_BYTE_BUF_RX_SHIFT 8
123#define I2CD_BYTE_BUF_RX_MASK 0xff
124
125
126static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
127{
128 return bus->ctrl & I2CD_MASTER_EN;
129}
130
131static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
132{
133 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN);
134}
135
136static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
137{
138 bus->intr_status &= bus->intr_ctrl;
139 if (bus->intr_status) {
140 bus->controller->intr_status |= 1 << bus->id;
141 qemu_irq_raise(bus->controller->irq);
142 }
143}
144
145static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
146 unsigned size)
147{
148 AspeedI2CBus *bus = opaque;
149
150 switch (offset) {
151 case I2CD_FUN_CTRL_REG:
152 return bus->ctrl;
153 case I2CD_AC_TIMING_REG1:
154 return bus->timing[0];
155 case I2CD_AC_TIMING_REG2:
156 return bus->timing[1];
157 case I2CD_INTR_CTRL_REG:
158 return bus->intr_ctrl;
159 case I2CD_INTR_STS_REG:
160 return bus->intr_status;
161 case I2CD_BYTE_BUF_REG:
162 return bus->buf;
163 case I2CD_CMD_REG:
164 return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
165 default:
166 qemu_log_mask(LOG_GUEST_ERROR,
167 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
168 return -1;
169 }
170}
171
172static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
173{
174 bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
175 bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
176}
177
178static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
179{
180 return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
181}
182
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185
186
187static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
188{
189 bus->cmd &= ~0xFFFF;
190 bus->cmd |= value & 0xFFFF;
191 bus->intr_status = 0;
192
193 if (bus->cmd & I2CD_M_START_CMD) {
194 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
195 I2CD_MSTARTR : I2CD_MSTART;
196
197 aspeed_i2c_set_state(bus, state);
198
199 if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
200 extract32(bus->buf, 0, 1))) {
201 bus->intr_status |= I2CD_INTR_TX_NAK;
202 } else {
203 bus->intr_status |= I2CD_INTR_TX_ACK;
204 }
205
206
207
208 bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
209
210
211 if (!i2c_bus_busy(bus->bus)) {
212 return;
213 }
214 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
215 }
216
217 if (bus->cmd & I2CD_M_TX_CMD) {
218 aspeed_i2c_set_state(bus, I2CD_MTXD);
219 if (i2c_send(bus->bus, bus->buf)) {
220 bus->intr_status |= (I2CD_INTR_TX_NAK);
221 i2c_end_transfer(bus->bus);
222 } else {
223 bus->intr_status |= I2CD_INTR_TX_ACK;
224 }
225 bus->cmd &= ~I2CD_M_TX_CMD;
226 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
227 }
228
229 if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
230 int ret;
231
232 aspeed_i2c_set_state(bus, I2CD_MRXD);
233 ret = i2c_recv(bus->bus);
234 if (ret < 0) {
235 qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
236 ret = 0xff;
237 } else {
238 bus->intr_status |= I2CD_INTR_RX_DONE;
239 }
240 bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
241 if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
242 i2c_nack(bus->bus);
243 }
244 bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
245 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
246 }
247
248 if (bus->cmd & I2CD_M_STOP_CMD) {
249 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
250 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
251 bus->intr_status |= I2CD_INTR_ABNORMAL;
252 } else {
253 aspeed_i2c_set_state(bus, I2CD_MSTOP);
254 i2c_end_transfer(bus->bus);
255 bus->intr_status |= I2CD_INTR_NORMAL_STOP;
256 }
257 bus->cmd &= ~I2CD_M_STOP_CMD;
258 aspeed_i2c_set_state(bus, I2CD_IDLE);
259 }
260}
261
262static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
263 uint64_t value, unsigned size)
264{
265 AspeedI2CBus *bus = opaque;
266
267 switch (offset) {
268 case I2CD_FUN_CTRL_REG:
269 if (value & I2CD_SLAVE_EN) {
270 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
271 __func__);
272 break;
273 }
274 bus->ctrl = value & 0x0071C3FF;
275 break;
276 case I2CD_AC_TIMING_REG1:
277 bus->timing[0] = value & 0xFFFFF0F;
278 break;
279 case I2CD_AC_TIMING_REG2:
280 bus->timing[1] = value & 0x7;
281 break;
282 case I2CD_INTR_CTRL_REG:
283 bus->intr_ctrl = value & 0x7FFF;
284 break;
285 case I2CD_INTR_STS_REG:
286 bus->intr_status &= ~(value & 0x7FFF);
287 bus->controller->intr_status &= ~(1 << bus->id);
288 qemu_irq_lower(bus->controller->irq);
289 break;
290 case I2CD_DEV_ADDR_REG:
291 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
292 __func__);
293 break;
294 case I2CD_BYTE_BUF_REG:
295 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT;
296 break;
297 case I2CD_CMD_REG:
298 if (!aspeed_i2c_bus_is_enabled(bus)) {
299 break;
300 }
301
302 if (!aspeed_i2c_bus_is_master(bus)) {
303 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
304 __func__);
305 break;
306 }
307
308 aspeed_i2c_bus_handle_cmd(bus, value);
309 aspeed_i2c_bus_raise_interrupt(bus);
310 break;
311
312 default:
313 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
314 __func__, offset);
315 }
316}
317
318static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
319 unsigned size)
320{
321 AspeedI2CState *s = opaque;
322
323 switch (offset) {
324 case I2C_CTRL_STATUS:
325 return s->intr_status;
326 default:
327 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
328 __func__, offset);
329 break;
330 }
331
332 return -1;
333}
334
335static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
336 uint64_t value, unsigned size)
337{
338 switch (offset) {
339 case I2C_CTRL_STATUS:
340 default:
341 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
342 __func__, offset);
343 break;
344 }
345}
346
347static const MemoryRegionOps aspeed_i2c_bus_ops = {
348 .read = aspeed_i2c_bus_read,
349 .write = aspeed_i2c_bus_write,
350 .endianness = DEVICE_LITTLE_ENDIAN,
351};
352
353static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
354 .read = aspeed_i2c_ctrl_read,
355 .write = aspeed_i2c_ctrl_write,
356 .endianness = DEVICE_LITTLE_ENDIAN,
357};
358
359static const VMStateDescription aspeed_i2c_bus_vmstate = {
360 .name = TYPE_ASPEED_I2C,
361 .version_id = 1,
362 .minimum_version_id = 1,
363 .fields = (VMStateField[]) {
364 VMSTATE_UINT8(id, AspeedI2CBus),
365 VMSTATE_UINT32(ctrl, AspeedI2CBus),
366 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2),
367 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus),
368 VMSTATE_UINT32(intr_status, AspeedI2CBus),
369 VMSTATE_UINT32(cmd, AspeedI2CBus),
370 VMSTATE_UINT32(buf, AspeedI2CBus),
371 VMSTATE_END_OF_LIST()
372 }
373};
374
375static const VMStateDescription aspeed_i2c_vmstate = {
376 .name = TYPE_ASPEED_I2C,
377 .version_id = 1,
378 .minimum_version_id = 1,
379 .fields = (VMStateField[]) {
380 VMSTATE_UINT32(intr_status, AspeedI2CState),
381 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
382 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
383 AspeedI2CBus),
384 VMSTATE_END_OF_LIST()
385 }
386};
387
388static void aspeed_i2c_reset(DeviceState *dev)
389{
390 int i;
391 AspeedI2CState *s = ASPEED_I2C(dev);
392
393 s->intr_status = 0;
394
395 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
396 s->busses[i].intr_ctrl = 0;
397 s->busses[i].intr_status = 0;
398 s->busses[i].cmd = 0;
399 s->busses[i].buf = 0;
400 i2c_end_transfer(s->busses[i].bus);
401 }
402}
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425static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
426{
427 int i;
428 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
429 AspeedI2CState *s = ASPEED_I2C(dev);
430
431 sysbus_init_irq(sbd, &s->irq);
432 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
433 "aspeed.i2c", 0x1000);
434 sysbus_init_mmio(sbd, &s->iomem);
435
436 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
437 char name[16];
438 int offset = i < 7 ? 1 : 5;
439 snprintf(name, sizeof(name), "aspeed.i2c.%d", i);
440 s->busses[i].controller = s;
441 s->busses[i].id = i;
442 s->busses[i].bus = i2c_init_bus(dev, name);
443 memory_region_init_io(&s->busses[i].mr, OBJECT(dev),
444 &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40);
445 memory_region_add_subregion(&s->iomem, 0x40 * (i + offset),
446 &s->busses[i].mr);
447 }
448}
449
450static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
451{
452 DeviceClass *dc = DEVICE_CLASS(klass);
453
454 dc->vmsd = &aspeed_i2c_vmstate;
455 dc->reset = aspeed_i2c_reset;
456 dc->realize = aspeed_i2c_realize;
457 dc->desc = "Aspeed I2C Controller";
458}
459
460static const TypeInfo aspeed_i2c_info = {
461 .name = TYPE_ASPEED_I2C,
462 .parent = TYPE_SYS_BUS_DEVICE,
463 .instance_size = sizeof(AspeedI2CState),
464 .class_init = aspeed_i2c_class_init,
465};
466
467static void aspeed_i2c_register_types(void)
468{
469 type_register_static(&aspeed_i2c_info);
470}
471
472type_init(aspeed_i2c_register_types)
473
474
475I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr)
476{
477 AspeedI2CState *s = ASPEED_I2C(dev);
478 I2CBus *bus = NULL;
479
480 if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) {
481 bus = s->busses[busnr].bus;
482 }
483
484 return bus;
485}
486